JPS5816381B2 - Koukaizoud TV Jiyoungji Yuzuki - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high resolution television receiver.

Television plays an extremely important role in modern society, and is deeply involved in people's daily lives in a wide range of areas, including reporting, education, culture, and entertainment.

It is expected that this trend will continue to increase in the future, but if that happens, people will no longer be satisfied with the current screen,
It can be fully predicted that a time will come in the near future when higher quality images will be desired.

Definition is the most important factor in achieving high definition in television.

Currently, NTSC television broadcasting is being carried out in Japan, and in this system, the number of scanning lines is set at 525.

Taking slide film as an example of resolution standard, 2
It has been reported that simulation results show that a screen size of 0 inches corresponds to the image quality displayed using approximately 2000 scanning lines.

Although we have raised the resolution of slide film as a tentative standard, the limits of what can be achieved are determined by current hardware technology.

A cathode ray tube is one of the currently available display devices for home use, and a high-resolution color cathode ray tube capable of displaying approximately 1000 scanning lines has already been developed.

From this, as a tentative guideline for high-definition TVs, 10
It can be said that a system having about 00 scanning lines is the most effective.

If the number of frames is 30 frames per second and the interlace ratio is 2:1, as it is now, the video bandwidth will be proportional to the square of the number of scanning lines, so a wide bandwidth of about 4 @, or about 16 MH2, will be required. It's coming.

This means that high-definition television broadcasting requires fundamental changes in transmission methods.

In order to solve this problem, the present invention receives an interlaced scanning television signal and performs high-resolution signal processing on the receiver side, without changing the current transmission method. The present invention provides a high-resolution television receiver that enables high-resolution image display.

An embodiment of the present invention will be described below with reference to the drawings.

Figure 1 is a diagram showing the general configuration of the normal NTS
A regular NTSC demodulator 100 receives the C television signal and converts it into video signals Y and I.

Q, a composite synchronization signal HV, and a subcarrier SC, and supply these to the subsequent high-resolution video signal generator 200.

This high-resolution video signal generation device 200 outputs high-resolution video signals R, G, and B, a high-resolution horizontal synchronization signal H', and a high-resolution vertical synchronization signal V', as will be described later.
A high resolution image is displayed on a subsequent display device 300 comprising a high resolution cathode ray tube.

FIG. 2 shows the configuration of the high-resolution video signal generation device 200, in which the input video signals Y, I, and Q each have a low frequency f
The signals pass through the wave generators 10a, iob, and 10c, are sampled and held in the sample-and-hold circuits 20a, 20b, and 20c, and are converted into digital signals by the A-D converters 30a, 30b, and 30c, and each has a memory for subsequent storage. It passes through arithmetic processing units 40a, 40b, and 40c, and becomes high resolution.

It is converted into digital signals y/, I/, and Q/.

Here, the specific method of calculating the high-resolution video signal by the processing units 40a, 40b, and 40c is to use known means such as so-called interpolation or extrapolation from known signals.

, although there are many such interpolation or extrapolation methods,
Examples of interpolation methods include the method described in the proceedings of the 1974 National Conference of the Institute of Electronics and Communication Engineers, entitled "Transmission of Video Telephone Signals by Interpolation Adapted to Contours," and the average interpolation method.

In this embodiment, a video signal on a new scanning line is obtained by a known interpolation or extrapolation method.

After that, the D-A converter 50a, sob, 50c, low frequency r
The signal passes through wave generators 60a, 460b and 60c and enters a matrix circuit 70, from which high-resolution signals R, G, and B are obtained as outputs.

On the other hand, the high-resolution synchronization signal generator 80 uses the composite synchronization signal HV obtained from the NTSC demodulator 100 to
Using the usual method, the horizontal and vertical synchronization signals are separated and phased.
While obtaining a high-resolution horizontal synchronizing signal H/ having two frequencies using a locked loop <PLL) etc.,
As will be described later, a vertical synchronizing signal whose phase is delayed by a time corresponding to 1/4 of the horizontal scanning period is generated every other vertical scanning period, and this signal is used as a high-resolution vertical synchronizing signal V/.

In addition, the high-resolution synchronization signal generation device 80 generates a clock pulse by multiplying the subcarrier SC obtained from the demodulation device 100 by 12@ using means such as PLL, and based on this, each Sampling pulses and other control pulses are obtained.

In this case, the Y, I, and Q bands are 6 each, 4MH2, IMH2
, 0, 5 MH2, etc., and the sampling frequency of each signal is selected to be 3 times, 1 times, and 1/3 times the subcarrier of 358 MHz.

FIG. 3 shows the configuration of the arithmetic processing unit 40a for the video signal Y, but the arithmetic processing unit 40a for the I and Q signals differs only in the period of the clock pulse.
Since the configurations and operations of 0b and 40c are completely equivalent, only the arithmetic processing unit 40a for the Y signal will be described.

In FIG. 3, reference numeral 41 denotes a memory changeover switch, which switches input signals in the order of a, b, and c in synchronization with a horizontal synchronizing signal.

42, 43, and 44 are memories each having a storage time corresponding to IH (one horizontal scanning period), 45 is an associated processing circuit section, and 46 is a control section.

First, in FIG. 3, when the contact of the changeover switch 41 is in the a position, the input signal is output to the memory 42, which is referred to as A.

Sequentially, take notes corresponding to the B and C positions of the changeover switch!
J43 and J44 have IH signal ports, and 8 is activated.

Again, the transfer switch returns to position a and the cycle repeats.

Next, the case of reading signals from memory will be explained.

Assuming that the signal C is now being written into the memory 44, the contents A of the memory 42 are first read out at twice the writing speed.

The time required for this is 1/2H.

During the next 1/2 time, the contents 490 of the memories 42 and 43 are read out while being averaged by the processing circuit section 45, and a high-resolution digital video signal Y' is output.

In other words, the processing circuit section 45 processes the contents of the memories 42 and 43.

By interpolating or extrapolating the mouth,
A high-resolution digital video signal Y' is derived.

Of course, the processing method is not limited to simple arithmetic averaging; it is also possible to adopt a method of performing weighted averaging in consideration of the statistical properties of the image.

FIG. 4 is a time chart for explaining this situation, in which a represents a video signal (analog) and b represents a digitized video signal.

c, d, and e are memories 42 and 43 in FIG. 3, respectively.
It represents the contents of the write and read signals of .degree.44.

410 DEG C.2 shown in this time chart is an image signal for continuous IH minutes. In the diagram, the hatched period indicates the memory write mode, and the horizontal line period indicates the read mode.

By sequentially performing writing and reading in this manner, it is possible to generate a high-resolution digital video signal Y' with improved image quality.

Similarly, high-resolution digital video signals I/, Q/ are obtained corresponding to the I and Q signals, and Y/, I/, Q/
The high-resolution video signals R and G are transmitted through the above-mentioned path.

B is output.

A display device 300, which will be described later, receives high-resolution video signals R, G, and B, a high-resolution horizontal synchronization signal H', and a high-resolution vertical synchronization signal V', and displays 1050 high-resolution images.

Next, using FIGS. 5 to 9, high-resolution synchronization signals used in the high-resolution television receiver of the present invention will be explained.

The generator, particularly its high-resolution vertical scanning circuit, will be described.

FIG. 5 is a diagram for explaining scanning in a high resolution television receiver according to the present invention.

The numbers in the figure are the numbers within one screen (=one frame) of scanning lines.

In the figure, a shows the scanning state before scan conversion, and b shows the scanning state after scan conversion.

In order to maintain the 2:1 interlace relationship before scan conversion even after scan conversion, it is necessary to perform scanning as shown in FIG. 4.

In the figure, the scanning lines numbered with / are newly replaced by scan conversion and calculation.

By scanning as shown in the figure, a high-resolution image can be displayed.

FIG. 6 is a diagram for explaining the function of the scanning circuit.

In the figure, C indicates a vertical synchronization signal, and d indicates a horizontal synchronization signal after scan conversion.

e indicates the vertical sawtooth wave signal of the deflection stop corresponding to C, and f indicates e in order to complete the scanning shown in Fig.
This shows a vertical sawtooth wave signal, that is, a high-resolution vertical scanning signal, after correcting the waveform of .

g is a correction signal waveform that is superimposed on e in order to change e to f; this is a rectangular wave that is synchronized with the vertical synchronization signal of C and has half the frequency.

h is the waveform of another correction signal for changing e to f,
This is not a direct correction of e, but a correction of the vertical synchronization signal C.

FIG. 7 is a timing chart for explaining the operation of the scanning circuit shown in FIGS. 8 and 9.

FIG. 8 is a block circuit diagram showing an example of a scanning circuit used in the present invention.

The following description will be made with reference to FIG. 1.

In FIG. 8, a vertical synchronizing signal C and a horizontal synchronizing signal i before scan conversion are applied to an odd-even field discriminator 81 to generate an odd-even field discriminating signal k.

The correction waveform generator 82 generates a correction signal g whose phase is shifted from the vertical synchronization signal C and the odd-even field discrimination signal by a time corresponding to 1/4 of the horizontal scanning period every other vertical scanning period, that is, a high-resolution vertical signal. Generates synchronization signal V/.

After this signal is made to an appropriate signal level by a waveform shaper 83, it is converted from a vertical synchronizing signal C to a vertical sawtooth wave generator 84.
It is superimposed on the vertical sawtooth wave signal e generated by the superimposition device 85 to drive the vertical deflection coil.

FIG. 9 is a block circuit diagram showing another example of the scanning circuit.

The following description will be made with reference to FIG. 1.

In FIG. 9, a quadruple multiplier 86 generates a signal j having a frequency of four times the horizontal synchronizing signal i before scan conversion, which is synchronized with the horizontal synchronizing signal.

The delay device 87 generates a delayed synchronization signal l which is synchronized with the vertical synchronization signal C and delayed by one cycle of the signal j, which is four times the horizontal synchronization signal.

On the other hand, using the correction signal g explained in FIG.
8, 1/1 horizontal scanning period corresponds to the odd-even field.
A correction signal, that is, a high-resolution vertical synchronization signal V' is created by switching between a vertical synchronization signal delayed by a time corresponding to 4 and a vertical synchronization signal that is not delayed.

This correction signal f is applied to the vertical sawtooth wave generator 84, and the generated vertical sawtooth wave signal f drives the vertical deflection coil.

In the above embodiments, a case has been described in which an NTSC television signal is displayed as a high-resolution image, but the present invention can also be applied to other interlaced scanning television signals, and can also be used to display color images. Not limited to signals,
Needless to say, this method is also effective in the case of black and white video signals.

As described above, according to the high-resolution television receiver of the present invention, high-resolution images can be easily produced by applying arithmetic processing and scan conversion techniques without making any changes to the current television broadcasting system such as the NTSC system. can be displayed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic configuration of an embodiment of the present invention, FIG. 2 is a block circuit diagram of a high-resolution video signal generator which is a feature of the present invention, and FIGS. A block circuit diagram showing an example of the arithmetic processing device in the figure and a time chart showing its operation, FIG. 5 is a diagram for explaining scanning of the high-resolution television receiver of the present invention, and FIG. 6 is used in the present invention. FIG. 7 is a waveform diagram to explain the function of the scanning circuit, FIG. 7 is a timing chart to explain the operation of the scanning circuit used in the present invention, and FIGS. 8 and 9 are different examples of the scanning circuit used in the present invention. It is a block circuit diagram showing. Note that the same reference numerals in the figures indicate the same or corresponding parts. 100... NTSC system demodulation device, 200... High resolution video signal generation device, 300... Display device, 40 a, 40 b, 4 D c... Arithmetic processing unit, 42.43, 44...・Memory, 80...
・High resolution synchronization signal generator.

Claims (1)

[Scope of Claims] 1. A demodulation device that receives an interlaced scanning television signal and outputs a video signal, a horizontal synchronization signal, and a vertical synchronization signal; a memory, an arithmetic processing device that reads the stored contents of the plurality of memories at a speed of 2@ at the time of storage and performs arithmetic processing such as interpolation or extrapolation to derive a high-resolution video signal, the horizontal synchronization signal and the vertical synchronization signal; Upon receiving the signal input, a high-resolution horizontal synchronizing signal having a frequency of 2 @ and a high-resolution vertical synchronizing signal whose phase is delayed by a time corresponding to 1/4 of the horizontal scanning period every 1 vertical scanning period are generated. A high-resolution television receiver comprising: a high-resolution synchronization signal generating device; and a display device that displays a high-resolution image in response to input of the high-resolution horizontal synchronization signal and the high-resolution vertical synchronization signal. Machine.