JPH01274581A - Convergence correcting circuit - Google Patents

Abstract

PURPOSE:To prevent production of color shear over the entire picture by providing a means generating a symmetrical triangle wave and obtaining a color deviation correction data of an even order number of the triangle wave from the arithmetic means of the color deviation correction data of an odd number order. CONSTITUTION:A high-order bit of a signal 19 inputted to a PC 3 generates a bit X corresponding to a horizontal representative grating point and sends it to a VIP 6. Moreover, the low-order bit generates an address signal 21 and a control signal 23 and an inverter 13 and a data selector 14 generate a triangle wave having a period being twice the representative grating points. The control signal 23 generates a bit X subject to vertical interpolation by the signal 20 at the VIP 6 corresponding to the current 19 as an odd or even number color deviation correction data. Furthermore, the signal 23 is inputted to selectors 7, 14 to supply the address signal and the color deviation correction signal to converters MDA1(8), 2(9) in response to the odd or even number. Then the correction data of the even order number in the correction data is obtained from the arithmetic mean of the odd number order data to prevent the production of color deviation over the entire picture.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital convergence correction circuit for a display using a CRT, and is suitable for use in a multi-scan projection display.

[Conventional technology]

In a projection display, three projection tubes of red, green, and blue are generally arranged horizontally together with a projection lens to project and synthesize a color image onto a single screen. Since the red and blue images are projected obliquely onto the screen, trapezoidal distortion as shown in FIG. 2 occurs based on projection geometry, resulting in color shift.

In order to correct this color shift, a convergence yoke (hereinafter abbreviated as CY) for electron beam auxiliary deflection, similar to a deflection yoke, is conventionally mounted on the neck of the projection tube and the output of the convergence amplification section is applied to CY. The color shift was corrected. The correction signal applied to CY is:
It is desirable to be able to synchronize with the deflection scanning period and correct the dark brown shift pattern with high precision. There are two types of correction waveform generation means: an analog system and a digital system. The analog type is
Although it was simple, it had the drawback of poor accuracy. Although the digital method has high correction accuracy, it has the drawback of requiring a large memory capacity and being therefore expensive. In order to reduce the required memory capacity, the screen is represented by approximately 16 x 16 representative points,
Only the correction information of the representative point is memorized.

A method of interpolating the remaining area from representative point data is described in US Pat. No. 4,422,019 (registered in 1983) and Japanese Patent Publication No. 61-55310. The convergence signal generation circuit described in the above-mentioned conventional example performs interpolation in the horizontal direction of the screen using a normal LPF, and performs interpolation calculation digitally or analogously in the vertical direction to create a correction signal. However, although this type of conventional technology is suitable for one specific scanning format, it is suitable for so-called multi-scan displays that can display multiple formats with different horizontal frequencies and screen sizes. When applied, it has the disadvantage of requiring a large amount of memory capacity. Therefore, for example, even if correct correction can be made in one format, if the horizontal frequency of the display is slightly changed, color shift may occur.

In addition, when obtaining a convergence correction signal in a conventional projection display, the correction waveform has opposite polarity for red and blue, but in either case, it is necessary to obtain a waveform that is synchronized with the deflection scanning period. Ta.

In the prior art, as described in Japanese Patent Publication No. 61-15631, for example, there is a method in which a sawtooth-shaped horizontal deflection current is detected as a voltage signal by some means, and a waveform is synthesized based on this signal. It was used.

This conventional method has a problem in that color misregistration remains at the left end of the screen. The reason for this will be explained next. The waveform synthesis process requires a finite delay time, and the delay time is usually about 2% to 3% of the horizontal scanning period. Since the CRT displays the screen by horizontal and vertical scanning, the left end of one screen corresponds to the position immediately after high-speed horizontal blanking.

Since the correction signal information arrives here with a delay, color misregistration remains in a portion of about 2 to 3% of the entire screen width at the left end of the screen.

SUMMARY OF THE INVENTION An object of the present invention is to overcome the drawbacks of the prior art described above and to provide a horizontal interpolation method that can accommodate a wide variety of formats with a small memory capacity.

Another object of the present invention is to reduce the color shift.

Still another object of the present invention is to apply a weighted average circuit that utilizes analog multiplier means in place of a conventional horizontal interpolation LPF to reduce the color shift by adapting to various signal sources having different horizontal scanning frequencies. This can be achieved at low cost by combining the means and the weighting coefficient generating means and by creating a structure that is resistant to variations in multipliers.

The above purpose is to assume a coordinate system with a virtual scanning line number several times the number of the format that requires the maximum number of scanning lines among the formats to be supported, and to synchronize the virtual scanning line number with the input vertical synchronization signal. PLL means including programmable counter means for counting within one vertical period, and means for controlling the count number of the programmable counter means within one vertical period to be approximately proportional to the vertical size of the screen,
This is achieved by providing means for performing interpolation calculations in the virtual scanning line coordinate system from representative point data.

The color shift at the left edge of the screen is overcome by generating a magnification correction waveform based on a preceding sawtooth wave generation means independent of the deflection current. The leading sawtooth wave causes the center of gravity of the waveform of the scanning period to precede the deflection current by an amount equivalent to the delay time of the subsequent convergence signal processing amplifier circuit.

Furthermore, although it is not an essential requirement, it is desirable that the waveform of the preceding sawtooth wave during the retrace period is intentionally distorted in order to transmit the position information of the left edge of the screen to the subsequent convergence signal processing amplifier circuit as quickly as possible. .

[Effect]

The weighting coefficient generation circuit means operates to generate a triangular wave with a period twice the representative grid interval, and the weighted average circuit means calculates each color shift of adjacent left and right representative grid points based on the triangular wave. It operates to weight-average the correction data to obtain a weighted-average output.

In addition, by introducing a virtual scanning line coordinate system that has several times the number of actual scanning lines, the accuracy of scanning line position estimation is improved, so irregular brightness unevenness on the playback screen caused by rounding deviation in position estimation is improved. The effect is that interference (details will be described later) can be suppressed within the permissible range. Therefore, it is possible to continuously correspond to formats having different numbers of scanning lines. Further, changes in screen size can be continuously responded to by using the PLL means provided with the programmable counter means.

Therefore, unlike conventional devices, color misregistration does not occur.

Furthermore, by generating the correction waveform as described above, the information applied to the convergence output section becomes exactly matched in time. Therefore, the problem of residual color shift at the left end of one screen can be overcome, and color shift over the entire screen can therefore be eliminated.

〔Example〕

Now, a first embodiment of the present invention is shown in FIG.

The configuration and operation of the figure will be explained below.

1 is a phase detector, 2 is a voltage controlled oscillator with a frequency of 1.6 M)Iz, and 3 is an 8-bit programmable counter (PC) whose output 14 is a pulse of about 64K)Iz. The output 14 of the PC 8 is negatively fed back to the phase detector 1 and compared in timing with an input horizontal synchronizing signal at the input 18 or a horizontal retrace pulse generated in a separate horizontal deflection circuit, and the entire circuit functions as a well-known PLL loop. The repetition frequency f, 4 of the input horizontal retrace pulse signal changes from 16 KT (z to 80 KHz depending on the signal source), so the oscillation frequency of the voltage controlled oscillator 2 (hereinafter abbreviated as vCO) is approximately 4 MI. (Varies from z to 20MHz.

The programmable counter 3 (hereinafter abbreviated as PC) divides the frequency twice, and has the same frequency as the input f, and the timing is also the same as the input f,
Outputs an output pulse 24 that matches the .

The amplitude PP (peak-to-peak) of the signal 19 proportional to the horizontal deflection current is detected by the envelope detection circuit 4, and a DC voltage is obtained at the output end of the envelope detection circuit 4. This DC voltage has a voltage value proportional to the horizontal size of the screen.

The DC voltage is converted into an approximately 7-bit digital signal by the AD converter 5. The AD converter 5 does not need to be an expensive one that sequentially digitizes high-speed alternating current signals; instead, a well-known inexpensive commercial product that simply converts a direct current voltage into a digital value can be used. In the drawings of this specification, a multiplex line means a flow of a digital signal, and a single line means a flow of an analog signal or a 1-bit digital signal.

Now, a digital signal representing the horizontal screen size output from the AD converter 5 is applied to the program terminal of the PC 3 as described later. PC3 is an up counter that counts up from O to 27-1, and has a first part whose counting start point is programmable, and an up counter that counts up from O to (2'-1) following the counting of the first part. and a second part whose counting end point is programmable.

In other words, + PC3 as a whole consists of one 8-bit clock whose count start point and count end point are each programmable.
Equivalent to a bit counter.

The 7 bits at the end of the count in the second part of the PC3 contain A.
The output of D converter 5 is set.

Also, at the count start point of the first part, the AD converter 5
The one's complement of the output of is set. Therefore, for example, when the horizontal size becomes large, the first part of PC3 starts counting up from a number closer to the lower limit O of the starting point than when the horizontal size is small, and the second part starts counting up from a number closer to the lower limit O of the starting point than when the horizontal size is small. The count ends with a number close to the upper limit (2'-1) of the end point as the starting point, and the output pulse 24 is output at the moment of completion.
At the same time as , the count returns to the number at the starting point and starts counting up again.

The information of each bit of PC3 is s b on the virtual scanning line coordinate system.
It is used as an address signal for its.

The upper 4 bits correspond to 16 or less representative grid points sampled horizontally on the screen.

The upper 4 bits of the horizontal address signal are applied to a well-known vertical interpolation processor (VIP) 6 together with a vertical address signal 20 generated by a separate means. The VIP6
includes EPROM means in which data for approximately 16.times.16 representative grid points is stored and in which the data may be rewritten by known techniques. Furthermore, the VIP6
includes well-known means for producing as output vertically interpolated color shift correction digital data. In addition, the VI
Although not shown, the lower bits of the horizontal address are also applied to P6, which serves as a timing clock for digital processing. The output of the VIP 6 is applied to the data selector 7. A separate input 23 is applied to the control terminal of the selector 7 in the data selector. The separate input 23 is the least significant (LSB) signal of the upper 4 bits of the horizontal address, and when this is 1, the data selector 7 is connected to the odd side output terminal 7a, and when it is 0, it is connected to the odd side output terminal 7a. It is connected to the even side output terminal 7b. Odd.

Each even output is connected to a DA converter with a multiplier MDAl (8
), applied to MDA2 (9). said MDA1(8),
As the MDA2 (9), for example, AD1508 manufactured by Analog Devices, Inc. can be used. These analog outputs are added together by an adder 10, passed through an amplification section 11, and then connected to a coil 12 of a convergence yoke. coil 1
The current flowing through 2 provides additional deflection of the CRT's electron beam and provides the necessary color shift correction.

On the other hand, the lower four bits 21 of the horizontal address signal are connected to the low-side input terminal 14 a of the data selector 14 and also to the inverter 13 .

The output of the inverter is connected to the odd-side input terminal 14b of the data selector 14. The output of the data selector 14 is the value (Il) of the control human power 23 input to its control terminal.
Corresponding to o), the signal of the odd/even input terminal is obtained at its output. The output of the data selector 14 is the DA converter 1
5. The above-mentioned MD is used as the DA converter.
A1(8) It is possible to use the upper 4 bits of the same bit. A pair of analog current outputs are taken out from the output of the DA converter. Moreover, the DA converter 15 is configured so that the sum of the pair of output currents is constant. The previously described AD1508 has this property, but
If this is not available, an ordinary 1-output DA converter and an operational amplifier that inverts its output can be used. In any case, the pair of complementary current outputs is connected to the current mirror circuit 16.
17, and is applied to the analog multiplication terminals of MDA1 and MDA2.

Inverter 13. The operation of the data selector 14 will be explained. Although the signal 21 is actually a 4-bit address signal, it will be explained as a 2-bit signal for ease of understanding.

If this signal is X, the output of the inverter 13 is X, and the output 22 of the data selector 14 is A, it can be expressed as follows.

Control input 23 0.0.0.0.1.1.1.1.0.
0...x 00,01,10,11,00,01
,10,11,00,01...x 11,10,
01,00,11,10,01,00,11,10
・-・A 00,01,10,11,11,10,01
, 00, 00, 01... That is, it can be seen that the output A is a triangular wave that rises when the signal from the control human power 23 is 0 and falls when it is 1.

Next, the symbol Is in FIG. 1, 16.17.8.9. The parts marked with will be explained. The waveform of the positive output current of the DA converter 15 in FIG. 1 is shown in A in FIG.
It is. This represents the above-mentioned property that the value of X increases after passing through a certain even number and reaches the next odd number, and decreases when the value of X passes through a certain odd number and reaches the next even number. This positive output current is applied to the multiplication terminal of the multiplication type DA converter MDA1 (8) via the current mirror circuit 16. The waveform of the output signal of M D A l (8) is the waveform of one solid line shown in section D in FIG. That is, it can be seen that the waveform is obtained by horizontally interpolating the data of the representative grid point where X=odd number.

On the other hand, the other complementary output of the DA converter 15 is applied to M D A 2 (9) via the current mirror circuit 17, and the output waveform of M D A 2 (9) is 2 as shown in D2 in FIG. The waveform becomes a heavy solid line. This waveform is a waveform obtained by horizontally interpolating the data of representative grid points where X=even. Finally, the output of the adder 10 in FIG. 1 has the point m in FIG.
A signal with a waveform shown by Ds is obtained. Therefore, a desired waveform can be obtained by horizontally interpolating the data of each representative grid point.

According to the configuration shown in FIG. 1 described above, it is possible to correct color shift by continuously following various formats having different horizontal scanning frequencies f and horizontal screen sizes.

This is because the change in fK requires the phase detector 1. V
It can be tracked by the action of PLL consisting of CO2 and PO2, and envelope detection is used to detect changes in horizontal screen size. AD5. PO2
This is because the configuration allows the count start point and count end point to be tracked as described above.

In the prior art, as a means for horizontal interpolation, an analog type low-pass filter was simply used, and the fact that its impulse response was triangular wave-like was utilized. However, since the duration of the triangular wave was constant, it was necessary to prepare a plurality of LPFs and switch between them for formats with different horizontal deflection speeds.

In this embodiment, when the horizontal deflection speed changes, the period of the triangular wave changes accordingly, and as a result, the distance width corresponding to the period of the triangular wave on the screen can be kept constant, so continuous tracking is possible. I was able to pass it.

In addition, prior art (USP4422019 and Japanese Patent Publication No. 1983-
No. 55310) describes that a multiplication type DA converter is used not for horizontal interpolation, which is the object of the present invention, but for vertical interpolation inside the portion of VIP 6 in FIG. However, these conventional techniques do not show anything corresponding to the inverter 13 in FIG. 1 of this embodiment. Therefore, the manner in which the address signal of the lower 4 bits of the output terminal 22 changes is not a triangular wave with rising and falling parts symmetrical to each other at 2 grid intervals as shown in FIG.
It has a sawtooth wave shape that instantly resets and descends at each grid interval. When this format is attempted to be used for the purpose of horizontal interpolation, it has the drawback of generating correction unevenness interference, as described below. That is, in this format, the groove side of the data selector 7 in FIG. 1 is changed to the left side adjacent grid point data, and the odd side is changed to the right side adjacent grid point data.

Therefore, in MDA 1 (8) and MDA 2 (9),
Even data and odd data appear alternately at every grid interval.

Therefore, MD A 1 (8) and MD A 2 (9)
Even if there is a slight mutual deviation between the respective conversion gains, disturbances occur on the screen as changes in the amount of electron beam deflection near the lattice points.

In particular, when the electron beam is auxiliary deflected in the vertical direction by the compassence yoke 12, there is a problem in that the scanning line waves in a sawtooth shape. This means, for example, a sawtooth wave shape as shown by the dotted line in FIG. This figure shows that ripples occur even when the correction data itself is always a constant value. Therefore, in the type of the prior art, it was necessary to adjust the gains of the DA converters with analog multipliers corresponding to MDAI(8) and MDA2(9) very precisely.

In the configuration of FIG. 1, MDAI (8) is operated by the newly devised inverter 13.

Since the requirement for the gain deviation of M D A 2 (9) is significantly relaxed, no adjustment is required.

This is because MDAI (8) only handles data corresponding to odd addresses, and MD P,2 (9) only handles data corresponding to even addresses, so the gain deviation can be corrected by rewriting the correction digital data itself in VIPe. This is because it can be easily corrected.

Another advantage of the configuration shown in FIG. 1 compared to the conventional technology is 1MDAI (8).

An advantage of this method is that it is resistant to transient glitch interference when the output analog value of MDA 2 (9) 8 changes suddenly. This is because in FIG. 3, for example, MD A 1
(8) is at the timing of X=4.

The color shift correction data corresponding to X=3 is switched to the color shift correction data corresponding to X=5. At this timing of X=4, the weighting coefficient of MDA 1 (8) is in a state of zero as shown by the single solid line in FIG. Therefore, glitch interference is suppressed.

Although the VIP 6 in FIG. 1 is shown as a digital processing system in this embodiment, it is also possible to apply the above-mentioned analog interpolation method that is resistant to variations to the vertical interpolation function of the VIP 6. This will be described later as a separate modification.

Now, we have finished explaining the advantages of the configuration shown in FIG. 1, and next we will discuss some remaining disadvantages and their solutions.

First of all, it is important to note that the value of the 8-bit address where PO2 in Figure 1 is generated is not on the howling cyclic coordinate system, and is not on the howling cyclic coordinate system, but from the end point to the start point at the start of horizontal retrace. This means that it should be considered to be on a non-howling reference frame that is cut and reset. In the conventional digital convergence system, PC3k! Always O
It was treated as a circular coordinate system that counted from 26-1 to 26-1. In the circular coordinate system, the delay time for digital signal processing in the VIP 6 can be easily overcome by simply cyclically shifting the address value by an amount corresponding to the delay. This is because the starting point and the ending point are just two points adjacent to each other on the suitable coordinate system.

However, on the non-fateful coordinate system, the starting point and the ending point are completely different points located at the extremes.

Therefore, in FIG. 1, it is necessary that the timing of starting counting of PO2 is at least as much as the delay time of the processing system ahead of the timing of starting horizontal scanning from the left edge of the screen.

In the circuit of FIG. 1, what is the timing relationship between the address value of the output of PO2 and horizontal deflection scanning?

The waveforms are as shown in FIG. 7, with the horizontal axis representing time t. In the figure, 25 indicates a horizontal deflection position or horizontal deflection current, and 28 indicates an address output value. As can be seen from the figure, the timing to start counting precedes the timing to start horizontal scanning by the water width period Tr. On the other hand, the delay time of the processing system in FIG. 1 is incidentally ΔX=
It can be seen from the previous explanation regarding FIG. 3 that there is a delay of one minute.

This corresponds to approximately π of the horizontal period. On the other hand, the horizontal retrace period Tr mentioned above is about τ of the horizontal period.

In addition, there is a slight delay in the VIP 6 part and the processing amplification unit 11 part in FIG. However, the total delay time is typically less than 100 horizontal periods. Therefore, the above requirements are met. Therefore, the operation is close to the desired one. However, it is still a little far from the ideal.

There are two typical sufficient conditions to get close to the ideal. These address values are shown by dotted line waveforms in FIGS. 5 and 6. In both figures, the horizontal axis is time t, and waveform 25 is the seventh
This is the same as waveform 25 in the figure. The common characteristic of FIGS. 5 and 6 is that in the rising process of the waveform, that is, in the horizontal scanning period,
This means that the address value precedes the scanning movement of the electron beam by 8t times. This Δ
t is set approximately equal to the total delay time of the convergence circuit. T r in the same figure.

ΔA will be described later.

FIG. 8 shows a second embodiment. This is to obtain the address value waveform shown by the dotted line in FIG. This figure mainly shows the parts that are different from FIG. 1. Other parts are the same as in FIG. The operating waveforms in the same figure are
As shown in the figure.

The waveforms of a, b, a, d, and e are shown in a of FIG.

These are waveforms at points b, c, d, and e.

In FIG. 8, DL1 at 29 and DL2 at 30 are pulse delay circuits. DL, 29 delays the signal by a time approximately equal to the delay time described above for VIP6, MDAI (8), and MDA2 (9) in FIG. The delay time is
Since the clock period is a certain integer multiple, the DL engineer 29 has V
It can be configured as a shift register type in which the timing shown in FIG. 10 is shifted using the output signal of CO2 as a clock.

DL230 is for correcting the delay in the analog amplifier section 11 in Figure 1, which is usually about 0.1-1μ9e.
The magnitude of e is a fixed value that does not depend on the format of the input signal. Therefore, as the DL 230, a mono-multivibrator whose pulse width is matched to the delay amount can be used. MM31 is a mono-multivibrator whose pulse width is set equal to or slightly less than the retrace period Tr of the horizontal deflection circuit. The output pulse of the MM31 is applied to the disable terminal of PO2, and PC3 suspends counting during this period. Therefore, the waveform of each part is the first
It will be as shown in Figure O at b+ Ct dt e. The waveform of this e is the same as the desired dotted line 26 in FIG.

Next, FIG. 9 shows a third embodiment. In the figure, 29°30 is the same as in FIG. 32 is an amplitude detector that detects the minimum value corresponding to the left edge of the screen of the horizontal deflection sawtooth wave 19 as a DC voltage, and 33 is a 7-bit AD converter whose output is converted into one's complement for each bit by an inverter. After that.

It is supplied to PO2 and the count start point of PO2 is set. 34 is an amplitude detector for detecting the maximum value of the horizontal deflection sawtooth wave, the output of which is added to the output of the frequency detector 7;
The signal is supplied to PO2 via the AD converter 36, and the count end point of PO2 is set. Each part a, b, a in Fig. 8,
, e are as shown in FIG. Therefore, it can be seen that the horizontal address signal e having the waveform indicated by the dotted line 27 in FIG. 6 is obtained.

The function of the FMDET 37 is to correct the amount of ΔA shown in FIG. Even if the horizontal scanning frequency f of the input signal increases, the multi-scan display generally operates in such a way that the retrace period of the horizontal deflection circuit remains constant and only the scanning period changes.

Therefore, the magnitude of ΔA in FIG. 6 increases in proportion to fK. Therefore, FMDET 37 and adder 35 in FIG.
It can be seen that this ΔA can be compensated for by the action of .

D E Ta2.34 can be constructed by a well-known amplitude detection circuit using a diode and a capacitor. Further, as the FMDET 37, a well-known pulse count type frequency detector can be used.

Although the above three embodiments have been described, intermediate variations between these embodiments are also possible, and some of the functions can also be replaced by a microcomputer.

Next, FIG. 12 shows a fourth embodiment in which the latter half of FIG. 1 is modified. In the same figure, 3.6.13.14.15°23 is the first
Same as the figure. 38 is a DA converter.

39 is a sample and holder. Odd data D is obtained at the upper output of 39, and even data D2 is obtained at the lower output. 40 is a weighted average circuit. If the output is D3, the weighting coefficient is W, and it is given by the following equation.

D, ccWD2+ (1-W)Dl -...■W
If the differential voltage applied to the base electrodes of the upper four transistors of 40 is E, then the following formula % Formula % Here, k: Boltzmann's constant T: Absolute temperature T: Absolute temperature q: Electron charge kT □Cape 60 m V Therefore, the PP value of the triangular wave-like differential voltage E is approximately ±100 m
If V is selected, since ±100 mV 2 0.03, the desired weighted value of W=1 to 0 can be obtained. Therefore, the weighted average circuit 40 outputs horizontally interpolated color shift correction data.

This concludes the explanation of the fourth embodiment, and a modification of the simplification according to the application will be described.

In applications where the horizontal screen size is constant f, the PO2 counting start and end points can be fixed. That is, in that case, the PC 3 does not need to be a programmable counter, and may simply be a counter from 0 to 2s-1.

Also, there is no need to continuously change the horizontal screen size,
In applications where only a few types of switching are required, the count start point and end point can be set and switched simply by a mechanical switch or a microcomputer.

In the second (FIG. 8) and third (FIG. 9) embodiments, although not shown in both figures, the 15.16.17° 8.9.
The part corresponding to 10 is a digital weighted average circuit and D
It can be replaced with A converter.

- As an example, an embodiment combined with FIG. 8 is shown in FIG. 13 as a fifth embodiment.

In the same figure, 1.2.3.4.5.18, 19, 29, 30.
The portion 31 is the same as in FIG. Also, 6, 7, 13
The portions ゜14, 20.23.11.12 are the same as in Fig. 1. Inverter 41 is used to obtain digital values of triangular waves of complementary polarity. 42.43. is a digital multiplier, 44 is a digital adder, and 45 is a DA converter. The operation is a weighted calculation similar to that of the formula described above.

In the fifth embodiment, in current digital technology, the multiplier 42
．． 43 is more expensive than the type shown in FIG. 1, but it is presumed that technological progress will result in a more advantageous configuration.

Even in that case, each delay element 29, 30, . The plow is considered to be an important technology for realizing continuous tracking digital convergence circuits.

Next, the luminance unevenness disturbance that occurs when the number of data bits is insufficient will be explained.

−m is the size of the lowest digit of the digitized data.
S B (Least 51gn1ficant B
it), a rounding error of ±1/2LSH must occur. Generally, the allowable limit for color shift deviation is about 1 pixel (a pixel is the smallest unit that makes up a screen, and corresponds to the scanning line interval in the vertical direction. In the present invention, the screen has a maximum size of about 1000 pixels). It is assumed that the display is composed of 1,000 x 1000 pixels (ultra high-definition displays for CAD/CAM applications almost fall under this category), and the detection limit is approximately 0.25 pixels. Therefore, the deviation -LSB is 0.2
It is desirable that the number of pixels be 5 or less.

On the other hand, the maximum amount of color shift between green and red that should be corrected (equal polarity between green and blue) is determined by the concentration angle ω shown in FIG.
It is approximately proportional to the horizontal angle of view α. Maximum vertical deviation P
When the P value is L and the height of the screen is H, the following relationship exists.

L: ωtanα +H”-・・■ As an actual example, ω=o, 1rad, tanα=0.5
Substituting, L40.05 XH=50 h ・・・・・・■
Here, h is the size of one pixel, h=-, that is, about 50 pixels. This color shift deviation can be reduced to about 177, ie, about 7 hours, by a separate analog convergence circuit.

This needs to be further reduced by a digital convergence circuit. Therefore, if the maximum range that the digital convergence circuit should handle is M, then M47h ...... ■ From the color shift detection limit mentioned above, I L S B = o, sh
Therefore, the required number of bits n of digital data is calculated as follows.

h n41og2--log214 #4...
... ■ o, s5 That is, approximately 4 bits seems to be sufficient.

However, unfortunately, this is a necessary condition, not a sufficient condition. It is true that 4 bits is sufficient accuracy for the color shift itself, but there is also the problem of brightness unevenness caused by rounding errors. This occurs because the gaps between sample points are no longer uniform. That is, the brightness appears to be high where the scanning lines are dense, and the brightness appears to be low where the scanning lines are sparse. this is.

This is especially noticeable on monochromatic screens, such as red. The visual detection limit for brightness unevenness based on the unevenness of scanning line density is extremely severe, being about 3% in terms of relative change in density.

Therefore, the magnitude of LSH is 0.0000000000, which satisfies the color shift detection limit.
Instead of 5 hours, it needs to be within 0.03 hours, which satisfies the brightness unevenness limit.

Therefore, the required number of bits is: 0.03h 1 LSB≦0.03h . . . , approximately 8 bits are required.

Therefore, in the prior art, it was common to use 8-bit digital data.

Now, FIG. 14 shows a sixth embodiment of the present invention for preventing the color unevenness described above. The configuration and operation of the figure will be explained below.

1 is a phase detector, 2 is a voltage controlled oscillator with a frequency of 240 KHz, and 3' is a 12-bit programmable counter whose output 14 is approximately 607 pulses, which is negatively fed back to the phase detector 1 and input to the input 11. Input vertical sync signal or
The timing is compared with a vertical retrace pulse generated in a separate vertical deflection circuit, and the whole operates as a well-known PLL loop. The repetition frequency fv of the input vertical synchronization signal is 40H
Since it changes from z to 12011Z depending on the signal source, the voltage controlled oscillator (hereinafter abbreviated as vCO) of 2 changes from about 160 to 480 K&, and 3
A programmable counter (hereinafter abbreviated as PC) output pulse 14 is obtained.

Now, the digital signal representing the vertical screen size output from the AD converter is applied to the program terminal of the PC 3' as will be described later. PC3' is an up counter that counts up from 0 to 211-r, and is PO2 in FIG.
Similarly, the first part is programmable for its counting start point.

Next, this is followed by a second part which is an up counter that counts up from O to (2''-1) and whose counting end point is programmable.

The output of the AD converter 5 is set to the upper 7 bits of the 11 bits at the count end point of the second part of the PC 3', and the remaining lower bits are always set to 0. Furthermore, the one's complement of the output of the AD converter 5 is set in the upper seven bits of the count start point of the first part. Furthermore, 1 is set in the remaining lower bits. Therefore, for example, when the vertical size increases, the first part of PC3' starts counting up from a number closer to the lower limit O of the starting point, and the second part starts counting up from a number closer to the upper limit (211-1) of the ending point. At the same time, the count ends and 47 output pulses are generated at that moment.

Return to the number at the starting point and start counting up.

The information of each bit of PC3' is 12 on the virtual scanning line coordinate system.
Used as a bits address signal.

The upper 4 bits correspond to the representative grid points within 16 sampled in the vertical direction of the screen.

This is separately generated by the same means as before.
bits horizontal address signal (each address from 0 to 15 corresponds to a sample point obtained by dividing the screen width into 16 or less) is applied to six EPRPMs (electrically rewritable memories) 40. The EPROM40 has 16X
Data corresponding to each of the 16 sample points is stored. (This data can be rewritten using a separately known means.) Each piece of data is stored in two pieces of 4. The first 4 bits correspond to data for correcting color shift at adjacent sample points on the screen, and the second 4 bits correspond to data for correcting color shift at adjacent sample points on the screen.
its corresponds to data of sample points adjacent to the top and bottom of the screen.

These data are transferred from the EPROM to the upper adjacent data 4 in the same figure.
5. The upper adjacent data 46 is read out to the signal line. These total 8 bits of information are stored in the vertical interpolation ROM.
The ROM 41, which is applied as an address input to the read-on memory 41, has 12 points on the virtual scanning line coordinate system.
The information of the remaining lower 8 bits in the address signal of bits is also applied as an address signal to the ROM 41.

Therefore, the total number of addresses is 24 x 24 x 21''': 64. Each address stores <IByte of data based on the interpolation formula. Therefore, the total capacity is 64 KB.
It is te.

The interpolation formula is as follows.

Dy, 11=DY, 4+ (DY+1.4- DY-4)
-22 atmosphere...■ Coconi, Dy, 8: ROM output (7) 8 bits data y is the value DY of the lower 8 bits of the vertical address, 4: The input data Y of 4 bits of the upper adjacent sample is the upper vertical address 4 bits value DY+1
, 4: 4-bit input data of upper adjacent sample Next, the relationship between virtual vertical scanning line coordinates and luminance unevenness, which is the core of this embodiment, will be explained.

In formula (2), y is an integer number, and the size of LSH is 1.

On the other hand, from the already stated formula ■, the maximum value of the values in parentheses of formula ■ is M
= 7h. Therefore, the size ε of the LSB in the output Dy, g is i = 7 h X −= 0, 027
h...[Phase] 25 is found to just satisfy the brightness unevenness detection limit specification of equation (2).

On the other hand, as with the prior art, if a coordinate system with approximately 1000 lines/screen height, which is almost the same as the actual number of scanning lines, is selected, then 1
The number of scan lines in the sample interval is approximately 70, so the formula [
The ε value of the phase] is about 0.1 h, and therefore, the luminance unevenness becomes extremely noticeable. Therefore, the prior art has been problem-free only in so-called single scans with a fixed vertical frequency and a fixed vertical size.

In the single scan method based on the conventional technology, a coordinate system of the actual number of scanning lines is adopted, and therefore, 1. in FIG.
The elements 2.3' and 4.5 did not exist, and instead of 3', the system counted the actual number of scanning lines using a counter that simply counted horizontal retrace pulses, that is, a scanning line number counter. Therefore, in principle, there is no problem with counting accuracy i, e or rounding error. Instead, for different formats with different numbers of scanning lines and vertical screen sizes, different EFROM data, different RO
Required for M interpolation.

In this embodiment, it is possible to automatically follow a wide range of formats using a set of EPROM and ROM interpolation. This is because an unreliable real scanning line coordinate system that changes depending on the format is discarded, and a virtual scanning line coordinate system having about four times as many lines is used.

Returning to FIG. 14, the output of the ROM 41 is transmitted to the DA converter 42 and becomes an analog signal.
3 to the convergence coil 12, where C
The RT electron beam is auxiliary deflected to correct color shift. The processing amplification section 43 includes well-known LPF means for horizontal interpolation.

Here, smoothing interpolation is performed between the 16 samples in the horizontal direction. Further, the processing amplification section 43 includes a well-known analog convergence circuit, and coarse correction can be performed by the analog convergence circuit.

Although only one set of circuits is shown in the figure, the degree of freedom for color shift is four-dimensional, that is, vertical/horizontal correction is required for each of red and blue, so the blocks after 40 in Figure 14 are Four sets of each are required. This concludes the description of the sixth embodiment of the present invention.

Next, we will discuss some modifications.

The ROM 41 in FIG. 14 can be replaced with a digital multiplier and adder that performs the operations of 20.

The parts 1, 2, 3' and 4.5 in Fig. 14 are conventionally used when a high-speed (approximately 480K) (z sampling rate) and high-precision (approximately 12 bits) AD converter becomes available. A converter converts the 19 input signals into a 12-bit digital signal, which can be used as an address signal.

EPROM41 in FIG. 14 is E2PROM (Elect
Rally Erasable and Prog
rammable ROM).

The output from the EPROM in FIG. 14 is any set of 3 to 15 sets of upper adjacent data instead of 2 sets of upper adjacent data, and the well-known Lagrange's calculation formula is used instead of the linear interpolation formula (■). Interpolation polynomial, Hermite
A piecewise curve interpolation formula based on the interpolation polynomial can be used. Alternatively, Whittaer's interpolation formula, which is a mathematical model of an ideal low-pass filter, can be used. (Refer to page 32 of Electronic Communication Handbook, Ohmsha 1974 edition) When using the curve interpolation formula, ROM4
Since the capacity of 1 is large, it is advantageous to use a digital arithmetic unit.

As a prerequisite for the explanation of the embodiment shown in FIG. (Omitted) The required number of bits for data in the EPROM 40 is 7 bits, and the required number of bits for input to the DA 42 is 11 bits. In this case, even in the case of linear interpolation, the required number of addresses in ROM41 is 27X2'
X2”=2”=4M address, which is very large, so RO
It is appropriate to use a digital arithmetic unit instead of M.

In general, the required number N of virtual scanning line coordinate systems required for the present invention is set from the following equation by reversing the equation [phase].

N≧(Number of samples in vertical direction) Maximum value of difference in required correction amount between adjacent samples × Size of LSH at luminance unevenness detection limit (11) In the description of the sixth embodiment, 0. 03 h = 4096 = 2" ... (12). Even in the last modification mentioned above, formula 5 [phase]
Since the term 7h in the middle of is considered to be almost unchanged (described later), in calculating the number of required addresses mentioned above, 2' = 256
was used.

This is because, as can be understood from Figure 2, the maximum value of the difference in the required correction amount between adjacent samples is greatest at the top or bottom of the screen, and its size is calculated by dividing 50h in equation (■) into 15 sample points. This is because it is estimated to be approximately 3.3 hours when divided by , and 7 hours is considered to be sufficient even if other unknown factors are included.

Conversely, in the explanation of the sixth embodiment, the difference 7h in the required correction amount between the upper and lower adjacent samples used in the formula [phase] is
It can be said that this corresponds to the worst case in which the performance of the analog convergence circuit included in the processing amplification section 43 in FIG. 14 is considerably poor. However, even if the performance of the analog convergence circuit is excellent, in an economically and industrially reasonable configuration, 7h in the equation [phase] cannot be changed to 4.
It is quite difficult to make it less than h. Therefore, the minimum number of virtual scanning line coordinate systems required is approximately twice the assumed number of actual scanning lines, 1000.

Next, FIG. 15 shows a seventh embodiment of the present invention.

In the same figure, the parts numbered 1, 2.3', 11, 12.14 are the same as in FIG.

Reference numeral 17 denotes a mono-multivibrator, the output pulse width of which is set to be approximately equal to the separately mounted deflection retrace pulse width. During the period PC3' of this pulse width, the counting operation is stopped. By doing this, the output address signal of the PC 3' stops changing during the retrace period, and when the electron beam returns to the top of the screen, its counting starts.

DET 48 is an amplitude detector that detects the positive peak of the input vertical deflection sawtooth signal, that is, the size of the top edge of one screen, as a DC voltage. The output of this is: A count start number of PC 3' is set via AD converter 49.

Further, the DET 50 detects the negative peak as a DC voltage, and similarly sets the count end number of the PC 3' via the AD converter 51.

Note that the same purpose can be achieved by replacing the upper and lower end detection with the same PP value detection and average value detection as in FIG. 14, and by using an arithmetic circuit. . In this embodiment, the followability to the scanning format of the input signal is slightly improved compared to the sixth embodiment.

In both the sixth and seventh embodiments, the DET and AD portions can be omitted in applications where it is only necessary to support formats in which the vertical screen size is approximately constant. In this case, the PC need not be a programmable counter, but may simply be a counter that is reset every vertical period.

In addition, in an application example in which the vertical screen size and the number of vertical scans are almost constant, and only the horizontal scanning frequency and horizontal screen size change for each format, 1.2, 4 in Figure 14
．． 5 may be omitted, PC3' may simply be a counter that is reset every vertical period, and a substantially fixed frequency signal source may be used in place of vCO2. Even in such an application example, since the number of scanning lines differs depending on the format, this embodiment is effective.

FIG. 16 shows an eighth embodiment of the present invention. 3'' in the figure is the same as PC3' in FIG.

53 in the figure is a microcomputer with a built-in register. 54 is a variable frequency signal source, and a microcomputer 53
The frequency of the output signal is controlled so as to be approximately proportional to the average speed of vertical scanning. A terminal 55 is a digital signal for setting the count start number of the programmable counter 3''. 56 is a vertical retrace pulse signal, and the trailing edge of the pulse, ie, the end point of the vertical retrace.

That is, at the start of vertical scanning, the PC3'' is reset and returns to the original starting number to continue counting.The above 54 variable frequency signal sources may be composed of, for example, a fixed oscillator with a sufficiently high frequency and a variable frequency division counter. This can be easily realized using well-known techniques.The digital output of the counter is the first
Connected to the circuit shown in Figure 4. In the above embodiment.

It is possible to accommodate formats with different vertical screen sizes and vertical deflection speeds using a register memory of extremely small capacity.

A ninth embodiment of the present invention is shown in FIG.

In the same figure, 2.3" and 48.51 are the same as in FIG. 153. In the figure, 12 is a signal corresponding to the vertical deflection current.5
7 is a differentiating circuit which obtains a voltage proportional to the vertical deflection speed at its output. 58 is a negative side amplitude detector. The negative amplitude is proportional to the so-called vertical deflection speed during the vertical scanning period.

In proportion to this, the frequency of vCO2 and the counting speed of PC3'' are controlled and reset by the edge after 56 vertical retrace pulses to obtain approximately the desired address output at the output of PC3''.

According to the embodiments of the present invention described above, EPROM
It is possible to realize a digital convergence circuit that can handle the required memory capacity to a minimum, and its industrial value is high.

Next, generation of a correction waveform for preventing residual color shift at the left end of the screen will be explained based on the tenth embodiment of the present invention shown in FIG. . The operation shown in FIG. 19 will be explained together with the corresponding waveform diagram in FIG. 19.

A horizontal retrace pulse is applied to the input 11 of the phase detector 1. The output of the phase detector 1 is applied to a frequency control terminal of a voltage controlled oscillator 2 (hereinafter referred to as VCO). vC
The oscillation output of O is a seven-nostable multivibrator (
60 tris (hereinafter abbreviated as MM) are applied to the input terminal.

The output pulse width Tr' of MM60 is horizontal retrace pulse 18
It is selected to be smaller than the retrace period width Tr by ΔTr. In normal use, ΔTr is selected to be approximately the transient response time (approximately 1 to 2 times the rise time) of the subsequent convergence signal processing amplification section 70. The MM6
The output of 0 is applied to the input of the pulse delay circuit 61.

The delay time τd of the pulse delay circuit 61 is selected to be approximately equal to the delay time of the subsequent convergence signal processing amplification section 70. The delayed pulse 68 is negatively fed back to the phase detector 1.

1, 2.60.61 collectively form a PLL loop. As a result of the PLL operation, the delayed pulse output 68 is
As shown in FIG. 9, the timing of the rising edge portion is aligned with the rising edge of the input horizontal retrace pulse. Therefore, at the input side 19 of the pulse delay circuit 61, as shown in FIG. 3, a leading pulse whose rising edge is preceded by the pulse delay amount τd is obtained. This pulse is transmitted to inverter 6
2. The output PP value of the inverter 62 is proportional to its power supply voltage Vcc, and is proportionally controlled by separately controlling the Vcc. The control output pulse is applied to an integrator 63 to obtain a horizontally periodic sawtooth wave 69 at its output. The timing of waveform 69 is as shown in FIG. The amplitude of the sawtooth wave is detected and held by a PP value detector 64. Another PP value detector 65 applies a sawtooth voltage proportional to the horizontal deflection position to its input, and detects and holds the amplitude lpp value corresponding to the horizontal screen size. A horizontal deflection current can be substituted for the sawtooth voltage proportional to the horizontal deflection position. The deviation of the outputs of the PP value detectors 64 and 65 is differentially amplified by a comparator and amplifier 66, and the LPFI
0, the power supply voltage of the inverter 62 described above is controlled by negative feedback. As a result of the negative feedback effect, the amplitude of the output sawtooth wave is
It can be made according to the horizontal screen size. The output sawtooth wave passes through the convergence signal processing amplification section 70 and becomes CY
12 to correct and control the position of the electron beam of the CRT, and as a result, the color shift is corrected as a whole including the left edge of the screen. Although only one CY is shown in the figure, four are normally used (red top, bottom, left and right, blue top, bottom, left and right).

When the present invention is applied to a digital convergence circuit using digital technology, the value of the delay time τd is usually larger than the above-mentioned 2 to 3% of the horizontal period (the time required for digital data transfer processing is Therefore, the delay time of the pulse delay circuit is selected accordingly. In addition, the digital address signal for specifying the horizontal coordinate of the electron beam on the screen is the output sawtooth wave 69 in Figure 1.
can be obtained by digitizing with an AD converter.

This is shown in FIG. 20 as an eleventh embodiment.

In the same figure, the input of the AD converter 21 is 6 in FIG.
A leading sawtooth wave shown at 9 is provided. A digitized approximately 8-bit address signal is output from the AD converter 21. The maximum address number corresponding to the left edge of the screen is outputted from the maximum value detection circuit 72.

The digital multiplexer 73 receives the auxiliary input signal 19, that is, the preceding retrace pulse shown in FIG. The maximum address is selected during the period when is 11 LI+. Therefore, the multiplexer 73
At the output 24 of , a preceding address signal corresponding to the waveform 74 shown in solid line in FIG. 21 is obtained. The reason why the second half of the same waveform, which has a shorter retrace period, is made to match the address at the left end of the screen is to minimize the influence of transient vibrations of the convergence amplification section at the left end of the screen.

In the same figure, programmable read-only memory (FROM)
75 stores data for color shift correction at each address. The address of the FROM 75 is determined by a separate vertical coordinate designation address 76 and the horizontal address 74, and digital data is obtained at the output end of the FROM 75.

The data is converted into an analog signal by the DA converter 77, and amplified by the amplifier 78. The amplified signal disables CY, and finally the color shift on the screen is corrected. In the above description, the functions of the maximum value detection circuit 72 and the multiplexer 23 are processed in the digital signal domain, but they can also be processed in an analog manner in the analog signal 74 domain. Note that, as is generally known, the amount of information delay accompanying digital processing is proportional to an integral multiple of the clock period. Therefore, in addition to the delay caused by the fixed delay element 61 shown in FIG. It can automatically match and follow changes in the horizontal scanning period. This concludes the explanation of the first embodiment.

Next, the convergence signal processing amplification section 70 in FIG.
A twelfth embodiment is shown in FIG. 22, in which the reference numeral 69 is the same as the preceding horizontal sawtooth wave 69 in FIG. 19, and the reference numeral 79 is a vertical sawtooth wave. Although not shown in the figure, the current flowing through the vertical deflection coil is extracted as a voltage across the series-connected resistor by a well-known means. Two signals, a preceding horizontal sawtooth wave 69 and a vertical sawtooth wave 79, are input to the multiplier 80, and output is the multiplication result of the surface input signal. The multiplier 80 may be ICMC-1495L manufactured by Motorola, USA. The circuit of this embodiment further includes a gain adjustment circuit 81, a negative feedback power amplifier 82, a vertical convergence yoke (V-C
It includes an inductance L of Y), a stray capacitance of v-cy C185, and a damping resistor R□84. This circuit corrects the trapezoidal distortion shown in FIG. 2 by scaling it in the vertical direction. By the way, since this negative feedback circuit causes the current flowing in Ro to follow the input waveform, the current flowing in actual v-cy is I□
Then, 〈〉 is a form obtained by reducing Io by filtering, as shown in the following equation.

Here, p=jw An example of a constant in this case is shown below.

L1=301LH, C1=120p F, R,=16
0ΩR0=1Ω,', τ=LlG,:60o+μsec, 2ζ
#1.6 Corresponding to the above, the cutoff frequency fc in equation (13) is C.

Further, the closed loop bandwidth of the negative feedback amplifier 82 is normally about 0.8 MHz, and correspondingly, the delay of the current T0 itself with respect to the input is about 0.3 μsec, and the rise time is about 0.6 μsec. .

Therefore, the total delay time of the circuit shown in FIG. 22 is approximately 0.4μ92C as the sum of the above factors. Also, the total rise time follows the rms law.

(0,2μ5ec)”+(0,6μ5ec)”40.6
It becomes 3μSeC. The rise time of the staircase response can be considered as the main transient oscillation time of the zo-system. Therefore, τd and ΔTr' in FIG. 19 described above are each set as follows.

This concludes the explanation of the upper half of FIG. 22, and next the lower half of FIG. 22 will be explained. The lower half is red.

This is to correct the color shift of the blue vertical line (so-called linearity distortion).

In the figure, the output 96 of the multiplier 87 has a waveform shown in FIG. 23 96. Gain adjustment section 88. Maximum value detection holding circuit 9
4. The analog switch 95 obtains the output shown in the waveform 96 in FIG. 23 in accordance with the H and L of the horizontal preceding pulse 19 in FIG. 18 already described. That is, the sharply changing portion within the horizontal retrace period is flattened. Otherwise, the tracking speed of the subsequent negative feedback amplifier section 89 will not be able to catch up. (Since it is an inductance load, overvoltage saturation will occur if the current changes suddenly.) 90 is the horizontal convergence yoke H-C
Point Y. Code 91.92.93 is already mentioned 84, 85.8
Refers to the same thing as 6.

In the prior art, an integrating circuit was simply used as the means for creating the parabolic wave in the lower half of FIG. 22, but in such a configuration, waveform 98 in FIG. 23 is obtained, so There was no need to use the blanking period flattening circuit shown at 94.95 in FIG. However, this integration method has the disadvantage that it cannot follow changes in the number of horizontal scans f, because, for example, when fK is halved, the output amplitude of the integration circuit is attenuated by half, and as a result, color shift occurs. This is because half of it remains. The method shown in FIG. 22 overcomes this drawback.

The specific configuration of the maximum value detection and holding circuit 94 shown in FIG.
As shown in the figure. The maximum value is detected and held by the transistor 89 and capacitor 100 within the dotted line in the figure. The conduction potential difference between the pace emitter of the transistor 99 is approximately equal to the potential difference between the base and emitter of the emitter follower 101, and the value of the capacitor 100 is set to approximately 10 mμF or more so as to maintain the maximum value during the horizontal retrace period. Select.

This concludes the explanation of the tenth embodiment. Figures 18 and 20
In the figure, there is only one convergence output section each.

In Figure 22, only two are shown, but in reality there are at least four in total (top and bottom in red).

left and right, blue top and bottom, left and right).

Next, a simplified modification of the eighth embodiment is designated as a thirteenth embodiment, and its essential parts are shown in FIG. ' instead of input to the inverter 62. That is, the first
This is an example in which 1.2.64 in FIG. 8 is omitted. Input 11 in the figure is the horizontal retrace pulse shown at 11 in FIG. 26, which is the same as 11 in FIG. Output pulse 1
As shown at 19' in FIG. 26, the rising portion of 9' is made to match the input, and the falling portion is set by MMIO2. The pulse @Tr' is K than the pulse width Tr of the input pulse.
Just narrow it down. The value of K is selected to be approximately twice the delay time τd of the subsequent amplifier.

As can be seen by comparing the waveform diagram in FIG. 3 corresponding to the eighth embodiment with this FIG. It is to take the lead. As can be seen by substituting the numerical example in equation (15) above, in the first embodiment, the pulse width reduction of the preceding pulse is 0.63 μsec, while in the embodiment of Mizui 11, it is 0.63 μsec. This is a decrease of 8 μsec. As the pulse width decreases, the subsequent amplification section must perform a retrace operation within a short time, which is therefore disadvantageous. However, since the difference is relatively small in the above example, the eleventh example also has practical value.

A further simplified plan including the remaining circuitry in FIG. 18 is shown in FIG. 27 as a fourteenth embodiment.

In the figure, the circuits numbered 11 and 102 have the same function as in Figure 25, and the circuits numbered 62, 63, and 69 are the 18th circuit.
It works the same as those in the figure. FIG. 28 shows a specific example of this amplitude detection and holding circuit 103. Amplitude detection holding circuit 1
03, the capacitor 104. diode 105,
PP amplitude detection circuit 106° capacitor 107, resistor 10
8 forms a holding circuit, transistors 109, 110,
Resistors 111 and 112 form an emitter follower buffer/diode temperature compensation circuit. The PP value of the horizontal retrace pulse human power 11 is detected as a DC voltage at the output.

Therefore, the output pulse PP value of the inverter 62 in FIG. 27 is equal to the input retrace pulse PP value. Therefore, the output of the integrator 63 provides a desired sawtooth wave output proportional to this. In the configuration of FIG. 27, the elements 64, 65, 66, and 67 in the configuration of FIG. 18 are replaced by elements 103.

In addition, in Fig. 27, the input pulse does not include a DC component (
For example, if it is a pulse transformer output) format, D
E T 103 can be replaced by the maximum value detection circuit 94 shown in FIG.

As another modification of the present invention, as a means for compensating for the delay time of the convergence processing amplifier section, instead of leading the waveform to the main horizontal deflection current waveform, a delay means (
Substantially the same effect can be obtained by delaying the signal by an integral multiple of the horizontal period - the delay time. The present invention encompasses such modifications. Such a delay means is not suitable for analog elements because it is large-scale, but it is industrially applicable for digital elements.

In the above description, the effects of the present invention have been mainly explained from the viewpoint of color misregistration correction accuracy, but it will be noted below as a supplementary explanation that there is also a power saving effect as an incidental effect of the present invention. In FIG. 22, that is, the twelfth embodiment, V-CY8
3, a current containing a sawtooth wave component with a horizontal period flows.

Therefore, the current waveform is differentiated and a pulse voltage is generated at both ends of v-cy, that is, at the output of the amplifier section 82. In the prior art, this pulse waveform was similar to the horizontal retrace pulse 11 in FIG. This is because, as is well known, the horizontal deflection circuit freely oscillates for half a period during the horizontal retrace period, so that the result of processing based on the deflection current waveform is necessarily sinusoidal. On the other hand, in the present invention, as can be seen from the waveform examples shown in FIGS. 19 and 26, the pulses are shaped into rectangular pulses. Therefore, the correction current waveform flowing through v-cy in FIG. 19 has a horizontal period of 1! As you can see, it is a linear sawtooth wave similar to the waveform 69 in FIG. 19, and the corresponding output voltage waveform is a square pulse.

As a general property, in order to change the current flowing through the inductor L by a predetermined amount rpp, it is necessary to apply a voltage-time product of a predetermined value LIρP. Therefore, if the pulse durations are assumed to be equal to each other, a voltage peak amplitude of -41.57 times that of the sine wave is required to cause a change of a predetermined LIp.rho. It is necessary to select a higher power supply voltage for the amplifying section 32 by that amount. Therefore, the power consumption of the power source becomes 1.57 times as large, and it can be seen that the present invention can conversely achieve a power saving effect.

Of course, there is a disadvantage in terms of power as the pulse width is narrowed, but this is a much smaller ratio than 1.57.

〔Effect of the invention〕

According to the present invention, color shift at the left end of the screen of a display can be corrected with high precision. Therefore, a higher definition image can be projected over a wider screen range. Therefore, for example,
It has high industrial value when applied to computer graphics displays with more than 1 million pixels.

According to the present invention, it is possible to realize a digital convergence circuit that can accommodate various signal source formats having different numbers of scanning lines while minimizing the required memory capacity of the EPROM.

According to the present invention, for various signal source formats,
Since it is possible to configure a digital convergence circuit that can continuously track and correct color shift, it becomes possible to use the display in a variety of application fields.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. FIG. 2 is an explanatory diagram showing the pattern of color shift, FIG. 3 is a waveform diagram of the main part of the embodiment shown in FIG. 1, FIG. 4 is an explanatory diagram showing the second embodiment of the present invention, and FIG. FIG. 6 is a waveform diagram for explaining the third embodiment of the present invention; FIG. 10 is a waveform diagram for the fourth embodiment; FIG. 11 is a waveform diagram for the fifth embodiment.
FIG. 12 is a circuit diagram showing the main part of the fourth embodiment. FIG. 13 is a circuit diagram showing the main part of the fifth embodiment. FIG. 14 is a circuit diagram showing the main part of the fifth embodiment. 15 is a circuit diagram of the sixth embodiment of the present invention, and FIG. 15 is a main part circuit diagram of the seventh embodiment of the present invention.
6 is a circuit diagram of the main part of the eighth embodiment of the present invention, FIG. 17 is a circuit diagram of the main part of the ninth embodiment of the present invention, and FIG. 18 is a circuit diagram of the main part of the 10th embodiment of the present invention. Figure 20 is a waveform diagram of the main part of the tenth embodiment of the present invention. Figure 20 is a circuit diagram of the main part of the eleventh embodiment of the invention. Figure 21 is a waveform diagram of the main part of the eleventh embodiment of the invention. FIG. 22 is a circuit diagram of the main part of the twelfth embodiment of the present invention. FIG. 23 is a waveform diagram of the main part of the twelfth embodiment of the invention. Circuit diagram FIG. 25 is a circuit diagram of a main part of a thirteenth embodiment of the present invention. FIG. 26 is a waveform diagram of a main part of a thirteenth embodiment of the present invention. FIG. FIG. 28 is a specific circuit diagram of the amplitude detection and holding circuit shown in FIG. 27. 1... Phase detector, 2... Voltage controlled oscillator, 3゜3
1.311... Programmable counter, 4... Crossover detector, 5... AD converter, 6... Color shift correction data generation circuit, 8, 9...: DA converter with multiplier, 12 ...-convergence yoke, 13: inverter, 15: DA converter. 16.17... Current mirror circuit 6... EPROM, 7... ROM, 8... DA converter, 9... Processing amplifier section, 10... Convergence yoke, 37... Frequency detector , 40...
EPROM, 41...ROM, 42...DA converter, 43. . . . processing amplification unit, 52. 60 . . . mono multivibrator, 53 . . . microcomputer, 54. variable frequency signal source, 57. ... Differential circuit, 5
8... Negative side amplitude detector, 61... Delay circuit, 62...
...Inverter, 63...Integrator. 64.65...pp value detection holder, 66...comparison amplifier, 70...convergence signal processing amplifier section, 7
2... Maximum value detection circuit, 73... Multiplexer,
75...Programmable ROM Figure 1 7□4 Fu C to - σσ'-O Momo 3, 4 Figures, 1st flash, 8th Figure 4, 7th Figure 10th figure, 14th flash of tr diagram Hing/'? Figure 22 Figure 23 Figure 27 Figure 103 A3

Claims (10)

[Claims] (1) A display device equipped with a CRT, which performs analog interpolation in the horizontal direction of the color shift correction amount of the remaining points based on digital data for color shift correction corresponding to representative grid points ordered in the horizontal direction of the screen. In this type of display device, there is provided a triangular wave generating means for generating a symmetrical triangular wave having a period twice the interval of the representative grid points; A convergence correction circuit comprising: weighted average circuit means for obtaining weighted average of color shift correction data; (2) a multi-scan display using a CRT, a color shift correction data storage means for storing color shift correction data at representative lattice points of about n x m in length and width on the screen;
comprising a correction data generating means for generating color misregistration correction data for the remaining points from the color misregistration correction data based on an interpolation principle;
A display that performs convergence correction, comprising address signal generating means for generating a vertical address signal as a digital signal based on a virtual scanning line number coordinate system having a number of scanning lines that is twice or more the number of scanning lines of a signal source, The address signal generating means generates an address signal in synchronization with vertical scanning and supplies it to the color misregistration correction data storage means, and the correction data generating means reads the address signal from the correction data storage means based on the address signal. A digital convergence correction circuit that vertically interpolates the color shift correction amount of a point on a vertical line passing through the representative grid point from the color shift correction data at the representative grid point. (3) The digital convergence correction circuit according to claim 2, wherein the address signal generating means comprises a counter means, and the difference between the count start point and the end point of the counter is set to be approximately proportional to the screen size. (4) In claim 2, the LSB of the data at the representative grid point is set to a small number of necessary bits as a rough size that is close to the color shift detection limit, and the LSB of the data at the representative grid point is vertically interpolated from a point on a vertical line passing through the representative grid point. LSB of data
is a digital convergence correction circuit that has a small size and a large number of bits that correspond to the brightness unevenness detection limit. (5) In a display device using a CRT, a convergence yoke means for color shift correction, a processing amplification means for driving the yoke, and a horizontal sawtooth signal generation means for supplying a horizontal sawtooth wave to the processing amplification means. , wherein the sawtooth signal generating means generates a preceding sawtooth wave of a horizontal scanning period that precedes the main horizontal deflection sawtooth current by a period approximately equal to the delay time of the processing amplification means. correction circuit. (6) The convergence correction circuit according to claim 5, wherein the amplitude of the preceding sawtooth wave is made substantially proportional to the horizontal double-sided size. (7) Claim 5, characterized in that the retrace period width of the preceding sawtooth wave is narrower than the retrace period width of the main horizontal deflection by a period approximately equal to the transient response time of the processing amplification means. convergence correction circuit. (8) The convergence correction circuit according to claim 5, wherein the value of the retrace period of the preceding sawtooth wave is held at a value corresponding to the left edge of the screen. (9) The convergence correction circuit according to claim 5, wherein the processing amplification means includes squaring means for squaring the preceding sawtooth wave, and the squared output corrects color shift of vertical lines on the screen. (10) In claim 5, the horizontal sawtooth signal generating means is selected to be approximately equal to an integer multiple of the horizontal period minus the delay time of the processing amplification means for the main horizontal deflection sawtooth signal. A convergence correction circuit comprising means for delaying a period of time.