JPH05183917A - Digital convergence device - Google Patents

Abstract

PURPOSE:To realize high-accuracy digital convergence with small circuit scale and a data memory for correction even when an input horizontal frequency is changed over a wide range by controlling the adjusting point of the convergence corresponding to the horizontal input frequency and interpolating corrected data by a horizontal interpolating filter. CONSTITUTION:This device is provided with a horizontal frequency detection circuit 32 for the horizontal frequency inputted to a receiver, plural interpolating filters to interpolate and calculate the corrected data of the convergence for one horizontal period, selector 52 to switch the interpolating filters 51, and means 50 to control the selector 52. Corresponding to the detected horizontal frequency, the number of the adjusting points of the digital convergence is controlled, only the corrected data at a prescribed adjusting point among those adjusting points are stored in a corrected data memory 3 and concerning remaining corrected data, the corrected data are obtained by calculating them at real time. Namely, since the corrected data are interpolated by the interpolating filters 51, the data stored in the memory 3 and the positions of the adjusting points are always fixed regardless of the horizontal frequency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CRT type digital convergence apparatus for correcting color deviations of color images.

[0002]

2. Description of the Related Art FIG. 14 shows a configuration example of a digital convergence device in a multi-scan type three-tube video projector. In the figure, 1 is an input terminal for correction data and 2 is an address for writing the correction data in a memory. Input terminals, 3 is a memory for storing convergence correction data, 4 is a serial-parallel conversion circuit for converting 6-channel (hereinafter referred to as 6CH) serial data read from the memory into 6CH parallel data, and 5 is a serial-parallel conversion circuit. A D / A converter that converts the digital data output from 4 into an analog correction signal, 6 to 8 are low-pass filters (hereinafter referred to as LPFs), 9 is a selector that selects LPFs 6 to 8, and 10 is an amplifier for amplifying the correction signal. Amplifier, 11
Is a convergence yoke for giving a correction magnetic field to the electron beam of the receiver, 12 is D / A per correction signal 1CH
The conversion block and blocks 13 to 17 are the same as the D / A conversion block 12, respectively. 18 to 22 are the same convergence yokes as the convergence yoke 11, 23 is an input terminal of an erase pulse (hereinafter, referred to as H-BLK pulse) in a horizontal blanking period, 24 is an input terminal of a window signal for measuring a horizontal frequency, Reference numeral 25 is an input terminal of an erase pulse (hereinafter, referred to as V-BLK pulse) in a vertical blanking period, 26 is a phase comparator, 27 is a loop filter, 28 to 30 are voltage controlled oscillators (hereinafter, referred to as VCO), and 31 is VCO
A selector for selecting 28 to 30; 32, a horizontal frequency detection circuit for detecting the input horizontal frequency by the H-BLK pulse input from the input terminal 23; 33, based on the information obtained by the detection circuit of the horizontal frequency detection circuit 32. , A circuit for generating a control signal for controlling the selector 31 and 34 is a memory 3
A horizontal address generation circuit at an adjustment point for reading out the correction data stored in, and a vertical address generation circuit 35 are also provided.

Next, the operation will be described. When projecting a signal source whose input horizontal frequency (fH) changes from 15 KHz to 150 KHz with a CRT projector, three colors of red (R), green (G), and blue (B) are high on the screen. There is a digital convergence system for accurate color matching.

As shown in FIG. 15, assuming that the digital convergence adjustment points are 32 points in the horizontal direction and 16 points in the vertical direction, the correction data in one horizontal scanning period (1H) is R, G for each adjustment point. In order to perform color matching by moving the electron beams of the three colors B and B in the horizontal and vertical directions, a total of 6CH (RH, RV, GH, GV, BH, B
V) minutes will be required.

In order to process this correction data in series, a clock which is 6 times the interval of one adjustment point is required. When this clock is fs, fs is as follows. fs = nH × 6 × fH (Hz) Formula 1 where nH: number of horizontal adjustment points fH: horizontal scanning frequency FIG. 16 is a timing chart showing the above relationship,
fs = 192 · fH.

Next, FIG. 14 will be described. The input terminals 1 and 2 are connected to an external data writing device, and correction data for correcting color misregistration are written in the memory 3 from here. The correction data stored in the memory 3 is
It is read in synchronization with the horizontal and vertical main deflection of the projector and converted into 6CH parallel data by the serial-parallel conversion circuit 4. Of this, the red horizontal correction data (RH) is input to the D / A converter 5. , After being converted into an analog signal, interpolation between adjustment points is performed through LPFs 6 to 8, the output of the LPF is selected by the selector 9, the output of the selector 9 is amplified by the amplifier 10, and then the convergence yoke 1
At 1, the color misregistration is corrected. RV, GH, GV, BH, BV
Similarly, for the D / A conversion block 12
After passing through the same blocks 13 to 17 as described above, the color misregistration correction is performed by the Yombersence yokes 18 to 22.

Next, the read address control of the correction data memory will be described. The horizontal scanning reference signal input from the input terminal 23 and the comparison pulse (HP) obtained by dividing fs by 192 are compared in phase by the phase comparator 26, and the error is converted into a voltage and output. This voltage is the loop filter 27
Is input to the VCOs 28 to 30. The VCO oscillates by varying the oscillation frequency with respect to the input error voltage (VI). Only the output of the VCO selected by the selector 31 becomes the system clock of the horizontal address generation circuit 34. The horizontal address generation circuit 34 is composed of a 192-ary counter, counts up with fs, counts 192, and then outputs a reset pulse (HP) to be reset. Since the phase of the H-BLK input from the HP and 23 is compared, fs is always 192 times the H-BLK, that is, fH.
192 times the frequency. Therefore, the correction data is always read at 192 times fH.

Now, the input horizontal frequency (fH) is 1
If it changes from 5 KHz to 150 KHz, fs fH is 192 times, that is, 2.88 MHz to 28.8 MHz.
Therefore, the oscillation frequency range for the error voltage output from the phase comparison of 26 becomes extremely wide, which is not so preferable from the viewpoint of oscillation stability. Therefore, 2.88MHz to 28.8MH
The range of z is divided into 3 and 2.88MHz to 11.52MHz
To 28 VCO 1, 11.53 MHz to 20.16
29 VCO2, 20.17 MHz to 2 MHz
Allocate 30 VCO3 for 8.8 MHz. As a result, the oscillation frequency range of one VCO is 8.64MHz
Is within the allowable range. This VCO switching is performed by detecting the input horizontal frequency, and fH is 0 Hz to 51 KHz,
52KHz-102KHz, 103KHz-153KH
Perform in the range of z. As described above, the correction data is fs
Since it is read at the rate of, the characteristics of the LPFs in the 12 blocks should be changed linearly, but here, in the same range as the VCO switching range,
Switch PF3 type.

Next, a horizontal frequency detection circuit and a VCO
And the control circuit of the LPF will be described. FIG. 17 shows an example of the input horizontal frequency detection circuit and the VCO control circuit. In the figure, 32 is an 11-bit up counter, which counts the number of H-BLKs during the period of the positive polarity window signal (TW). The up counter 32 has a maximum of 204
Up to 8 counts are possible. For example, if TW is set to 10 ms, 100 times the value counted during the TW period becomes the actual frequency, and fH can be counted from 0 Hz to 204.8 KHz. This output is decoded by the decoding circuit 33 within a predetermined frequency range, and the select signals (SEL1, SE
L2, SEL3) are output. The results are summarized in Table 1. In this table, "H" is logical 1 and "L" is O
Indicates.

[0010]

[Table 1]

FIG. 18 is a graph showing the relationship between the control voltage (VI) input to the VCOs 28 to 30 and the oscillation frequency of each VCO. As you can see from this graph, one VCO is responsible for the oscillation frequency range of about 10MHz,
For example, when the oscillation frequency (fs) is controlled within ± 1%, the control voltage is ± 12 mV in the worst case, which requires very high-precision voltage control and is a system weak against noise.

FIG. 19 shows the characteristics of the LPF after D / A conversion which is switched by the select signal. LPF1,
The characteristics of LPF2 and LPF3 are VCO1 and VCO, respectively.
2, the center frequency at which the VCO 3 oscillates is set to ideal characteristics, and the wider the oscillation frequency range of each VCO, the more the respective LPFs deviate from the ideal characteristics.

[0013]

The digital convergence device in the conventional multi-scan type video projector is configured as described above, and the VCO and the LPF after D / A must be switched according to the input horizontal frequency. However, there is a problem that the accuracy is insufficient and the circuit scale becomes very large.

The present invention has been made to solve the above problems, and it is not necessary to switch between the VCO and the LPF after D / A even if the input horizontal frequency to the receiver changes over a wide range. It is an object of the present invention to obtain a digital convergence apparatus that can realize highly accurate digital convergence with a minimum circuit scale and a small correction data memory, and that the LPF is always optimal for the convergence correction data rate.

[0015]

SUMMARY OF THE INVENTION A digital convergence apparatus according to the present invention comprises a horizontal frequency detecting means for inputting to a receiver and a plurality of means for performing interpolation calculation of convergence correction data in real time for one horizontal period. It has an interpolation filter, a selector for switching a plurality of interpolation filters, and a means for controlling the selector, and controls the number of digital convergence adjustment points according to the detected horizontal frequency. Only the correction data at a predetermined adjustment point is stored in the memory, and the remaining correction data is calculated in real time to obtain the correction data.

Further, when the controlled number of adjustment points becomes an integral multiple of the predetermined number of adjustment points, the interpolation filter for performing the correction data interpolation calculation of the horizontal period is switched.

Further, of the correction data for one horizontal period,
The correction data for the horizontal blanking period is obtained by interpolating from the correction data for the scanning period, and the interpolation filter used for this interpolation is switched according to the input horizontal frequency.

[0018]

The horizontal interpolation filter according to the present invention calculates the data for interpolating the convergence correction data stored in the memory in real time.

The selector according to the present invention selects the output of a predetermined horizontal interpolation filter according to the input horizontal frequency.

The horizontal blanking interval correction data creation circuit of the present invention creates convergence correction data for the horizontal blanking interval from the correction data for the scanning interval in accordance with the input horizontal frequency.

[0021]

EXAMPLES Example 1. Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing the configuration of a digital convergence device according to this embodiment. In the figure, 1 is an input terminal for correction data, 2 is an address input terminal for writing correction data in a memory, and 3 is convergence correction data. A memory for storing, 4 is a serial-parallel conversion circuit for converting 6CH serial data read from the memory into 6CH parallel data, and 51 is interpolation data between the correction data output from the serial-parallel conversion circuit 4 and the correction data. Horizontal selector filter, 52 is a selector for selecting the output of the horizontal interpolation filter, 5 is a D / A converter for converting the digital data selected by the selector 52 into an analog correction signal, 40 is a low-pass filter, and 10 is a correction An amplifier that amplifies the signal, 11 is a convergence yoke, and 53 is water per correction signal 1CH. Correction blocks after interpolation, 54 to 58 are the same blocks as the correction block 53, 18 to 22 are the same convergence yokes as the convergence yoke 11, 23 is an input terminal of the image erasing pulse in the horizontal blanking period, and 24 is a horizontal frequency. Input terminal of a window signal for measuring, 25 is an input terminal of an image erasing pulse in the vertical blanking period, 49 is a PLL circuit for generating a clock synchronized with H-BLK, and 34 is a correction stored in the memory 3. A horizontal address generation circuit at an adjustment point for reading data, 35 is also a vertical address generation circuit, 32 is a horizontal frequency detection circuit, 48 is a horizontal address generation circuit control circuit, and 50 is a horizontal interpolation filter control circuit.

Next, the operation will be described. In FIG. 1, the input terminals 1 and 2 are connected to an external data writing device, from which correction data for correcting color misregistration is written in the memory 3. The correction data stored in the memory 3 is read out in synchronization with the horizontal and vertical main deflections of the projector and converted into 6CH parallel data by the serial-parallel conversion circuit 4, of which the red horizontal correction data ( RH) is 1 by the horizontal interpolation filter 51.
Regarding the correction data in the horizontal period, new correction data correlated with the memory data is interpolated between the correction data read from the memory and the next correction data. This interpolation filter has a plurality of outputs according to the input horizontal frequency to the projector, and the selector 52 selects the output of the horizontal interpolation filter 51. This selected digital data is D
After entering the / A converter 5 and being converted into an analog signal, it passes through the LPF 40 and interpolates between horizontal adjustment points,
Amplification is performed by the amplifier 10, and color convergence correction is performed by the convergence yoke 11. Similarly, the same block 5 as the correction block 53 is used for RV, GH, GV, BH and BV.
After passing 4 ~ 58, convergence yoke 18 ~ 2
In step 2, color misregistration correction is performed.

Next, the read address control of the correction data memory will be described. A system clock N times the horizontal frequency (fH) synchronized with the horizontal scanning reference signal (hereinafter referred to as H-BLK) input from the input terminal 23 is set to P.
It is generated in the LL circuit 49 and used as the clock of the horizontal address generation circuit 34. The horizontal address generating circuit 34 is composed of an N-ary counter and counts up with fs.
After N counts, a load pulse (HP) is output and preset. This HP and the H- input from the input terminal 23
Since BLK is compared in phase, fs is always N of fH.
The oscillation frequency is doubled. Therefore, the correction data is always fH
Will be read at a data rate N times higher. If this fs is always constant regardless of the change of the input horizontal frequency, or if the range of change is very small with respect to the center frequency of the VCO oscillation of the PLL circuit, it is necessary to switch between the VCO and the LPF after D / A. There is no.

Next, a method for keeping the reading rate of the correction data substantially constant regardless of the input horizontal frequency will be described. Now, assuming that the input horizontal frequency has changed from 15 KHz to 150 KHz, the frequency is measured by the 32 horizontal frequency detection circuits, and based on this result, the 48 address control circuits cause the horizontal address generation circuit of 34 to obtain a predetermined control value. give.

FIG. 2 shows an example of the frequency detection circuit and the address control circuit. In the figure, 32 is an 11-bit up-counter, which is H-B during the positive window signal (TW).
Count the number of LKs. The maximum counter 32 is 204
Up to 8 counts are possible. For example, when TW is set to 10 ms, 100 times the value counted in the TW period becomes the actual frequency, and fH can be measured from 0 Hz to 204.8 KHz. In this embodiment, fs = 6 × nH × fH,
(However, nH is the number of horizontal adjustment points.) To keep fs constant, nH should be changed to nH = fs
It may be set to a value of / (6 · fH).

Since the horizontal address generating circuit is composed of an 11-bit counter, the number of adjustment points can be controlled by controlling the start offset value (P) of the counter. This value (P) is given by the following equation. ΔP = 2047-6nH = 2047-fs / fH Equation 2 fH measured by the counter 32 is held by the latch circuit 481 and the value of fH is output to R0M482. ROM
At 482, the inverted output of fs / fH with respect to the input fH is output and the addition circuit 483 is entered. 483 addition result P
Becomes a value that satisfies Expression 2, and this P is used to control the horizontal adjustment point atres.

Now, if fs = 21.6 MHz is set,
The desired control value P is P = 2047-21.6 × 10 ⁶ / f
H (Hz), which is the value shown in the graph of FIG. However, since the division ratio N = 6 · nH is an integer, f
s is not constant and has a certain width.

Next, horizontal data interpolation will be described. Of the 1H adjustment points set according to the input horizontal frequency fH as described above, the minimum adjustment points are 24 points, the maximum adjustment points are 240 points, and the adjustment points in the 1H period stored in the three memories are 24 points. When the number of adjustment points is 24 times n times, 24 × n correction data are interpolated. When n is an integer, n is from 1 to 9. The state of the data at this time is shown in FIG.

FIG. 5 is a block diagram of this horizontal interpolation filter. f'is a data rate of correction data per 1CH, and has a relationship of fSD = 24.fH. When n = 1, that is, when one data is interpolated between the data read from the memory, the data is F101 and the direct output and F102.
The output of is switched by the switch 511. By performing this switching at the timing of 2 · fSD, the corrected data of the data-interpolated 2fSD rate is input to the selector 52.

In the following, when n = 2 to 9, similarly, f
After the SD rate correction data enters F201 to F918 and passes the switches 512 to 519, the selector 52 B to J
to go into.

FIG. 6 shows the configuration of the interpolation filter when n = 2 among the above filters. The correction data input at fSD is delayed by the D flip-flops 5101 to 5103, and the respective outputs are coefficient ROMs 5014 to 5024.
And add a predetermined coefficient, and then adders 5025 to 50
The output is added at 28, and the output is switched by the switch 512 and output.

Next, the selector 52 for selecting the horizontal interpolation filter will be described. FIG. 7 shows an example of the horizontal frequency detection circuit and the interpolation filter control circuit in this embodiment. In the figure, 32 is an 11-bit up-counter, which counts the number of H-BLK signals in the period of the positive polarity window signal (TW). This cowan is capable of counting up to 2048 counts. For example, if TW is set to 10ms,
The actual horizontal frequency is 100 times counted in the TW period, and fH can be measured from 0 Hz to 204.8 KHz. The output of the counter 32 is latched by the D flip-flop 501 and input to the ROM 502. ROM502
Then, a 4-bit control signal is output with respect to the measured fH, and this output switches the selector of the interpolation filter. FIG. 8 shows the relationship among the control signal S, the horizontal frequency fH, and the output (S) of the selected filter.

Next, the correction data in the horizontal blanking period will be described. FIG. 9 shows a state of a screen created by scanning. The shaded area in the figure is the scanning blanking period and there is no video signal. FIG. 10 shows the state of the correction data before and after the blanking period. It is necessary to interpolate correction data that smoothly connects the correction data (memory data) on the n-th line and the correction data on the (n + 1) th line from the data in the scanning period, but if the number of memory data in one horizontal period is fixed. However, if the number of correction data in this blanking period also changes when the number is changed according to the input horizontal frequency, it is necessary to switch the filter for interpolating this data. FIG. 11 shows a simple configuration of a correction data generation block to be written in the memory. The correction data of the video period is input from the terminal 601 and is input from the synthesis circuit 602 in the horizontal blanking period correction data generation circuit 603. Correction data for the blanking period is created based on the horizontal scanning reference signal (HD), and the combining circuit 602 is used.
Then, the created data is interpolated into the data input from the terminal 601, and output as memory write data.

By using the digital convergence device as described above, the oscillation frequency of the VCO in the PLL,
The data rate of the correction data has the characteristic shown in FIG. In the figure, the oscillation frequency may be ± 2% of the center frequency with respect to the VCO control voltage of 4 V, which enables highly accurate control.

Example 2. FIG. 13 shows another embodiment of the present invention. In the above embodiment, the horizontal interpolation filter 51
Although the selector 52 and the selector 52 are provided after the serial-parallel data conversion circuit 4, they may be provided after the correction data memory. In this case,
The clock for the interpolation calculation is performed at a rate 6 times that of the first embodiment. In this embodiment, only one set of horizontal interpolation filters is required, which is advantageous over the first embodiment in terms of circuit scale.

[0036]

As described above, according to the present invention, the number of convergence adjustment points is controlled according to the horizontal input frequency, and the correction data is interpolated by the horizontal interpolation filter. Data and the position of the adjustment point on the screen are always constant regardless of the horizontal water wave number. Further, there is an effect that a digital convergence device having a small circuit scale can be obtained without requiring switching of LDF after D / A.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a digital convergence device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a horizontal frequency detection circuit and an address control circuit according to the present invention.

FIG. 3 is a graph showing an address control value according to the present invention.

FIG. 4 is a diagram showing data interpolation of a horizontal interpolation filter according to the present invention.

FIG. 5 is a configuration diagram of a horizontal interpolation filter according to the present invention.

FIG. 6 is a configuration diagram of an interpolation filter.

FIG. 7 is a diagram showing a control circuit of a selector according to the present invention.

FIG. 8 is a diagram showing a correspondence relationship between an input horizontal frequency, a filter selection signal, and an output of a selector.

FIG. 9 is a diagram for explaining a screen scanning period and a blanking period.

FIG. 10 is a diagram showing correction data before and after a blanking period.

FIG. 11 is a diagram illustrating a correction data creation unit in a blanking period.

FIG. 12 is a graph showing the characteristics of the VCO control voltage and the oscillation frequency in the present invention.

FIG. 13 is a circuit diagram showing a configuration of a digital convergence device showing another embodiment of the present invention.

FIG. 14 is a circuit diagram showing a configuration of a conventional digital convergence device.

FIG. 15 is a diagram for explaining adjustment points of a conventional digital convergence device.

FIG. 16 is a timing chart of interpolation data for one horizontal period.

FIG. 17 is a diagram showing a horizontal frequency detection circuit and a VCO control circuit in a conventional digital convergence device.

FIG. 18 is a graph of the control voltage of the VCO and the oscillation frequency characteristic of each VCO in the conventional example.

FIG. 19 is a diagram showing characteristics of a conventional LPF.

[Explanation of symbols]

 24 Horizontal Frequency Detection Window Signal Input Terminal 34 Horizontal Address Control Circuit 50 Filter Control Circuit 51 Horizontal Interpolation Filter 52 Selector

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[Procedure amendment]

[Submission date] June 8, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 1

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction content]

Now, the input horizontal frequency (fH) is 1
If it changes from 5 KHz to 150 KHz, fs fH is 192 times, that is, 2.88 MHz to 28.8 MHz.
Must be controlled in a wide range of oscillation frequency range for the error voltage output from the 26 of the phase comparator is very wide, less favorable In terms of stability of the oscillator. Therefore, 2.88MHz to 28.8M
The range of Hz is divided into 3 and 2.88MHz to 11.52MH
28 VCO for z, 11.53 MHz to 20.1
29 VCO2 for 6 MHz, 20.17 MHz-2
Allocate 30 VCO3 for 8.8 MHz. As a result, the oscillation frequency range of one VCO is 8.64MHz
Is within the allowable range. This VCO switching is performed by detecting the input horizontal frequency, and fH is 0 Hz to 51 KHz,
52KHz-102KHz, 103KHz-153KH
Perform in the range of z. As described above, the correction data is fs
Since it is read at the rate of, the characteristics of the LPFs in the 12 blocks should be changed linearly, but here, in the same range as the VCO switching range,
Switch 3 types of PF.

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] 0029

[Correction method] Change

[Correction content]

FIG. 5 is a block diagram of this horizontal interpolation filter. f SD is a data rate of the correction data per CH, and has a relationship of f SD = 24 · fH. In the case of n = 1, that is, when one data is interpolated between the data read from the memory, the switch 511 switches between the direct output of F101 and the output of F102. This switching is 2
The correction data of the data-interpolated 2fSD rate is input to the selector 52 by performing at the timing of fSD.

Claims (3)

[Claims] 1. A digital convergence device having data for correcting a color shift of a receiver at each of the adjustment points for convergence correction, which is a point obtained by dividing a screen of the color receiver into a grid pattern. An input horizontal frequency is detected and the number of adjustment points is changed according to the horizontal frequency, and a storage device for storing only predetermined adjustment point data among the correction data of the adjustment points is provided, and the variable adjustment is performed. When the score becomes an integral multiple of the stored adjustment point, correction data other than the stored adjustment point data is calculated in real time using the stored data to obtain complementary data. apparatus. 2. The digital filter according to claim 1, wherein when the multiple of the total number of adjustment points with respect to the stored number of adjustment points changes, the digital filter for interpolation calculation is switched in real time. Convergence device. 3. When the digital convergence adjustment point is divided into a scanning period adjustment point and a blanking period adjustment point for one horizontal scanning period of a receiver, correction data of the blanking period is adjusted. When the input horizontal frequency is changed, the number of adjustment points in the scanning period or the blanking period is changed, and the filter for interpolating the correction data in the blanking period is switched. A digital convergence device.