JPH05300398A - Pll circuit - Google Patents

Abstract

PURPOSE:To automate manual re-adjustment for an offset for the PLL circuit. CONSTITUTION:In the PLL circuit generating a clock signal phase-locked with a horizontal synchronizing signal, when the PLL circuit is not synchronized, a differential amplifier 5 compares an output voltage e2 of a voltage amplifier 2 of a loop filter with a reference voltage E1 and amplifies the error signal and its resulting output voltage e3 is fed back to the input to the voltage amplifier 2 via a switch 6 to lock the PLL circuit automatically. When the locking is finished, the feedback loop is disconnected by the switch 6 and the normal PLL operation is restored.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MUSE signal processing circuit, and relates to control of a PLL circuit.

[0002]

2. Description of the Related Art MUSE (Multip
le Sub-Nyquist Sampling Encoding) method,
A frame pulse is added to the first two lines of each frame, and a horizontal synchronizing signal is added to the first line of each line. This MUS
In the E signal decoder, a PLL (Phase Locked L
(OP) circuit is used to generate a clock signal that is phase-synchronized with the horizontal synchronization signal and is supplied to each digital signal processing circuit. The PLL circuit operates by a closed loop including a phase error detector, a loop filter, and a voltage controlled oscillator (VCO) so that an input horizontal synchronizing signal and an oscillation signal of the VCO, that is, a clock signal maintain a predetermined phase relationship. .. It is desirable that the PLL circuit has a wide synchronous pull-in range from the asynchronous state such as channel switching to the pull-in of frequency and phase. Therefore, if the loop gain is set to a large value, the phase jitter in the synchronous state increases and the stability is improved. become worse. Therefore, the response characteristics of the PLL circuit are set in consideration of the optimum balance between the sync pull-in range and the sync stability. However, the signal source of the MUSE signal is not only the high-definition broadcasting by satellite but also the high-definition VTR and MUS.
There is an E signal generator or the like. For the above reason, the synchronization pull-in range does not have a large margin, and therefore, the PLL may not be pulled in when the signal sources are switched due to the difference in the horizontal synchronization signal waveform depending on the signal sources. Therefore, the offset voltage is manually readjusted and synchronized.

FIG. 2 shows an example of a conventional PLL, voltage amplification and offset adjustment circuit for a loop filter section. In the figure, reference numeral 1 designates an input terminal to which a voltage e1 obtained by integrating the output of the phase error detecting section is inputted. That is, MU
A voltage e corresponding to the phase difference between the horizontal synchronizing signal of the SE signal and the comparison signal based on the clock signal output from the PLL circuit.
1 is entered. Reference numeral 2 is a voltage amplifier which amplifies the input voltage e1 (gain A1) and outputs a voltage e2.
Determine next loop gain. The output voltage e2 is subjected to predetermined processing and becomes the control voltage of the voltage controlled oscillator (VCO).
R1 and R2 are feedback resistors, and the voltage gain A1 of the voltage amplifier 2 is
Is determined, and A1≈ (R1 + R2) / R2. Reference numeral 3 is a connection terminal for connecting an offset voltage, C1 is a smoothing capacitor, 4 is an offset voltage generation circuit, which is composed of an offset adjustment volume VR1, a power supply Vcc, etc., and outputs an adjustable offset voltage. Conventionally, in the circuit as described above, the offset voltage is readjusted each time when the PLL is out of synchronization.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and maintains the synchronization stability in a synchronized state, and at the same time, switches the signal source of the MUSE signal or the like.
(EN) Provided is a PLL circuit that automatically performs readjustment of an offset that was manually performed when the LL circuit is out of synchronization.

[0005]

In order to solve the above-mentioned problems, the present invention comprises a phase error detecting section for detecting a phase difference between a horizontal synchronizing signal and a comparison signal based on a clock signal, and a voltage amplifier inside. In a PLL circuit including a loop filter section and a voltage controlled oscillator section for generating and outputting a clock signal phase-locked with a horizontal synchronizing signal, a differential amplifier having a predetermined reference voltage and an output voltage of the voltage amplifier as inputs. And a PLL circuit configured to feed back the output of the differential amplifier to the input of the amplifier via a switch when the PLL circuit is in an asynchronous state.

[0006]

With the above construction, the PL according to the present invention
In the L circuit, when the PLL is asynchronous, the output voltage of the voltage amplifier of the loop filter is compared and amplified with the reference voltage by the differential amplifier, and the output is fed back to the input of the voltage amplifier via the switch. As a result, the voltage difference from the reference voltage is substantially offset, and the synchronization of the PLL is automatically pulled in. When synchronized, the feedback loop is disconnected by the switch, and normal PLL operation is restored. Therefore, when the signal source of the MUSE signal is switched, the PLL is automatically pulled in and locked against the loss of synchronization of the PLL.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of essential parts showing an embodiment of a PLL circuit according to the present invention. In the figure, the same parts as those in FIG. In the figure,
Reference numeral 5 is a differential amplifier which receives the output e2 of the voltage amplifier 2 and the reference voltage E1 as an input, and which has a voltage e corresponding to the difference voltage between the outputs e2 and E1.
Outputs 3. The resistors R3, R4, R5 and R6 determine the gain A2 of the differential amplifier 5. An analog switch 6 connects the voltage e3 to the offset voltage connection terminal 3 via the resistor R7 by a control signal input to the terminal 7. Reference numeral 4 denotes an offset voltage generation circuit including the above-mentioned units.

Next, the operation of the PLL circuit according to the present invention will be described. First, the operation of the differential amplifier 5 will be described. Now
The resistors R3, R4, R5 and R6 are connected to R3 = R5, R4 =
If the relation R6 is selected, the following equation is obtained. e3 = R4 / R3 (e2-E1) = A2 (e2-E1) That is, in the differential amplifier 5, the gain A2 is determined by the ratio of the resistors R4 and R3, and the voltage e3 proportional to the difference voltage between the voltages e2 and E1. Is output. Next, assuming that the MUSE signal generator is set as a reference as the MUSE signal source,
The reference voltage E1 is selected as the value of the output voltage e2 of the voltage amplifier 2 in the PLL synchronous state at this time. Also, terminal 7
A PLL synchronous / asynchronous signal is input to the analog switch 6, and the analog switch 6 is switched to the lower side in the figure in the synchronous state and to the upper side in the asynchronous state by this signal. Well, MU
When out-of-synchronization occurs due to switching of the SE signal source or the like, the output voltage e3 of the differential amplifier 5 described above is output to the voltage amplifier 2 via the switch 6 and the offset voltage connection terminal 3.
It is connected to the input of and makes a feedback loop. As a result, the voltage e
The difference voltage between 2 and E1 is 1 compared to the case without feedback.
It is compressed to / (1 + A1 ・ A2) and drives the PLL operation to the synchronous state. When the synchronous state is entered, the feedback loop is disconnected by the switch 6 and the normal PLL operation is resumed. The value of A1 · A2 (the product of the gains of the voltage amplifier 2 and the differential amplifier 5) indicating the feedback amount is set according to the condition of the PLL circuit.

[0009]

As described above, P according to the present invention
In the LL circuit, when the PLL is asynchronous,
The output voltage of the voltage amplifier of the filter is compared and amplified with the reference voltage by the differential amplifier, and its output is fed back to the input of the voltage amplifier to be offset. Therefore, there is an effect that the PLL is automatically pulled in and locked against the loss of synchronization of the PLL when the signal source of the MUSE signal is switched, without manual readjustment of the offset.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a main part showing an embodiment of a PLL circuit according to the present invention.

FIG. 2 shows an example of a conventional voltage amplification and offset adjustment circuit for a PLL and loop filter section.

[Explanation of symbols]

 1 Input Terminal 2 Voltage Amplifier 3 Offset Voltage Connection Terminal 4 Offset Voltage Generation Circuit 5 Differential Amplifier 6 Analog Switch 7 Control Terminal

Claims (2)

[Claims] 1. A horizontal error detection unit for detecting a phase difference between a horizontal synchronizing signal and a comparison signal based on a clock signal, a loop filter unit internally provided with a voltage amplifier, and a voltage controlled oscillator unit. A PLL circuit that generates and outputs a clock signal that is phase-locked with a synchronization signal is provided with a differential amplifier that receives a predetermined reference voltage and an output voltage of the voltage amplifier as input, and when the PLL circuit is in an asynchronous state, the differential circuit is provided. A PLL circuit characterized in that the output of the amplifier is fed back to the input of the amplifier via a switch. 2. The PLL according to claim 1, wherein the amount of feedback from the differential amplifier is set to a value that substantially offsets the difference voltage between the reference voltage and the output voltage of the voltage amplifier.
circuit.