JPH0583027B2 - - Google Patents
Info
- Publication number
- JPH0583027B2 JPH0583027B2 JP60163373A JP16337385A JPH0583027B2 JP H0583027 B2 JPH0583027 B2 JP H0583027B2 JP 60163373 A JP60163373 A JP 60163373A JP 16337385 A JP16337385 A JP 16337385A JP H0583027 B2 JPH0583027 B2 JP H0583027B2
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- circuit
- voltage
- signal
- horizontal synchronizing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000010355 oscillation Effects 0.000 claims description 9
- 230000001360 synchronised effect Effects 0.000 claims description 4
- 230000001960 triggered effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Landscapes
- Controls And Circuits For Display Device (AREA)
- Synchronizing For Television (AREA)
Description
【発明の詳細な説明】
産業上の利用分野
本発明は水平同期周波数が広範囲にわたる映像
信号が入力されるテレビジヨン受像機において用
いることができる水平同期回路に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a horizontal synchronization circuit that can be used in a television receiver to which video signals having a wide range of horizontal synchronization frequencies are input.
従来の技術
一般にテレビジヨン受像機の水平同期回路は、
第２図に示すように、偏向出力回路４からの信号
ｂと水平同期信号ａとの位相を位相比較回路１に
よつて比較し、その位相差に応じた電圧をローパ
スフイルタ２を通して取り出して電圧制御発振器
３を制御し、電圧制御発振器３の発振周波数を水
平同期信号の周波数と一致させることにより、水
平同期信号ａと同期したブラウン管の水平偏向を
行なつている。Prior Art Generally, the horizontal synchronization circuit of a television receiver is
As shown in FIG. 2, the phases of the signal b from the deflection output circuit 4 and the horizontal synchronizing signal a are compared by the phase comparison circuit 1, and a voltage corresponding to the phase difference is extracted through the low-pass filter 2 and the voltage is By controlling the controlled oscillator 3 and making the oscillation frequency of the voltage controlled oscillator 3 match the frequency of the horizontal synchronizing signal, horizontal deflection of the cathode ray tube is performed in synchronization with the horizontal synchronizing signal a.
発明が解決しようとする問題点
このような従来の水平同期回路においては、水
平同期信号ａと偏向出力回路４からの信号ｂの間
では、位相の比較しか行なわれていないために、
水平同期信号ａの周波数が、例えば２倍以上とい
うように大きく変化した場合、そのままでは水平
同期信号の周波数と偏向出力信号の周波数との同
期をとることが出来ない。そこで、その都度、電
圧制御発振器３を再調整する必要があつた。Problems to be Solved by the Invention In such a conventional horizontal synchronization circuit, only a phase comparison is performed between the horizontal synchronization signal a and the signal b from the deflection output circuit 4.
If the frequency of the horizontal synchronizing signal a changes significantly, for example by twice or more, it is impossible to synchronize the frequency of the horizontal synchronizing signal and the frequency of the deflection output signal as it is. Therefore, it was necessary to readjust the voltage controlled oscillator 3 each time.
本発明は水平同期信号の周波数が２倍以上に大
きく変化しても、自動的に電圧制御発振器を制御
して水平同期信号と偏向出力の信号との同期をと
ることが出来る優れた水平同期回路を提供するこ
とを目的とする。 The present invention provides an excellent horizontal synchronization circuit that can automatically control the voltage controlled oscillator to synchronize the horizontal synchronization signal and the deflection output signal even if the frequency of the horizontal synchronization signal changes significantly by more than double. The purpose is to provide
問題点を解決するための手段
本発明の水平同期回路は、水平同期信号と偏向
出力回路の偏向出力信号との位相差に応じた電圧
を電圧制御発振器の制御入力に印加して、発振周
波数を水平同期信号周波数に一致させ、この電圧
発振器の出力信号を前記偏向出力回路を介して前
記偏向出力信号とすると共に、水平同期信号周波
数と偏向出力信号周波数との周波数差に応じた電
圧を出力する周波数比較回路を設け、周波数比較
回路の出力電圧を前記電圧制御発振器の制御入力
に加算したことを特徴とする。Means for Solving the Problems The horizontal synchronization circuit of the present invention applies a voltage corresponding to the phase difference between the horizontal synchronization signal and the deflection output signal of the deflection output circuit to the control input of the voltage controlled oscillator to adjust the oscillation frequency. Matching the horizontal synchronizing signal frequency, the output signal of this voltage oscillator is used as the deflection output signal through the deflection output circuit, and a voltage corresponding to the frequency difference between the horizontal synchronizing signal frequency and the deflection output signal frequency is outputted. The present invention is characterized in that a frequency comparison circuit is provided, and the output voltage of the frequency comparison circuit is added to the control input of the voltage controlled oscillator.
作 用
この構成によると、水平同期信号と偏向出力信
号との位相比較だけでなく、周波数比較回路を設
けて水平同期信号の周波数と偏向出力信号の周波
数の比較を行ない、その周波数の差に応じて電圧
制御発振器の制御を行つているため、位相比較回
路が充分に動作し得るまで、電圧制御発振器の発
振周波数を水平同期信号の周波数まで近づけてお
き、あとは位相比較回路によつて位相の比較を行
ない、偏向出力信号と水平同期信号に同期させる
ことが出来、水平同期信号周波数が２倍以上に大
きく変化した場合においても、自動的に偏向出力
信号を水平同期信号に同期させることができる。Operation According to this configuration, in addition to comparing the phase of the horizontal synchronizing signal and the deflection output signal, a frequency comparison circuit is provided to compare the frequency of the horizontal synchronizing signal and the frequency of the deflection output signal, and the frequency difference between the horizontal synchronizing signal and the deflection output signal is compared. Since the voltage controlled oscillator is controlled by the phase comparator, the oscillation frequency of the voltage controlled oscillator is kept close to the frequency of the horizontal synchronization signal until the phase comparator circuit can operate satisfactorily, and then the phase comparator circuit controls the voltage controlled oscillator. It is possible to perform a comparison and synchronize the deflection output signal with the horizontal synchronization signal, and even if the horizontal synchronization signal frequency changes significantly by more than double, the deflection output signal can be automatically synchronized with the horizontal synchronization signal. .
実施例
以下、本発明の一実施例を第１図に基づいて説
明する。なお、従来例と同様の作用を成すものに
は同一符号を付けてその説明を省く。Embodiment Hereinafter, an embodiment of the present invention will be described based on FIG. It should be noted that the same reference numerals are given to those having the same functions as those of the conventional example, and the explanation thereof will be omitted.
水平同期信号ａは位相比較回路１の一方の比較
入力端子と単安定回路５に入力される。単安定回
路５の出力パルスｃは積分回路７により平滑され
て、水平同期信号ａの周波数に比例した電圧ｅが
得られる。偏向出力回路４の偏向出力信号ｂは位
相比較回路１の他方の比較入力端子と単安定回路
６に入力され、単安定回路６の出力パルスｄは積
分回路８により平滑されて偏向出力回路４の信号
の周波数に比例した電圧ｆが得られる。この電圧
ｆをコンパレータとしての演算増幅器９の反転入
力端子（−）に、前記電圧ｅを非反転入力端子
（＋）に入力すると、演算増幅器９の出力電圧ｇ
には、水平同期信号ａの周波数と偏向出力回路の
信号ｂの周波数との差に応じた電圧が発生する。
そしてこの電圧ｇによつて電圧制御発振器３を制
御する。１０はローパスフイルタ２と電圧制御発
振器３の間に介装された加算点である。このよう
にして水平同期信号と偏向出力回路の信号との周
波数比較回路１１を構成している。 The horizontal synchronizing signal a is input to one comparison input terminal of the phase comparison circuit 1 and the monostable circuit 5. The output pulse c of the monostable circuit 5 is smoothed by an integrating circuit 7 to obtain a voltage e proportional to the frequency of the horizontal synchronizing signal a. The deflection output signal b of the deflection output circuit 4 is inputted to the other comparison input terminal of the phase comparison circuit 1 and the monostable circuit 6, and the output pulse d of the monostable circuit 6 is smoothed by the integrating circuit 8 and sent to the deflection output circuit 4. A voltage f proportional to the frequency of the signal is obtained. When this voltage f is input to the inverting input terminal (-) of the operational amplifier 9 as a comparator, and the voltage e is input to the non-inverting input terminal (+), the output voltage g of the operational amplifier 9
A voltage is generated in accordance with the difference between the frequency of the horizontal synchronizing signal a and the frequency of the signal b of the deflection output circuit.
The voltage controlled oscillator 3 is controlled by this voltage g. Reference numeral 10 denotes an addition point interposed between the low-pass filter 2 and the voltage controlled oscillator 3. In this way, the frequency comparison circuit 11 between the horizontal synchronizing signal and the signal of the deflection output circuit is constructed.
ここで、水平同期信号ａの周波数が高くなる方
向に変化したとすると、電圧ｅが上昇する。する
と、演算増幅器９の出力電圧ｇは上昇する方向に
動き、制御電圧ｈも上昇する電圧制御発振器３は
制御電圧ｈに比例して周波数が変化するため、電
圧ｅが上昇するとその発振周波数も高くなる。発
振周波数が高くなると偏向出力回路４の信号ｂの
周波数が高くなるため、演算増幅器９の反転入力
端子（−）の電圧ｆが上昇する。電圧ｆが上昇す
ると、演算増幅器９の出力ｇ低下する。このよう
にしてこの回路は安定なところで止まるのである
が、はじめ電圧ｅとｆが等しかつたとすると、水
平同期信号の周波数が高くなつて電圧ｅが上昇し
た場合、電圧ｆも電圧ｅとほぼ等しいところまで
上昇してこの回路が安定になる。この回路が安定
に動作する限り、演算増幅器９の利得が高いほ
ど、電圧ｅとｆはより近い電圧となる。また、電
圧ｅは水平同期信号の周波数を表わし、電圧ｆは
偏向出力回路４の信号の周波数、すなわち、電圧
制御発振器３の発振周波数を表わしているため、
このような周波数比較回路１１を用いると、水平
同期信号の周波数が２倍以上に大きく変化して
も、電圧制御発振器３の周波数を水平同期信号の
周波数にほぼ等しく保つことができる。この両者
の周波数がほぼ等しい場合には、位相比較回路１
が正常に動作を行ない、電圧制御発振器３の発振
周波数が水平同期信号の周波数に同期する。この
ように、水平同期回路に位相比較回路１に加えて
周波数比較回路１１を用いることにより、水平同
期信号ａの周波数が２倍以上に大きく変化する場
合にも、自動的に同期をとることができる。演算
増幅器９の利得は回路が安定に動作する限りでき
るだけ大きいことが望ましい。 Here, if the frequency of the horizontal synchronizing signal a changes in the direction of increasing, the voltage e increases. Then, the output voltage g of the operational amplifier 9 moves in an increasing direction, and the control voltage h also increases.The frequency of the voltage controlled oscillator 3 changes in proportion to the control voltage h, so when the voltage e increases, its oscillation frequency also increases. Become. As the oscillation frequency becomes higher, the frequency of the signal b from the deflection output circuit 4 becomes higher, so that the voltage f at the inverting input terminal (-) of the operational amplifier 9 increases. When the voltage f increases, the output g of the operational amplifier 9 decreases. In this way, this circuit stops at a stable point, but if voltages e and f are initially equal, when the frequency of the horizontal synchronizing signal increases and voltage e rises, voltage f will also be almost equal to voltage e. The circuit becomes stable when the voltage rises to an equal point. As long as this circuit operates stably, the higher the gain of the operational amplifier 9, the closer the voltages e and f will be. Further, since the voltage e represents the frequency of the horizontal synchronizing signal and the voltage f represents the frequency of the signal of the deflection output circuit 4, that is, the oscillation frequency of the voltage controlled oscillator 3,
By using such a frequency comparison circuit 11, the frequency of the voltage controlled oscillator 3 can be kept almost equal to the frequency of the horizontal synchronizing signal even if the frequency of the horizontal synchronizing signal changes significantly by twice or more. If these two frequencies are almost equal, the phase comparator circuit 1
operates normally, and the oscillation frequency of the voltage controlled oscillator 3 is synchronized with the frequency of the horizontal synchronization signal. In this way, by using the frequency comparator circuit 11 in addition to the phase comparator circuit 1 in the horizontal synchronization circuit, synchronization can be automatically achieved even when the frequency of the horizontal synchronization signal a changes significantly by more than double. can. It is desirable that the gain of the operational amplifier 9 be as large as possible so long as the circuit operates stably.
発明の効果
以上のように本発明の水平同期回路は、位相比
較回路に加えて、周波数比較回路を設けたため、
水平同期信号の周波数が２倍以上にも大きく変化
する場合においても、自動的に電圧制御発振器の
制御を行なうことが出来、水平同期信号の周波数
が変わるたびに電圧制御発振器の再調整を行なう
必要がなく、電圧制御発振器の発振周波数を水平
同期信号の周波数に同期させることが出来るた
め、非常に有効なものである。Effects of the Invention As described above, since the horizontal synchronization circuit of the present invention includes a frequency comparison circuit in addition to a phase comparison circuit,
The voltage controlled oscillator can be automatically controlled even when the frequency of the horizontal synchronizing signal changes significantly by more than double, eliminating the need to readjust the voltage controlled oscillator every time the frequency of the horizontal synchronizing signal changes. This is very effective because the oscillation frequency of the voltage controlled oscillator can be synchronized with the frequency of the horizontal synchronization signal.
第１図は本発明の水平同期回路の一実施例の構
成図、第２図は従来の水平同期回路の構成図であ
る。
１……位相比較回路、３……電圧制御発振器、
４……偏向出力回路、５，６……単安定回路、
７，８……積分回路、９……演算増幅器〔コンパ
レータ〕、１０……加算点、１１……周波数比較
回路。
FIG. 1 is a block diagram of an embodiment of the horizontal synchronization circuit of the present invention, and FIG. 2 is a block diagram of a conventional horizontal synchronization circuit. 1... Phase comparator circuit, 3... Voltage controlled oscillator,
4... Deflection output circuit, 5, 6... Monostable circuit,
7, 8... Integration circuit, 9... Operational amplifier (comparator), 10... Addition point, 11... Frequency comparison circuit.
Claims (1)
との位相差に応じた電圧を電圧制御発振器の制御
入力に印加して、発振周波数を水平同期信号周波
数に一致させ、この電圧発振器の出力信号を前記
偏向出力回路を介して前記偏向出力信号とすると
共に、水平同期信号周波数と偏向出力信号周波数
との周波数差に応じた電圧を出力する周波数比較
回路を設け、周波数比較回路の出力電圧を前記電
圧制御発振器の制御入力に加算した水平同期回
路。 ２ 周波数比較回路を、水平同期信号でトリガー
される第１の単安定回路と、偏向出力信号でトリ
ガーされる第２の単安定回路と、第１、第２の単
安定回路の出力信号をそれぞれ積分する第１、第
２の積分回路と、第１、第２の積分回路の両出力
を比較するコンパレータとで構成し、コンパレー
タの出力電圧を水平同期信号周波数と偏向出力信
号周波数との周波数差に応じた電圧出力としたこ
とを特徴とする特許請求の範囲第１項記載の水平
同期回路。[Claims] 1. Applying a voltage corresponding to the phase difference between the horizontal synchronizing signal and the deflection output signal of the deflection output circuit to the control input of the voltage controlled oscillator to match the oscillation frequency with the horizontal synchronizing signal frequency; A frequency comparison circuit is provided which outputs an output signal of the voltage oscillator as the deflection output signal through the deflection output circuit, and outputs a voltage according to a frequency difference between the horizontal synchronization signal frequency and the deflection output signal frequency. A horizontal synchronous circuit that adds the output voltage of the voltage controlled oscillator to the control input of the voltage controlled oscillator. 2. The frequency comparison circuit is connected to the first monostable circuit triggered by the horizontal synchronization signal, the second monostable circuit triggered by the deflection output signal, and the output signals of the first and second monostable circuits, respectively. It consists of first and second integrating circuits that integrate, and a comparator that compares both outputs of the first and second integrating circuits, and the output voltage of the comparator is determined by the frequency difference between the horizontal synchronizing signal frequency and the deflection output signal frequency. 2. The horizontal synchronizing circuit according to claim 1, wherein the horizontal synchronizing circuit has a voltage output according to the voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60163373A JPS6223284A (en) | 1985-07-23 | 1985-07-23 | Horizontal synchronizing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60163373A JPS6223284A (en) | 1985-07-23 | 1985-07-23 | Horizontal synchronizing circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6223284A JPS6223284A (en) | 1987-01-31 |
| JPH0583027B2 true JPH0583027B2 (en) | 1993-11-24 |
Family
ID=15772645
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60163373A Granted JPS6223284A (en) | 1985-07-23 | 1985-07-23 | Horizontal synchronizing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6223284A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6346073A (en) * | 1986-08-13 | 1988-02-26 | Nec Corp | Phase locked loop oscillation circuit |
| JP3019310B2 (en) * | 1988-09-30 | 2000-03-13 | ソニー株式会社 | Automatic frequency control circuit |
| US5404172A (en) * | 1992-03-02 | 1995-04-04 | Eeg Enterprises, Inc. | Video signal data and composite synchronization extraction circuit for on-screen display |
-
1985
- 1985-07-23 JP JP60163373A patent/JPS6223284A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6223284A (en) | 1987-01-31 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |