JPH07105898B2 - Horizontal synchronization circuit - Google Patents
Horizontal synchronization circuitInfo
- Publication number
- JPH07105898B2 JPH07105898B2 JP1695987A JP1695987A JPH07105898B2 JP H07105898 B2 JPH07105898 B2 JP H07105898B2 JP 1695987 A JP1695987 A JP 1695987A JP 1695987 A JP1695987 A JP 1695987A JP H07105898 B2 JPH07105898 B2 JP H07105898B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- frequency
- horizontal
- output
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Synchronizing For Television (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、水平同期周波数が広範囲にわたる映像信号が
入力されるテレビジョン受像機において用いることがで
きる水平同期回路に関するものである。TECHNICAL FIELD The present invention relates to a horizontal synchronizing circuit that can be used in a television receiver to which a video signal having a wide horizontal synchronizing frequency is input.
従来の技術 一般に広範囲の水平同期周波数に対応するテレビジョン
受像機の水平同期回路においては第２図に示すように、
ａから入力された水平同期信号は位相比較回路１に入力
されるとともに単安定回路６に入力され、単安定回路６
の出力は積分回路８で積分され水平同期周波数に比例し
た電圧ｂを得て、電圧制御発振器３の発振周波数との比
較を行なうため、演算増幅器10に入力されている。2. Description of the Related Art Generally, as shown in FIG. 2, in a horizontal synchronizing circuit of a television receiver corresponding to a wide range of horizontal synchronizing frequencies,
The horizontal synchronizing signal input from a is input to the phase comparison circuit 1 and the monostable circuit 6, and the monostable circuit 6
The output of 1 is integrated by the integrating circuit 8 to obtain a voltage b proportional to the horizontal synchronizing frequency, and is input to the operational amplifier 10 for comparison with the oscillation frequency of the voltage controlled oscillator 3.
また、偏向出力回路４からの信号は位相比較回路１に入
力されるとともに単安定回路７に入力され、単安定回路
７の出力は積分回路９で積分され水平発振周波数に比例
した電圧ｄを得て、演算増幅器10で入力された水平同期
信号と比較され、比較出力はローパスフィルター11を通
って電圧ｅを得る。この電圧ｅは位相比較回路１からの
比較出力ｆと加算回路５で加算され、電圧制御発振器３
を、入力される水平同期信号と同期するように制御す
る。The signal from the deflection output circuit 4 is also input to the phase comparison circuit 1 and the monostable circuit 7, and the output of the monostable circuit 7 is integrated by the integration circuit 9 to obtain the voltage d proportional to the horizontal oscillation frequency. Then, it is compared with the horizontal synchronizing signal input by the operational amplifier 10, and the comparison output passes through the low pass filter 11 to obtain the voltage e. This voltage e is added to the comparison output f from the phase comparison circuit 1 in the addition circuit 5, and the voltage controlled oscillator 3
Are controlled so as to be synchronized with the input horizontal synchronizing signal.
このようにして演算増幅器10で周波数の比較を行ない。
電圧制御発振器３の発振周波数を入力される水平同期信
号の周波数に近づけるとともに、位相比較回路１で位相
の比較を行ない水平偏向周波数を水平同期信号に同期さ
せている。In this way, the operational amplifier 10 compares the frequencies.
The oscillation frequency of the voltage controlled oscillator 3 is brought close to the frequency of the input horizontal synchronizing signal, and the phase comparison circuit 1 compares the phases to synchronize the horizontal deflection frequency with the horizontal synchronizing signal.
発明が解決しようとする問題点 ところがこのような水平同期回路においては、第３図の
A,Bに示しているような不正規複合同期信号が入力され
た場合、通常はｔHである水平同期の周期が垂直同期の
期間にＡの場合はｔ′Hに、Ｂの場合はｔ″HとｔHに
乱される。その場合、第２図の位相比較回路１及び周波
数比較回路12が乱された位相、及び周波数に追従するよ
うに出力が変動する。The problem to be solved by the invention is that in such a horizontal synchronizing circuit, as shown in FIG.
When an abnormal composite sync signal as shown in A and B is input, the horizontal sync cycle, which is usually t H , is t ′ H in the case of A during the vertical sync period, and t in the case of B. ″ H and t H. In that case, the output fluctuates so that the phase comparison circuit 1 and the frequency comparison circuit 12 shown in FIG. 2 follow the disturbed phase and frequency.
このとき、一般に周波数比較回路12は広範囲な水平周波
数に対応するため、位相比較回路１よりも電圧制御発振
器３に対して大きな制御範囲をもつため、主にこの周波
数比較回路12の出力変動は、水平偏向周波数に大きな影
響を与えテレビジョン受像機などの場合、画面上に大き
な乱れが生じ、非常に見苦しくなる。At this time, since the frequency comparison circuit 12 generally corresponds to a wide range of horizontal frequencies and has a larger control range for the voltage controlled oscillator 3 than the phase comparison circuit 1, the output fluctuation of the frequency comparison circuit 12 is mainly In the case of a television receiver or the like, which has a large influence on the horizontal deflection frequency, a large disturbance occurs on the screen, which makes it very unsightly.
本発明は、このような問題点を解決するものであり、複
合同期信号によくある第３図A,Bのような乱れに対し
て、垂直同期期間だけ周波数比較回路の動作を停止さ
せ、電圧制御発振器への影響を少なくすることのできる
水平同期回路を提供するものである。The present invention solves such a problem, and the operation of the frequency comparison circuit is stopped only during the vertical synchronization period in response to the disturbance such as that shown in FIGS. A horizontal synchronizing circuit capable of reducing the influence on a controlled oscillator.
問題点を解決するための手段 本発明の水平同期回路は、垂直同期信号パルスが入力さ
れている期間だけ、周波数比較回路の動作を停止させ、
その周波数比較回路の比較結果である出力電圧を垂直同
期信号が入力される直前の値に保持させることにより、
垂直同期信号期間に水平同期信号の位相及び周波数が乱
されているような複合同期信号入力に対しても、周波数
比較回路の出力電圧により制御される電圧制御発振器の
発振周波数の乱れをつよくし、安定な偏向出力が得られ
る回路を構成したものである。Means for Solving the Problems The horizontal synchronizing circuit of the present invention stops the operation of the frequency comparing circuit only while the vertical synchronizing signal pulse is input,
By holding the output voltage, which is the comparison result of the frequency comparison circuit, at the value immediately before the vertical synchronization signal is input,
Even for a composite sync signal input in which the phase and frequency of the horizontal sync signal are disturbed in the vertical sync signal period, the disturbance of the oscillation frequency of the voltage controlled oscillator controlled by the output voltage of the frequency comparison circuit is enhanced, This is a circuit that can obtain a stable deflection output.
作用 本発明の水平同期回路は、垂直同期信号が入力されてい
る期間だけ周波数比較回路の出力電圧を遮断する回路
と、垂直同期信号が入力される直前の周波数比較回路の
出力電圧を保持するための、たとえばコンデンサーを設
けることによって、垂直同期信号期間に水平同期信号の
位相及び周波数が乱されているような複合同期信号が入
力された場合においても、水平同期信号の位相及び周波
数が乱されている間は周波数比較回路の出力電圧が遮断
され水平同期信号の位相及び周波数が乱される直前の周
波数比較回路の出力電圧の値を保持しているため、この
周波数比較回路によって制御される割合の大きい電圧制
御発振器に水平同期信号の周波数の乱れが伝達されない
ために、安定な水平偏向出力が得られる水平同期回路が
構成される。The horizontal synchronizing circuit of the present invention holds the output voltage of the frequency comparison circuit and the output voltage of the frequency comparison circuit immediately before the input of the vertical synchronization signal only during the period in which the vertical synchronization signal is input. , For example, by providing a capacitor, the phase and frequency of the horizontal sync signal are disturbed even when a composite sync signal is input in which the phase and frequency of the horizontal sync signal are disturbed during the vertical sync signal period. During this period, the output voltage of the frequency comparison circuit is cut off, and the value of the output voltage of the frequency comparison circuit immediately before the phase and frequency of the horizontal synchronization signal are disturbed is held. Since the disturbance of the frequency of the horizontal synchronizing signal is not transmitted to the large voltage-controlled oscillator, the horizontal synchronizing circuit that can obtain a stable horizontal deflection output is configured.
実施例 以下、本発明の一実施例としてテレビジョン受像機の水
平同期回路を図面を参照して説明する。Embodiment Hereinafter, a horizontal synchronizing circuit of a television receiver will be described as an embodiment of the present invention with reference to the drawings.
第１図に示すように、ｇより入力された複合同期信号は
同期分離回路Ｂによって垂直同期信号ｈが分離される。
同期分離回路13を通過した複合同期信号ｉは位相比較回
路14と周波数比較回路27の単安定回路19に入力される。
単安定回路19の出力は、積分回路21で積分され、複合同
期信号ｉの水平同期信号成分の周波数に比例した電圧ｊ
となって演算増幅器23に入力される。As shown in FIG. 1, a vertical sync signal h is separated from a composite sync signal input from g by a sync separation circuit B.
The composite sync signal i that has passed through the sync separation circuit 13 is input to the phase comparison circuit 14 and the monostable circuit 19 of the frequency comparison circuit 27.
The output of the monostable circuit 19 is integrated by the integrating circuit 21, and the voltage j proportional to the frequency of the horizontal synchronizing signal component of the composite synchronizing signal i.
Is input to the operational amplifier 23.
演算増幅器23のもう一方の入力端子には単安定回路20及
び積分回路22を通った水平偏向出力信号ｌの周波数に比
例した電圧ｋが入力されており、演算増幅器23の出力端
子には入力される複合同期信号ｇの水平同期信号成分の
周波数と偏向出力回路17の水平偏向出力信号ｌの周波数
の差に応じた電圧ｍが出力される。この出力電圧ｍはウ
ナログスイッチ25が導通状態の時は、ｍ＝ｎとなりコン
デンサ26を充電するとともにローパスフィルタ24を経て
加算回路18に入力される。A voltage k proportional to the frequency of the horizontal deflection output signal 1 passing through the monostable circuit 20 and the integrating circuit 22 is input to the other input terminal of the operational amplifier 23, which is input to the output terminal of the operational amplifier 23. The voltage m corresponding to the difference between the frequency of the horizontal synchronizing signal component of the composite synchronizing signal g and the frequency of the horizontal deflection output signal 1 of the deflection output circuit 17 is output. This output voltage m is set to m = n when the unalog switch 25 is conductive, charges the capacitor 26, and is input to the adding circuit 18 via the low-pass filter 24.
一方、位相比較回路14に入力された複合同期信号は偏向
出力回路17の水平偏向出力信号ｌと位相比較され、ロー
パスフィルタ15を経て複合同期信号ｇの水平同期信号成
分と水平偏向出力信号ｌとの位相差に応じた電圧Ｐとな
る。On the other hand, the phase of the composite sync signal input to the phase comparison circuit 14 is compared with that of the horizontal deflection output signal 1 of the deflection output circuit 17, and the horizontal sync signal component of the composite sync signal g and the horizontal deflection output signal 1 are passed through the low pass filter 15. The voltage becomes a voltage P according to the phase difference.
この電圧Ｐと周波数差に応じた電圧ｑが加算回路18に入
力され、加算回路18の出力θで電圧制御発振器16が制御
される。すなわち、周波数比較された電圧ｑで電圧制御
発振器16の発振周波数を複合同期信号ｑの水平同期信号
成分の周波数に接近させ、位相比較された電圧Ｐで電圧
制御発振器16の発振周波数を複合同期信号ｇの水平同期
信号成分に同期させる。The voltage P and the voltage q corresponding to the frequency difference are input to the adder circuit 18, and the output θ of the adder circuit 18 controls the voltage controlled oscillator 16. That is, the oscillation frequency of the voltage-controlled oscillator 16 is brought closer to the frequency of the horizontal synchronizing signal component of the composite synchronizing signal q by the frequency-compared voltage q, and the oscillation frequency of the voltage-controlled oscillator 16 is made by the phase-compared voltage P. Synchronize with the horizontal sync signal component of g.
ここでアナログスイッチ25は同期分離回路13で分離され
た垂直同期信号ｈによってオン／オフされ、垂直同期信
号期間はOFFとなる。アナログスイッチ25がオフの期間
は、オフになる直前にコンデンサー26にチャージされた
電圧にアナログスイッチ25の出力電圧ｎが保持され、垂
直同期信号期間に複合同期信号ｇの位相及び周波数が乱
れることによって周波数比較回路27の出力電圧ｍが変動
しても、ローパスフィルタ24の出力電圧ｑは変化しな
い。すなわち、電圧制御発振器16を制御する加算回路18
の出力電圧θには、ローパスフィルタ15の出力電圧Ｐす
なわち位相比較回路14の出力の変化のみが表われる。Here, the analog switch 25 is turned on / off by the vertical synchronization signal h separated by the synchronization separation circuit 13, and is turned off during the vertical synchronization signal period. While the analog switch 25 is off, the output voltage n of the analog switch 25 is held at the voltage charged in the capacitor 26 immediately before it is turned off, and the phase and frequency of the composite sync signal g are disturbed during the vertical sync signal period. Even if the output voltage m of the frequency comparison circuit 27 changes, the output voltage q of the low pass filter 24 does not change. That is, the adder circuit 18 that controls the voltage controlled oscillator 16
In the output voltage θ of 1, only the change of the output voltage P of the low-pass filter 15, that is, the output of the phase comparison circuit 14 appears.
しかし、位相比較出力のＰは周波数比較出力ｑに比べて
変化範囲が小さいため、電圧制御発振器16に与える影響
は非常に小さなものとなり、複合同期信号ｇがその垂直
同期信号期間に水平同期信号成分の位相及び周波数が乱
されていても、その乱れの影響を受けない正常な偏向出
力ｌを得ることができる。However, since P of the phase comparison output has a smaller variation range than the frequency comparison output q, the influence on the voltage controlled oscillator 16 is very small, and the composite synchronization signal g is a horizontal synchronization signal component during the vertical synchronization signal period. Even if the phase and the frequency of are disturbed, it is possible to obtain a normal deflection output 1 which is not affected by the disturbance.
発明の効果 以上のように、本発明の水平同期回路は、周波数比較回
路の出力状態を、垂直同期信号が入力される直前の状態
に垂直同期信号の期間だけ保持させるようにしたことに
より、垂直同期信号期間の水平同期信号成分の位相及び
周波数が乱された複合同期信号が入力された場合におい
ても、その乱れの影響のない正常な偏向出力を得ること
ができる。EFFECTS OF THE INVENTION As described above, the horizontal synchronizing circuit of the present invention is arranged so that the output state of the frequency comparison circuit is held in the state immediately before the vertical synchronizing signal is input for the period of the vertical synchronizing signal. Even when a composite sync signal in which the phase and frequency of the horizontal sync signal component in the sync signal period are disturbed is input, it is possible to obtain a normal deflection output free from the influence of the disturbance.
第１図は本発明の一実施例における水平同期回路の回路
図、第２図は従来例の水平同期回路の回路図、第３図は
複合同期信号の波形図である。 13……同期分離回路、14……位相比較回路、15,24……
ローパスフィルタ、16……電圧制御発振器、17……偏向
出力回路、18……加算回路、27……周波数比較回路、25
……アナログスイッチ、26……コンデンサー。FIG. 1 is a circuit diagram of a horizontal synchronizing circuit in an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional horizontal synchronizing circuit, and FIG. 3 is a waveform diagram of a composite synchronizing signal. 13 …… Synchronous separation circuit, 14 …… Phase comparison circuit, 15,24 ……
Low pass filter, 16 ... Voltage controlled oscillator, 17 ... Deflection output circuit, 18 ... Addition circuit, 27 ... Frequency comparison circuit, 25
…… Analog switch, 26 …… Condenser.
Claims (1)
水平偏向出力信号の位相を比較する位相比較回路と、上
記水平同期信号と水平偏向出力信号の周波数を比較する
周波数比較回路と、上記位相比較回路の出力と周波数比
較回路の出力によって偏向回路の発振周波数を水平同期
信号の周波数と一致させかつ水平同期信号の位相と同期
させるように制御する手段と、上記同期分離回路より得
られる垂直同期信号の期間は上記周波数比較回路の動作
を停止させる手段と、上記周波数比較回路が動作を停止
している期間はその出力レベルを周波数比較回路が動作
を停止する前のレベルに保持する手段とを備えた水平同
期回路。1. A phase comparison circuit for comparing the phases of a horizontal synchronization signal and a horizontal deflection output signal obtained from a synchronization separation circuit, a frequency comparison circuit for comparing the frequencies of the horizontal synchronization signal and the horizontal deflection output signal, and the phase. Means for controlling the oscillation frequency of the deflection circuit so as to match the frequency of the horizontal synchronizing signal and to synchronize with the phase of the horizontal synchronizing signal by the output of the comparing circuit and the output of the frequency comparing circuit; and the vertical synchronization obtained by the synchronization separating circuit. A means for stopping the operation of the frequency comparison circuit during the signal period and a means for holding the output level at the level before the frequency comparison circuit stops the operation during the period when the frequency comparison circuit stops the operation. A horizontal synchronization circuit equipped.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1695987A JPH07105898B2 (en) | 1987-01-27 | 1987-01-27 | Horizontal synchronization circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1695987A JPH07105898B2 (en) | 1987-01-27 | 1987-01-27 | Horizontal synchronization circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63185171A JPS63185171A (en) | 1988-07-30 |
| JPH07105898B2 true JPH07105898B2 (en) | 1995-11-13 |
Family
ID=11930647
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1695987A Expired - Fee Related JPH07105898B2 (en) | 1987-01-27 | 1987-01-27 | Horizontal synchronization circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07105898B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3019310B2 (en) * | 1988-09-30 | 2000-03-13 | ソニー株式会社 | Automatic frequency control circuit |
-
1987
- 1987-01-27 JP JP1695987A patent/JPH07105898B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63185171A (en) | 1988-07-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4092672A (en) | Master oscillator synchronizing system | |
| JPH07105898B2 (en) | Horizontal synchronization circuit | |
| JPH084323B2 (en) | Synchronous circuit for video equipment | |
| JPH0747007Y2 (en) | AFC circuit | |
| JPS6161308B2 (en) | ||
| JP2798391B2 (en) | Circuit device that automatically switches the control speed of the phase control circuit | |
| JP2714193B2 (en) | Digital television receiver | |
| JP2880187B2 (en) | Digital television receiver | |
| JP2647876B2 (en) | Standard frequency generation circuit | |
| JP2641290B2 (en) | Clock generator | |
| KR910009089B1 (en) | Phae locked loop circuit | |
| JPS6223284A (en) | Horizontal synchronizing circuit | |
| JP2661300B2 (en) | Control method of image sampling clock | |
| JPS6187475A (en) | Horizontal synchronizing circuit | |
| JPH0638532Y2 (en) | External synchronization circuit of video camera | |
| JPS63158975A (en) | Synchronizing circuit for television receiver | |
| JPH03265374A (en) | Pll circuit | |
| JPH0149075B2 (en) | ||
| JPS6052621B2 (en) | Horizontal oscillation frequency automatic control circuit | |
| JPS63276921A (en) | Pll circuit | |
| JPH0523018Y2 (en) | ||
| JPH01208080A (en) | Synchronizing signal separating circuit | |
| KR19990001545A (en) | Synchronization Signal Generator in Image Processing System | |
| JPS6053985B2 (en) | vertical synchronizer | |
| JPS63108875A (en) | Video signal synchronizing device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |