JP3504153B2 - PLL circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention is particularly suitable for use in horizontal synchronization processing and IF signal processing of TV receivers.
The present invention relates to a highly versatile PLL circuit including a VCO incorporated in C and adjustment of its free-run frequency.

[0002]

2. Description of the Related Art When a PLL circuit is built in an IC, the IC
There is a problem of variation in free-run frequency of the voltage controlled oscillator (VCO), which is a constituent element of the PLL circuit, due to variation in time constant in the manufacturing process. In the state where the input signal arrives at the PLL circuit and the VCO is locked, the oscillation frequency of the VCO is equal to the input signal frequency, so that special means is required to detect the free-run frequency. Since the input signal frequency cannot be specified in a general application of the PLL circuit, the oscillation frequency of the VCO cannot be adjusted to a predetermined value in the locked state. If the adjusting circuit and the PLL circuit are operated at the same time, the control of both will be contradictory.
This is because the LL function fails. An example in which the PLL is adjusted under such restrictions will be described.

As an example of use in the horizontal synchronizing and reproducing section of a TV receiver, Japanese Patent Laid-Open No. 9-233366 "Horizontal Synchronizing Circuit" is given. Here, the fact that the horizontal synchronization PLL circuit stops pulling in during the vertical blanking period is utilized, and the frequency control of the PLL circuit is stopped (open loop) only during this period to oscillate the VCO at the free-run frequency. At the same time, the adjusting circuit is operated within this blanking period to adjust the free-run frequency to a desired value. The horizontal synchronizing PLL circuit and the adjusting circuit are operated in a time division manner.

As an example of using a PLL circuit in an intermediate frequency (IF) processing section of a TV receiver, Japanese Patent Laid-Open No. 7-30412 "PLL circuit and TV signal processing apparatus using the same" is given. Here, in order to reproduce the IF frequency signal, P
An LL circuit is provided and operates simultaneously with the adjusting circuit. By setting the time constant of the adjusting circuit longer than the time constant of the PLL circuit, the adjusting circuit does not immediately respond even if the incoming signal frequency deviates from the convergence point of the adjustment. Meanwhile, the error information is reflected through another tuner path called an AFT loop, and the input signal frequency of the PLL circuit is controlled to be equal to the adjustment convergence point. Therefore,
The PLL and the adjustment can be operated at the same time.

First, in the case of application to a horizontal synchronizing circuit,
Since the PLL circuit has released the pulled-in state, the PLL circuit starts re-pulling in when the adjustment period ends, and the upper portion of the screen appears to bend (pull).
Since the phase with the input signal gradually shifts while the VCO is in the free run, it is necessary to pull in the extra phase difference at the time of re-pulling in, and the pull-in transient response waveform has a tail to the pattern.

Further, in the case of the example applied to the IF of the video signal, although it operates stably by another function called AFT,
Since it is necessary to set the time constant of the adjusting circuit to be considerably long (KHz order), there is a problem that it is difficult to incorporate the time constant into the IC.

In any case, since the system cannot adjust and operate the PLL at the same time, it is necessary to take special measures in the system operation in which the PLL circuit is placed.

[0008]

SUMMARY OF THE INVENTION The conventional PLL described above.
The circuit is a system that cannot operate the adjustment of the free-run frequency of the PLL and VCO at the same time.
Special measures need to be taken in the operation of a system with L circuits.

An object of the present invention is to provide a PLL circuit which can adjust the VCO frequency without opening the PLL loop and can simultaneously operate the adjusting circuit and the PLL circuit without taking any special means. To do.

[0010]

In order to solve the above-mentioned problems, the PLL circuit of the present invention comprises a VCO whose oscillation frequency is controlled by current or voltage.
Based on a first control signal for controlling the oscillation frequency of
The first P that locks to the oscillation frequency according to the input signal
LL circuit and the VCO selected at a predetermined timing
The basis of any of the oscillation frequency and the reference frequency
A second control signal for controlling the oscillation frequency of the VCO and adding the second control signal to the first control signal;
And two PLL circuits. Also,
A PLL circuit of the present invention is the PLL circuit described above, further comprising a reference signal generating means for generating a reference signal of an adjustment reference frequency, and adjusting the reference frequency based on the adjustment reference frequency of the reference signal. A third control signal is generated, and the first control signal and the third control signal are generated.
The VC according to the first control signal based on the control signal of
An adjusting unit that adjusts the reference frequency so that the control amount of O and the adjustment amount of the reference frequency are equal to each other may be provided.

According to the above means, the control information for controlling the VCO when there is no input signal is zero, and the VCO oscillates at the free run frequency. At this time, the convergence point of the second PLL circuit is not shifted from the predetermined value, so the free-run frequency is adjusted to the predetermined frequency. When the input signal arrives, even if the first PLL circuit locks at a frequency deviated from the free-run frequency, the convergence point of the second PLL circuit shifts by the same amount as the deviation, so that the free-run frequency is relatively high. Can be detected and adjusted.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. A case where the present invention is applied to a horizontal synchronizing circuit as an embodiment of the PLL circuit of the present invention will be described with reference to FIG.

In FIG. 1, a VCO 11 and a countdown (C / D) circuit 12 for dividing the oscillation signal thereof, a phase comparison circuit 14 for inputting the counted down oscillation signal and a synchronization signal input from an input terminal 13, and The PLL circuit 100 is configured with the loop filter 15. The control current Δi output from the loop filter 15 is fed back to the VCO 11 via the adder 16, and the other input of the adder 16 is supplied with the control current Io from the adjusting circuit 200.

The adjustment circuit 200 includes a reference signal generator 21, a switch SW1, an f-I conversion circuit 22, and a CCO control circuit 2.
3, the FI control circuit 24 and the convergence point shift circuit 25, the oscillation signal from the VCO 11 of the PLL circuit 100 is input to one terminal of the switch SW1, and the control current from the CCO control circuit 23 to the PLL circuit 100. Output Io. Switches SW1 and SW2, CCO control circuit 23,
The f-I control circuit 24 is supplied with the pulse P1 signal from the timing signal generator 31 to control its operation.

Here, for simplicity of explanation, it is assumed that the reference signal frequency of the reference signal generator 21 is equal to the free-run frequency of the VCO 11.

First, the case where the synchronizing signal is not input to the input terminal 13 of the PLL circuit 100 will be described. Entering
Since the power signal has not arrived, the output of the phase comparison circuit 14
Nothing appears in the control current Δi from the loop filter 15.
Is not output . At this time, the VCO 11 oscillates at the free-run frequency determined by the control current Io output from the CCO control circuit 23.

The timing signal generator 31 periodically generates a pulse P1 regardless of the presence or absence of a synchronizing signal. The control state of each circuit by the pulse P1 is shown in FIG.

That is, when the pulse P1 is at H level, the switch SW1 selects the reference signal from the reference signal generator 21, and the active filter 22a and the phase comparator 22b are selected.
Output to the f-I conversion circuit 22. The active filter 22a is set to have a phase characteristic of 90 degrees at the reference signal frequency, and the phase comparator 22b performs phase comparison between the input signal of the active filter 22a and the signal that has passed through it. The CCO control circuit 23 holds the state when the pulse P1 is at the L level (HOL
D) and does not respond to the phase comparison output. The f-I control circuit 24 is turned on, inputs the phase comparison result, outputs the control current I1, and simultaneously stores the phase comparison output in the capacitor C2. The convergence point shift circuit 25 includes an adder 25a and a switch SW2. Switch SW2 is O
It is FF (open) and cuts off the path for transmitting the control current Δi from the loop filter 15 to the adder 25a.
Therefore, the convergence point shift circuit 25 outputs the control current I1 as the control current I2, and controls the frequency of the f-I conversion circuit 22.

In this way, the f-I conversion circuit 22 outputs f-
The path to the I control circuit 24 and the convergence point shift circuit 25 constitutes a loop, and the response of the active filter 22a to the reference signal is converged so as to have a phase of 90 degrees. When the pulse P1 is at H level, the f-I conversion characteristic is adjusted as a pre-process for adjusting the VCO 11.

When the pulse P1 is at L level, the switch S
W1 selects the oscillation signal of the VCO 11 and supplies it to the f-I conversion circuit 22. The CCO control circuit 23 is turned on and f-I
Since the control circuit 24 holds (HOLD) the state when the pulse P1 is at the H level, the CCO control circuit 23 inputs the phase comparison output and outputs the control current Io to the PLL circuit 100.
Output to. At the same time, the phase comparison output is stored in the capacitor C1. The switch SW2 is ON (closed),
The control current Δi from the loop filter 15 is supplied to the adder 16, but since the PLL circuit 100 is in the no input signal state, the control current Δi is zero and the control current I2 to the active filter 22a is the control current I2. I1 only, f
The -I conversion characteristic continues to be adjusted with respect to the reference signal. The path from the f-I conversion circuit 22 to the CCO control circuit 23 and then to the VCO 11 constitutes a loop.
Active filter 22a at the oscillation frequency of O11
The oscillation frequency of the VCO 11 is controlled so that the input / output phase of the VCO 11 has a phase difference of 90 degrees, and finally the oscillation frequency of the VCO 11 is made equal to the reference signal frequency. Therefore, the pulse P1
When it is at the L level, the oscillation frequency of the VCO 11 is adjusted.

Next, the case where the synchronizing signal is input to the input terminal 13 will be described. After the free-run frequency adjustment of the VCO 11 is completed, it is assumed that the horizontal synchronizing signal deviated from the predetermined frequency arrives at the input terminal 13 and the PLL circuit 100 can be locked. At this time, the loop filter 15 outputs a non-zero control current Δi.

When the pulse P1 of the timing signal generator 31 is at the H level, the switch SW2 is turned off (open), so that the adjustment of the f-I conversion characteristic is refreshed by the same operation as described above.

When the pulse P1 is at L level, VCO11
The oscillating frequency from is supplied to the f-I conversion circuit 22.
At this time, the switch SW2 is ON, and the control current Δi
Is supplied to the adder 16. VCO1 by control current Δi
If the frequency control amount of 1 and the frequency shift amount of the f-I conversion characteristic are made substantially equal, the f-I conversion frequency characteristic is shifted by an amount equal to the frequency difference in which the frequency of the synchronization signal deviates from the predetermined frequency The oscillation frequency of the locked VCO 11 and the f-I conversion characteristic become equal. Then, in the f-I conversion circuit 22, there is a 90-degree phase difference in the oscillation signal of the VCO 11 despite the deviation from the predetermined frequency, so the control current Io does not change, and it is in the adjusted state when there is no input signal, that is, in the free state. The run frequency adjustment state is maintained.

Therefore, even when the PLL circuit 100 is locked at the frequency offset from the predetermined frequency, the adjustment circuit 200 and the PLL circuit 100 are operated at the same time, and there is no failure.

Even when the adjustment of the free-run frequency of the VCO 11 is incomplete, the adjustment can be reliably performed even if the PLL circuit 100 locks to the synchronization signal. The following is a description of this matter.

It is assumed that the synchronization signal higher than the predetermined frequency arrives when the free-run frequency is still lower than the predetermined frequency. The control current Δi output from the loop filter 15 is larger than the current generated when the adjustment was originally completed. The frequency characteristic of the f-I conversion circuit 22 to which this is input is shifted to a higher frequency beyond the oscillation frequency of the VCO 11, and the convergence point and the actual VCO
A difference occurs in the oscillating frequency of 11, and the f-I conversion circuit 22 can detect the phase difference, and the VCO 1 is detected via the CCO control circuit 23.
The oscillation frequency of 1 is controlled to be high. Since the f-I conversion circuit 22 is adjusted by the reference signal as an absolute value,
Even when the free-run frequency of the VCO 11 and the f-I conversion frequency do not match, the locked control current causes both to move in parallel on the frequency axis. Therefore,
The frequency difference can be detected even after locking, that is, after translation.

Explaining from the aspect of the PLL loop configuration, V
The first PLL circuit including CO11 performs P
In the LL circuit 100, the f-I conversion circuit 22 to CC
A loop that feeds back to the VCO 11 via the O control circuit 23 constitutes a second PLL circuit and functions as automatic frequency control (AFC) of the VCO 11. From the f-I conversion circuit 22 to f-I
The loop that returns to the f-I conversion circuit 22 via the control circuit 22 is the third PLL circuit, which operates as automatic adjustment of the f-I conversion frequency characteristic. Therefore, a triple PLL loop configuration is obtained.

In this embodiment, f of the adjusting circuit 200 is
By performing the -I conversion, that is, shifting the frequency detection reference, the free-run frequency can be indirectly adjusted without using the open loop, and the PLL circuit 100 and the adjustment circuit 200 can be operated simultaneously. That is,
Even when locked to the horizontal sync signal of the video signal, it is not necessary to unlock the lock during the vertical blanking period to set the free-run frequency, and it is possible to prevent bending (pulling) at the top of the screen.

In the description of FIG. 1, the frequency of the oscillation signal of the VCO 11 is described as being controlled by the current, but it may be controlled by the voltage. Further, the f-I conversion circuit 22 for converting the frequency to the current may be an f-V conversion circuit for converting the voltage, and the f-I control circuit 24 is an f-V control circuit for controlling the voltage. It may be. Further, the CCO control circuit 23 that controls the oscillation frequency of the VCO 11 with a current may also be a VCO control circuit that controls with a voltage.

Various modifications and uses of the present invention are conceivable, which will be described below. In the control of each circuit by the pulse P1, the period in which the switch SW1 is set to the reference signal side is a period necessary for refreshing the adjustment of the f-I conversion circuit 22, and the capacitor C2 due to the leakage of the bipolar element or the like. If potential fluctuations are expected, it is necessary to switch cyclically. As described above, the control current Io and the voltage of the capacitor C1 maintain the same state once the adjustment has converged. That is,
Since it is only refreshed, there is no problem even if the cycle of the pulse P1 is unrelated to the operation of the PLL circuit 100.

Further, the timing generation circuit 31 shown in FIG. 1 is configured so that, for example, if a timing signal suitable for the output of the countdown circuit 12 is obtained, the countdown circuit 12 is generated.
It is also possible to omit the timing signal generator 31 by supplying the pulse P1 so that it becomes H during a proper period.

In the case of a TV receiver having a horizontal synchronizing circuit,
There is a crystal oscillation circuit in the color subcarrier reproduction circuit section for receiving the color signal, and if a reference signal of the color subcarrier frequency is obtained from this, it is not necessary to separately prepare a reference signal generator. When applied to the processing of the IF signal of the video signal, the present invention can perform the adjustment refresh at high speed even during the AFT pull-in, that is, even when the input IF frequency has not reached a predetermined value. Therefore, it is not necessary to set the holding time constant of the adjusting circuit 200 to the order of several KHz,
For example, at about 100 KHz, it is possible to fully incorporate the IC.

Further, in FIG. 1, the f-I conversion circuit 22 has been described as a phase shift circuit using an active filter. V
When the same shift amount cannot be obtained with the same control current Δi for CO and f-I conversion, an amplifier 25b (or an attenuation circuit) is provided in the convergence point shift circuit 25 as shown in FIG. It is possible to give the same frequency control sensitivity to and f-I conversion.

As a special case, when frequency detection is performed digitally, the f-I conversion circuit 22 itself is changed to f.
It may not be necessary to make adjustments via the -I control circuit 24. For example, in the case where a window obtained by dividing the reference signal is created and the frequency is detected by the number of cycles of the oscillation signal of the VCO 11 that enters the window, the window signal is already the absolute reference of FI conversion, No more cycles to adjust this. Therefore, the means for converging the frequency characteristic of the f-I conversion is not a necessary condition, but an active filter or V which fluctuates when incorporated in an IC.
Required when CO is used for f-I conversion.

Further, in the above description, it was assumed that the reference signal frequency of the reference signal generator 21 and the frequency of the oscillation signal of the VCO 11 were the same, but in many cases only different frequencies are actually obtained, and in this case. Will be described as a modification of FIG. 1 together with the block diagram of FIG.

In this case, after the f-I conversion is adjusted by the reference signal, when the oscillation frequency of the VCO 11 is detected, f
The -I conversion characteristic may be shifted. f-I conversion circuit 22
Itself or f-I conversion circuit 22 and convergence point shift circuit 2
An amplifying (attenuating) circuit 41 is installed between 5. A pulse P1 is used as a control signal for the amplifier circuit 41.

For example, the oscillation frequency of the VCO 11 is 500
KHz, 700 KHz from the reference signal generator 21
When the pulse P1 for operating the f-I control circuit 24 is at the H level, the input / output ratio of the switching means is set to 1 and the f-I conversion characteristic is converged at 700 KHz. When the pulse P1 becomes L level and the VCO oscillation signal is input to the f-I conversion circuit 22, the input / output ratio of the switching means is set to 5/7 and the f-I conversion characteristic is shifted to 500 KHz.

Using such a technique, the reference signal and VC
Even when the O oscillation frequency is different, the effect of the invention can be sufficiently exerted. In this case, the amplification (attenuation) circuit 41
Instead, the same is true by providing a means for switching the input / output characteristics based on a certain set ratio, such as a DA conversion circuit.

Further, the PLL circuit 100 of FIG. 1 has the countdown circuit 12 because the horizontal synchronizing circuit is taken as an example, but it is conceivable to delete the countdown circuit for general use, and adjustment is possible. Changes such as taking the signal input to the circuit 200 from the countdown circuit 12 instead of the output of the VCO 11 do not impair the gist of the present invention.

As described above, in the PLL circuit of the present invention, P
Since the LL circuit 100 and the adjustment circuit 200 can operate at the same time, and only the operation of the adjustment circuit 200 is temporarily suspended in order to refresh the adjustment state of the fV conversion characteristic of the adjustment circuit 200 itself, the operation of the PLL circuit 100 is basically performed. Does not have to stop. Therefore, the present invention can be applied to, for example, a PLL circuit for audio processing, which could not be provided with the adjusting circuit 200 for performing free-run adjustment in the conventional open loop. Taking a TV receiver as an example, an audio signal is FM-modulated at 4.5 MHz, and therefore a PLL circuit for demodulating the audio signal is required on the receiver side. This PLL
By using the circuit of the present invention for the circuit, it is possible to incorporate the holding capacitor into the IC as described in the IF example.

[0041]

As described above, in the circuit of the present invention, it is possible to adjust the frequency of the PLL circuit in the free-run state or in the no-signal state without making the PLL circuit into an open loop, and at the same time, the adjustment circuit and the PLL circuit can be simultaneously adjusted. Since it can operate, it can be applied to general applications.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining an embodiment of the present invention.

2 is a timing diagram used to describe the operation of FIG.

FIG. 3 is a block diagram for explaining a modified example of the present invention.

FIG. 4 is a block diagram for explaining another modification of the present invention.

[Explanation of symbols]

100 ... PLL circuit, 11 ... VCO, 12 ... Countdown circuit, 13 ... Input terminal, 14 ... Phase comparison circuit, 15
... loop filter, 200 ... adjustment circuit, 21 ... reference signal generator, 22 ... f-I conversion circuit, 23 ... CCO control circuit, 24 ... f-I control circuit, 25 ... convergence point shift circuit,
SW1, SW2 ... Switch, 31 ... Timing signal generator.

Claims (10)

(57) [Claims] 1. A VCO having an oscillation frequency controlled by current or voltage , and controlling the oscillation frequency of the VCO.
A first PLL circuit that locks to an oscillation frequency according to an input signal based on a first control signal for controlling the VCO, and the VCO based on either an oscillation frequency or a reference frequency of the VCO selected at a predetermined timing. Oscillation
And a second PLL circuit for generating a second control signal for controlling the frequency and adding the second control signal to the first control signal. 2. A VCO whose oscillation frequency is controlled by current or voltage is provided, and the oscillation frequency of the VCO is controlled.
A first PLL circuit that locks to an oscillation frequency according to an input signal based on a first control signal for controlling the VCO, and the VCO based on either an oscillation frequency or a reference frequency of the VCO selected at a predetermined timing. Oscillation
A second PLL circuit for generating a second control signal for controlling the frequency and adding the second control signal to the first control signal; and a reference signal generating means for generating a reference signal of an adjustment reference frequency. And a third control signal for adjusting the reference frequency based on the adjustment reference frequency of the reference signal, and the first control based on the first control signal and the third control signal. An adjusting means for adjusting the reference frequency so that the control amount of the VCO by a signal and the adjustment amount of the reference frequency are equal to each other.
LL circuit. 3. The first PLL circuit comprises an adding means for adding the second control signal to the first control signal, and the second PLL circuit sets the frequency of an input signal to the second control signal.
F− for converting to a current (or voltage) as a control signal of
A first (or f-V) converting means and a first signal for selectively supplying either the oscillation signal of the VCO or the reference signal of the reference signal generating means to the f-I (or f-V) converting means. The switching means and the f-I (or f-V) when the first switching means selects the oscillation signal of the VCO.
Supply means for supplying the output current (or voltage) of the converting means to the adding means, and the adjusting means includes the first control signal when the first switching means selects an oscillation signal of the VCO. And a shift means for shifting the reference frequency of the second PLL circuit based on the third control signal, and the f-I when the first switching means selects the reference signal of the reference signal generating means. (Or f-V) conversion means generates the third control signal and outputs the third control signal to the shift means, and when the first switching means selects an oscillation signal of the VCO, the third control signal is generated. F-I (or f- that holds the signal
The PLL circuit according to claim 2, further comprising V) a control unit. 4. The shift means comprises an adder and a second switching means, adds the third control signal and the first control signal via the second switching means, and adds the sum. The PLL circuit according to claim 3, wherein an output is supplied to the f-I (or f-V) conversion means. 5. The PLL circuit according to claim 4, further comprising a timing signal generator that controls operation timings of the second PLL circuit and the adjusting means. 6. The amplifying (or attenuating) means is provided between the first control signal output of the first PLL circuit and the second switching means. The described PLL circuit. 7. An amplification (or attenuation) circuit is connected between the f-I (or f-V) control means and the adder,
The PLL circuit according to claim 5, wherein an amplification (or attenuation) ratio is controlled by the timing signal. 8. The PLL circuit according to claim 5, wherein, instead of the timing signal generated by the timing signal generator, a signal obtained from a countdown circuit for the oscillation signal of the VCO is used as the timing signal. 9. The input signal of the first PLL circuit is a synchronizing signal forming a composite video signal, and the reference signal is a crystal oscillation signal of a color subcarrier reproduction circuit or a frequency division signal thereof. 9. The PLL according to claim 2, which is characterized in that
circuit. 10. The input signal of the first PLL circuit is:
5. The PLL circuit according to claim 4, wherein the f-I (or f-V) control unit is a video IF signal, and is provided with a holding capacitor that holds the third control signal.