JP3080474B2 - PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MUSE signal processing circuit, and to the control of a PLL circuit.

[0002]

2. Description of the Related Art MUSE (Mul)
single Sub-NyquistSampling
In the encoding method, a frame pulse is added to the first two lines of each frame, and a horizontal synchronization signal is added to the first line of each line. In this MUSE signal decoder, a PLL (Phase Locked Lo) is used.
An op) circuit is used to generate a clock signal that is phase-synchronized with the horizontal synchronizing signal, and supplies the clock signal to each digital signal processing circuit. The PLL circuit includes a phase error detector, a low-pass filter,
The input horizontal synchronizing signal and the oscillating signal of the VCO, that is, the clock signal, operate by maintaining a predetermined phase relationship by the closed loop including the loop filter, the voltage amplifier, and the voltage controlled oscillator (VCO). This PLL circuit desirably has a wide synchronization pull-in range from a non-synchronization state such as channel switching to pulling in a frequency and a phase.
Therefore, if the loop gain is set to a large value, the phase jitter in the synchronized state increases and the stability deteriorates. Therefore, the response characteristics of the PLL circuit are set in order to obtain an optimum balance between the synchronization pull-in range and the synchronization stability. However, as a signal source of the MUSE signal, there is a high definition VTR, a MUSE signal generator, or the like in addition to the high definition broadcasting by satellite. For the above-mentioned reason, the synchronization pull-in range does not have a large margin, and therefore, when the signal source is switched, P
A case occurs where the LL is not retracted. For this reason, the offset voltage has been manually readjusted and synchronized.

FIG. 2 shows an example of a voltage amplifying circuit and an offset adjusting circuit which are part of a conventional PLL circuit . In the figure, 1 is an input terminal, and the horizontal synchronization of the MUSE signal
The ratio based on the signal and the clock signal that is the output of the PLL circuit
Phase error detection that outputs a voltage corresponding to the phase difference with the comparison signal.
Obtained through a low-pass filter that integrates the output voltage at the output
The voltage e1 is input. 2 is a voltage amplifier which has an input voltage e
1 is amplified (gain A1) to output a voltage e2, and a secondary loop gain of the PLL circuit is determined. Lowpass filter
The obtained voltage e1 is input to the input terminal 1 of the voltage amplifier 2,
Constructs a loop filter section that amplifies and outputs voltage e2
Then, the output voltage e2 is subjected to a predetermined process, and the voltage controlled oscillator (V
CO). R1 and R2 are feedback resistors, which determine the voltage gain A1 of the voltage amplifier 2, and A1 ≒ (R1 + R
2) It becomes / R2. 3 is a connection terminal for connecting an offset voltage, C1 is a smoothing capacitor, and the PLL circuit is synchronized.
The fluctuation cycle of the output voltage of the voltage amplifier 2 when
The offset voltage generating circuit 4 keeps the voltage of the offset voltage connection terminal 3 constant. The offset voltage generating circuit 4 includes an offset adjustment volume VR1, a power supply Vcc, and outputs an adjustable offset voltage. Conventionally, the offset voltage has been readjusted each time the asynchronous state in which the PLL goes out of synchronization by the circuit as described above.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described circumstances, and maintains synchronization stability in a synchronized state, and performs switching of a MUSE signal by switching a signal source.
In asynchronous state in which the out-of-sync LL circuit, the readjustment of the offset which has been performed manually, there is provided a PLL circuit that is automatically performed.

[0005]

In order to solve the above-mentioned problems, the present invention detects a phase difference between a horizontal synchronizing signal and a comparison signal based on a clock signal, and outputs a voltage corresponding to the difference.
Integrating that a phase error detector, the output of the phase error detected sound
Low pass filter and amplifies the voltage obtained by this integration.
A loop filter unit consisting of a voltage amplifier that, this route
Input of the output of the voltage amplifier in the
And a voltage-controlled oscillator for controlling the oscillation frequency .
In a PLL circuit that generates and outputs a clock signal that is phase-synchronized with a horizontal synchronization signal, the output voltage of the voltage amplifier is
A differential amplifier having a constant reference voltage as an input;
When the LL circuit is in an asynchronous state, the output of the differential amplifier is
A switch that opens and closes based on the synchronous / asynchronous control signal
Therefore, the input voltage is substantially offset to the input of the voltage amplifier.
A PLL circuit configured to feed back a value is provided.

[0006]

With the above construction, the PL according to the present invention is provided.
In the L circuit, when the PLL is asynchronous, the output voltage of the voltage amplifier of the loop filter section is compared and amplified with the reference lightning pressure by the differential amplifier, and the output is a synchronous / asynchronous control signal.
Is fed back to the input of the voltage amplifier via a switch that opens and closes based on . As a result, the voltage of the difference from the reference voltage is substantially offset, and the PLL is automatically synchronized. Once synchronized, the switch breaks the feedback loop and returns to normal PLL operation. Accordingly, when the signal source of the MUSE signal is switched, the PLL is automatically pulled in and locked when the PLL loses synchronization.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a main part circuit diagram showing an embodiment of a PLL circuit according to the present invention. In the figure, the same parts as those in FIG. 2 are denoted by the same reference numerals, and the duplicate description will be omitted. In the figure,
Reference numeral 5 denotes a differential amplifier which receives the output e2 of the voltage amplifier 2 and the reference voltage E1 as inputs, and outputs a voltage e corresponding to the difference voltage between the outputs e2 and E1.
3 is output. The resistors R3, R4, R5 and R6 determine the gain A2 of the differential amplifier 5. Reference numeral 6 denotes an analog switch, which connects the voltage e3 to the offset voltage connection terminal 3 via a resistor R7 according to a control signal input to a terminal 7. Reference numeral 4 denotes an offset voltage generation circuit including the above-described units.

Next, the operation of the PLL circuit according to the present invention will be described. First, the operation of the differential amplifier 5 will be described. Now
The resistors R3, R4, R5 and R6 are set as follows: R3 = R5, R4 =
If the relationship is selected as R6, the following equation is obtained. e3 = R4 / R3 (e2-E1) = A2 (e2-E1) That is, in the differential amplifier 5, the gain A2 is determined by the ratio of the resistors R4 and R3, and the voltage e3 is proportional to the difference voltage between the voltages e2 and E1. Is output. Next, assuming that a MUSE signal source is set based on, for example, a MUSE signal generator,
The reference voltage E1 is selected as the value of the output voltage e2 of the voltage amplifier 2 in the synchronous state of the PLL at this time. The control terminal 7 receives a PLL synchronous / asynchronous control signal.
With this signal, the analog switch 6 is switched to the lower side in the figure when synchronous, and to the upper side when asynchronous. Now, O is out of synchronization by the switching of the signal source or the like of MUSE
When the asynchronous state occurs, the above-described differential amplifier 5
Is connected to the input of the voltage amplifier 2 via the analog switch 6 and the offset voltage connection terminal 3 to form a feedback loop. As a result, the difference voltage between the voltages e2 and E1 is 1 / (1 + A1 · A
It is compressed in 2) and drives the operation of the PLL into a synchronous state.
When the synchronous state is entered, the feedback loop is cut off by the analog switch 6, and the operation returns to the normal PLL operation. The value of A1 · A2 (the product of the gains of the voltage amplifier 2 and the differential amplifier 5) indicating the feedback amount is set according to the conditions of the PLL circuit.

[0009]

As described above, according to the present invention, P
In the LL circuit, when the PLL is asynchronous, the loop
The output voltage of the voltage amplifier of the filter unit is compared with the reference voltage by the differential amplifier, and the output is fed back to the input of the voltage amplifier so as to be offset. Therefore, the PLL in the case where the signal source of the MUSE signal is switched. Out of sync,
There is an effect that the lock is automatically pulled in and locked without manually re-adjusting the offset.

[Brief description of the drawings]

FIG. 1 is a main part circuit diagram showing one embodiment of a PLL circuit according to the present invention.

FIG. 2 shows an example of a voltage amplification circuit and an offset adjustment circuit that are part of a conventional PLL circuit .

[Explanation of symbols]

 Reference Signs List 1 input terminal 2 voltage amplifier 3 offset voltage connection terminal 4 offset voltage generation circuit 5 differential amplifier 6 analog switch 7 control terminal

Claims (1)

(57) [Claims] 1. A phase error detecting section for detecting a phase difference between a horizontal synchronizing signal and a comparison signal based on a clock signal, and outputting a voltage corresponding to the phase difference, and a low band integrating an output of the phase error detecting section. A loop filter section including a transmission filter and a voltage amplifier for amplifying a voltage obtained by integration, a voltage control oscillator section for inputting an output of the voltage amplifier of the loop filter section as a control voltage and controlling an oscillation frequency; A PLL circuit for generating and outputting a clock signal phase-synchronized with a horizontal synchronization signal, wherein a differential amplifier having an input of an output voltage of the voltage amplifier and a predetermined reference voltage is provided, and the PLL circuit is in an asynchronous state. And a switch for opening and closing the output of the differential amplifier based on a synchronous / asynchronous control signal .
Setting the value of the output voltage to the predetermined reference voltage,
Voltage and output of the voltage amplifier when the PLL circuit is in an asynchronous state
The voltage so that the voltage of the difference from the voltage becomes the offset voltage.
A PLL circuit configured to feedback-input to a voltage amplifier .