JP2000091914A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL circuit that allows a frequency of a VCO of which to be adjusted without the need of opening a PLL loop and simultaneously operate an adjustment circuit without the need of any special means. SOLUTION: A free-running frequency of a VCO 11 of the PLL circuit 11 can be adjusted without opening a PLL loop of the PLL circuit 100. An adjustment circuit is provided with an f-I conversion circuit 22, which has been adjusted by using a reference signal of a reference signal generator 21 in advance, an f-I conversion characteristic of the circuit 22 is shifted, based on a control signal Δi that is information to control the VCO 11 of the PLL circuit 100 by a same quantity in the case of applying f-I conversion to an oscillated signal from the VCO 11 so as to make a conversion axis of the oscillated signal equal to that of a locked frequency thereby controlling the VCO 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention is particularly suitable for use in horizontal synchronization processing and IF signal processing of a TV receiver.
The present invention relates to a highly versatile PLL circuit including a VCO built in C and adjustment of its free-run frequency.

[0002]

2. Description of the Related Art When a PLL circuit is built in an IC, the
A problem arises in the free-run frequency variation of the voltage controlled oscillator (VCO), which is a component of the PLL circuit, due to the variation of the time constant in the manufacturing process. When the input signal arrives at the PLL circuit and the VCO is locked, the oscillation frequency of the VCO is equal to the input signal frequency, so that special means is required to detect the free-run frequency. Since the input signal frequency cannot be specified in a general PLL circuit application, the oscillation frequency of the VCO cannot be adjusted to a predetermined value in a locked state. If the adjustment circuit and the PLL circuit are operated at the same time, the control of both will be contradictory.
This is because the LL function breaks down. An example in which the PLL is adjusted under such restrictions will be described.

[0003] Japanese Patent Application Laid-Open No. 9-233366, "Horizontal Synchronous Circuit" is used as an example of a horizontal synchronous reproducing section of a TV receiver. Here, utilizing the fact that the horizontal synchronous PLL circuit stops pulling in during the vertical retrace period, the frequency control of the PLL circuit is stopped (open looping) only during this period, and the VCO is oscillated at the free-run frequency. At the same time, the adjustment circuit is operated during this retrace period to adjust the free-run frequency to a desired value. The horizontal synchronization PLL circuit and the adjustment circuit are operated in a time division manner.

As an example in which a PLL circuit is used for an intermediate frequency (IF) processing section of a TV receiver, Japanese Patent Application Laid-Open No. 7-30412 discloses a "PLL circuit and a TV signal processing apparatus using the same". Here, in order to reproduce the IF frequency signal, P
An LL circuit is provided and operates simultaneously with the adjustment circuit. By setting the time constant of the adjustment circuit longer than the time constant of the PLL circuit, the adjustment circuit does not immediately respond even if the incoming signal frequency deviates from the adjustment convergence point. In the meantime, the error information is reflected through another tuner path called an AFT loop, and the input signal frequency of the PLL circuit is controlled to be equal to the adjustment convergence point. Therefore,
The PLL and the adjustment can operate simultaneously.

First, in the case of application to a horizontal synchronization circuit,
Since the PLL circuit has released the pulled-in state, when the adjustment period ends, the PLL circuit starts re-pulling, and the upper part on the screen is bent (pulled) and appears.
Since the phase with the input signal gradually shifts while the VCO is in the free-run state, it is necessary to pull in the extra phase difference at the time of re-pulling, and the pull-in transient response waveform trails to the picture.

Further, in the case of applying the present invention to the IF of a video signal, although it operates stably by another function called AFT,
Since it is necessary to make the time constant of the adjustment circuit considerably long (in the order of KHz), there is also a problem that it is difficult to integrate the time constant into an IC.

In any case, since the adjustment and the PLL cannot be operated at the same time, it is necessary to take special measures in the system operation in which the PLL circuit is placed.

[0008]

The above-mentioned conventional PLL
The circuit is a system that cannot operate the PLL and VCO free-run frequency adjustment at the same time.
Special measures need to be taken in the operation of a system with L circuits.

An object of the present invention is to provide a PLL circuit which can adjust the frequency of a VCO without opening a PLL loop and can simultaneously operate the adjustment circuit and the PLL circuit without taking any special measures. Is to do.

[0010]

In order to solve the above-mentioned problems, a PLL circuit according to the present invention includes a first PLL circuit that locks to an oscillation signal of a VCO whose oscillation frequency is controlled by current or voltage. A second PLL circuit for detecting the oscillation frequency of the VCO based on a reference frequency and controlling the oscillation frequency of the VCO, and control information for controlling the oscillation frequency of the VCO to the second PLL circuit. It comprises a shift means for supplying and shifting the reference frequency, and a timing signal generator for controlling operation timing of the second PLL circuit and the shift means.

According to the above means, the control information for controlling the VCO when there is no input signal is zero, and the VCO oscillates at the free-run frequency. At this time, since the convergence point of the second PLL circuit is not shifted from a predetermined value, the free-run frequency is adjusted to a predetermined frequency. When the input signal arrives, even if the first PLL circuit locks at a frequency shifted from the free-run frequency, the convergence point of the second PLL circuit is also shifted by the same amount as the shift, so that the free-run frequency is relatively high. Can be detected and adjusted.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings. Referring to FIG. 1, a case where the present invention is applied to a horizontal synchronization circuit as an embodiment of the PLL circuit will be described.

In FIG. 1, a VCO 11 and a countdown (C / D) circuit 12 for dividing the oscillation signal thereof, a phase comparison circuit 14 for inputting the counted-down oscillation signal and a synchronization signal input from an input terminal 13, and The PLL circuit 100 is configured from the loop filter 15. The control current △ i output from the loop filter 15 is fed back to the VCO 12 via the adder 16 and supplies the control current Io from the adjustment circuit 200 to the other input of the adder 16.

The adjustment circuit 200 includes a reference signal generator 21, a switch SW1, an fI conversion circuit 22, and a CCO control circuit 2.
3. An oscillation signal from the VCO 11 of the PLL circuit 100 is input to one terminal of the switch SW1, and the control current from the CCO control circuit 23 is supplied to the PLL circuit 100. Outputs Io. Switches SW1, SW2, CCO control circuit 23,
The fI control circuit 24 is supplied with the pulse P1 signal from the timing signal generator 31, and controls the operation.

Here, for the sake of simplicity, it is assumed that the reference signal frequency of the reference signal generator 21 is equal to the free-run frequency of the VCO 11.

First, a case where no synchronization signal is input to the input terminal 13 of the PLL circuit 100 will be described. The control current Δi output from the loop filter 15 in the no-signal state is zero. At this time, the VCO 11 oscillates at a free-run frequency determined by the control current Io output from the CCO control circuit 23.

The timing signal generator 31 periodically generates a pulse P1 regardless of the presence or absence of a synchronization signal. FIG. 2 shows a control state of each circuit by the pulse P1.

That is, when the pulse P1 is at the H level, the switch SW1 selects the reference signal from the reference signal generator 21, and switches the active filter 22a and the phase comparator 22b.
To the f-I conversion circuit 22 composed of The active filter 22a is set to have a phase characteristic of 90 degrees at the reference signal frequency, and the phase comparator 22b compares the phase of the input signal of the active filter 22a with the signal passed therethrough. The CCO control circuit 23 holds the state when the pulse P1 is at the L level (HOL
D) and does not respond to the phase comparison output. The fI control circuit 24 is turned on, inputs the phase comparison result, outputs the control current I1, and simultaneously stores the phase comparison output in the capacitor C2. The convergence point shift circuit 25 includes an adder 25a and a switch SW2. The switch SW2 is
It is FF (open) and cuts off the path for transmitting the control current △ i from the loop filter 15 to the adder 25a.
Therefore, the convergence point shift circuit 25 outputs the control current I1 as the control current I2, and controls the frequency of the f-I conversion circuit 22.

As described above, the f-I conversion circuit 22 outputs
The path to the I control circuit 24 and the convergence point shift circuit 25 forms a loop, and converges so that the response of the active filter 22a to the reference signal has a phase of 90 degrees. When the pulse P1 is at the H level, the f-I conversion characteristic is adjusted as preprocessing for adjusting the VCO 11.

When the pulse P1 is at L level, the switch S
W1 selects an oscillation signal of the VCO 11 and supplies it to the f-I conversion circuit 22. The CCO control circuit 23 is turned on and f-I
Since the control circuit 24 holds (HOLD) the state when the pulse P1 is at the H level, the CCO control circuit 23 inputs the phase comparison output and outputs the control current Io to the PLL circuit 100.
Output to At the same time, the phase comparison output is stored in the capacitor C1. Switch SW2 is ON (closed),
The control current △ i from the loop filter 15 is supplied to the adder 16, but since the PLL circuit 100 is in the non-input signal state, the control current △ i is zero, and the control current I2 to the active filter 22a is the control current. I1 only, f
The -I conversion characteristic remains adjusted with respect to the reference signal. The path from the f-I conversion circuit 22 to the CCO control circuit 23 and to the VCO 11 forms a loop.
Active filter 22a at an oscillation frequency of O11
The oscillation frequency of the VCO 11 is controlled so that the input / output phase of the VCO 11 becomes a phase difference of 90 degrees, and finally the oscillation frequency of the VCO 11 is made equal to the reference signal frequency. Therefore, when the pulse P1 is at the H level, the oscillation frequency of the VCO 11 is adjusted.

Next, a case where a synchronization signal is input to the input terminal 13 will be described. It is assumed that after the free-run frequency adjustment of the VCO 11 is completed, a horizontal synchronizing signal shifted from a predetermined frequency arrives at the input terminal 13 and the PLL circuit 100 can be locked. At this time, a non-zero control current △ i is output from the loop filter 15.

When the pulse P1 of the timing signal generator 31 is at the H level, the switch SW2 is turned off (open), so that the adjustment of the fI conversion characteristic is refreshed by the same operation as described above.

When the pulse P1 is at the L level, the VCO 11
Is supplied to the f-I conversion circuit 22.
At this time, the switch SW2 is ON and the control current △ i
Is supplied to the adder 16. VCO1 by control current △ i
When the frequency control amount of 1 and the frequency shift amount of the f-I conversion characteristic are made substantially equal, the f-I conversion frequency characteristic is shifted by the same amount as the frequency difference in which the frequency of the synchronization signal deviates from a predetermined frequency. The oscillation frequency of the locked VCO 11 and the fI conversion characteristic become equal. Then, the f-I conversion circuit 22 has a 90-degree phase difference in the oscillation signal of the VCO 11 despite the deviation from the predetermined frequency. Therefore, the control current Io does not change, and the state adjusted at the time of no input signal, that is, the free state is free. Maintain the adjustment state of the run frequency.

Accordingly, even when the PLL circuit 100 is locked at a frequency offset from a predetermined frequency, the adjustment circuit 200 and the PLL circuit 100 are simultaneously operated to prevent a breakdown.

In a state where the adjustment of the free-run frequency of the VCO 11 is not completed, the adjustment can be reliably performed even if the PLL circuit 100 locks to the synchronization signal. Hereinafter, this will be described.

It is assumed that a synchronization signal higher than the predetermined frequency arrives at a stage where the free-run frequency is still lower than the predetermined frequency, for example. Control current △ i output from loop filter 15 is larger than the current generated when adjustment was originally completed. The frequency characteristic of the f-I conversion circuit 22 to which this is input is shifted to a higher frequency than the oscillation frequency of the VCO 11, and the convergence point and the actual VCO
11 occurs, the f-I conversion circuit 22 can detect the phase difference, and the VCO 1
1 is controlled so as to increase the oscillation frequency. Since the f-I conversion circuit 22 adjusts with the reference signal as an absolute value,
Even when the free-run frequency of the VCO 11 does not match the f-I conversion frequency, the two move equally on the frequency axis by the locked control current. Therefore,
The frequency difference can be detected even after locking, that is, after translation.

In terms of the PLL loop configuration, V
The first PLL circuit including CO11 performs P
The LL circuit 100, wherein the f-I conversion circuit 22
A loop that returns to the VCO 11 via the O control circuit 23 constitutes a second PLL circuit and functions as an automatic frequency control (AFC) for the VCO 11. From the f-I conversion circuit 22 to f-I
A loop returning to the f-I conversion circuit 22 via the control circuit 22 is a third PLL circuit, which operates as an automatic adjustment of the f-I conversion frequency characteristic. Therefore, a triple PLL loop configuration is provided.

In this embodiment, f
By shifting the -I conversion, that is, shifting the frequency detection reference, the free-run frequency can be indirectly adjusted without using an open loop, and the PLL circuit 100 and the adjustment circuit 200 can be operated simultaneously. That is,
Even in the state where the video signal is locked to the horizontal synchronizing signal, it is not necessary to release the lock during the vertical flyback period to set the free-run frequency, and it is possible to prevent bending (pulling) at the top of the screen.

In the description of FIG. 1, the frequency of the oscillation signal of the VCO 11 has been described as being controlled by a current, but may be controlled by a voltage. Further, the f-I conversion circuit 22 for converting a frequency to a current may be an f-V conversion circuit for converting to a voltage, and the f-I control circuit 24 may be an f-V control circuit for controlling a voltage. There may be. Further, the CCO control circuit 23 that controls the oscillation frequency of the VCO 11 by current may be a VCO control circuit that controls the oscillation frequency by voltage.

The present invention is conceivable in various modifications and uses, which will be described below. In the control of each circuit by the pulse P1, the period in which the switch SW1 is tilted to the reference signal side is a period necessary for refreshing the adjustment of the f-I conversion circuit 22, and the period in which the capacitor C2 due to the leakage of the bipolar element or the like. If a potential change is expected, it is necessary to switch cyclically. As described above, once the adjustment has converged, the control current Io and the voltage of the capacitor C1 maintain the same state. That is,
Since it is only refreshed, there is no problem even if the cycle of the pulse P1 is irrelevant to the operation of the PLL circuit 100.

Further, the timing generation circuit 31 shown in FIG. 1 is adapted to operate the countdown circuit 12 if an appropriate timing signal is obtained at the output of the countdown circuit 12, for example.
It is also possible to supply the pulse P1 so that it becomes H during an appropriate period, and omit the timing signal generator 31.

In the case of a TV receiver having a horizontal synchronization circuit,
There is a crystal oscillation circuit in the chrominance subcarrier reproducing circuit for receiving the chrominance signal, and if a chrominance subcarrier frequency reference signal is obtained from this circuit, there is no need to prepare a separate reference signal generator. When the present invention is applied to processing of an IF signal of a video signal, the present invention can perform high-speed adjustment refresh even during the AFT pull-in, that is, even when the input IF frequency has not yet reached a predetermined value. Therefore, it is not necessary to increase the holding time constant of the adjustment circuit 200 to the order of several KHz,
For example, at about 100 KHz, it is possible to sufficiently incorporate the IC.

In FIG. 1, the fI conversion circuit 22 has been described as a phase shift circuit using an active filter. V
If the same shift amount cannot be obtained with the same control current △ i for CO and f-I conversion, an amplifier 25b (or an attenuation circuit) is provided in the convergence point shift circuit 25 as shown in FIG. And the f-I conversion can have the same frequency control sensitivity.

As a special case, when frequency detection is performed digitally, the f-I
Adjustment via the -I control circuit 24 may not be necessary. For example, when a window is created by dividing the reference signal, and the frequency is detected based on the number of cycles of the oscillation signal of the VCO 11 included in the window, the window signal is already an absolute reference for fI conversion, A cycle to adjust this is no longer needed. Therefore, the means for converging the frequency characteristic of the fI conversion is not a necessary condition, and an active filter or a V
It is required when CO is used for fI conversion.

Further, in the above description, it is assumed that the reference signal frequency of the reference signal generator 21 and the frequency of the oscillation signal of the VCO 11 are the same. However, in practice, only a different frequency can be obtained. Will be described as a modification of FIG. 1 together with the block diagram of FIG.

In this case, after the f-I conversion is adjusted with the reference signal, when the oscillation frequency of the VCO 11 is detected, f
What is necessary is just to shift the -I conversion characteristic. f-I conversion circuit 22
Itself or the fI conversion circuit 22 and the convergence point shift circuit 2
5, an amplification (attenuation) circuit 41 is provided. The pulse P1 is used as a control signal for the amplifier circuit 41.

For example, when the oscillation frequency of the VCO 11 is 500
KHz from the reference signal generator 21 to 700 KHz
Is obtained, the input / output ratio of the switching means is set to 1 while the pulse P1 for operating the fI control circuit 24 is at the H level, and the fI conversion characteristic is converged at 700 KHz. When the pulse P1 becomes L level and inputs the VCO oscillation signal to the f-I conversion circuit 22, the input / output ratio of the switching means is set to 5/7 and the f-I conversion characteristic is shifted to 500 KHz.

If such a method is used, the reference signal and the VC
Even when the O oscillation frequency is different, the effects of the invention can be sufficiently exhibited. In this case, the amplification (attenuation) circuit 41
Instead, the same applies to the case where a means for switching input / output characteristics based on a certain set ratio, such as a DA conversion circuit, is provided.

Further, the PLL circuit 100 shown in FIG. 1 has a countdown circuit 12 because a horizontal synchronization circuit is taken as an example. However, the countdown circuit may be deleted for general use. Changes such as taking the signal input to the circuit 200 not from the output of the VCO 11 but from the countdown circuit 12 do not impair the gist of the present invention.

As described above, in the PLL circuit of the present invention, P
The LL circuit 100 and the adjustment circuit 200 can operate at the same time, and the operation of the adjustment circuit 200 is only temporarily stopped in order to refresh the adjustment state of the fV conversion characteristics of the adjustment circuit 200 itself. Need not stop. Accordingly, the present invention can be applied to, for example, a PLL circuit for audio processing, which cannot have an adjustment circuit 200 for performing free-run adjustment in an open loop in the past. Taking a TV receiver as an example, since the audio signal is FM-modulated at 4.5 MHz, a PLL circuit for demodulating the FM signal is required on the receiver side. This PLL
By using the circuit of the present invention for the circuit, it is possible to integrate the storage capacitor into the IC as described in the example of the IF.

[0041]

As described above, in the circuit of the present invention, it is possible to adjust the frequency of the free-run or no-signal state of the PLL circuit without making the PLL circuit an open loop, and to simultaneously adjust the adjustment circuit and the PLL circuit. Since it can operate, it can be applied to general use.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining an embodiment of the present invention;

FIG. 2 is a timing chart used to explain the operation of FIG. 1;

FIG. 3 is a block diagram for explaining a modified example of the present invention.

FIG. 4 is a block diagram for explaining another modified example of the present invention.

[Explanation of symbols]

100 PLL circuit, 11 VCO, 12 countdown circuit, 13 input terminal, 14 phase comparison circuit, 15
... Loop filter, 200 ... Adjustment circuit, 21 ... Reference signal generator, 22 ... FI converter circuit, 23 ... CCO control circuit, 24 ... FI control circuit, 25 ... Convergence point shift circuit,
SW1, SW2: switch, 31: timing signal generator.

Claims (11)

[Claims] 1. A first PL that locks to an oscillation signal of a VCO whose oscillation frequency is controlled by a current or a voltage.
An L circuit, a second PLL circuit that detects an oscillation frequency of the VCO based on a reference frequency and controls the oscillation frequency of the VCO, and a control information that controls the oscillation frequency of the VCO, A PLL circuit, comprising: a shift unit that supplies the reference frequency and shifts the reference frequency; and a timing signal generator that controls operation timing of the second PLL circuit and the shift unit. 2. The second PLL circuit according to claim 1, wherein the input signal converts f-I (or f-I) to convert a frequency into a current (or a voltage).
-V) conversion means, first switching means for selectively supplying an oscillation signal of the VCO to the fI (or fV) conversion means, and wherein the first switching means comprises an oscillation signal of the VCO. A shift means for inputting control information for controlling the oscillation frequency of the VCO to shift the convergence point,
And fI (or fV) control means for controlling and holding the oscillation frequency of the VCO in accordance with the output of the fI (or fV) conversion means. , The second
2. The PLL circuit according to claim 1, wherein an operation state of said PLL circuit is controlled. 3. A third circuit for inputting the reference signal to the second PLL circuit and adjusting a deviation from a frequency of the reference signal.
The PLL circuit according to claim 1, wherein a convergence point of the third PLL circuit is shifted by the shift unit.
circuit. 4. The oscillation frequency of the VCO is selected from the reference signal and the oscillation signal of the VCO by a control signal from the timing generator, and the f-I is selected by the reference signal.
3. The PLL circuit according to claim 2, wherein the frequency characteristic of the conversion means is shifted to a predetermined characteristic and adjusted by converging. 5. A shift amount of a convergence point of the shift means is:
3. The PLL circuit according to claim 1, wherein the control amount of the oscillation frequency of the VCO is substantially equal to the control amount. 6. The shift means comprises an adder and a second switching means, adds information from the fI control means and control information of the VCO through the second switching means, and outputs an output. 3. The PLL circuit according to claim 2, wherein said PLL circuit is supplied to said fI conversion means. 7. The PLL circuit according to claim 6, wherein amplification (or attenuation) means is provided between the control information of the oscillation frequency of the VCO and the second switching means. 8. The amplifier according to claim 6, wherein an amplification (or attenuation) circuit is connected between the fI control means and the adder, and an amplification (or attenuation) ratio is controlled by a timing signal. PLL circuit. 9. The PLL circuit according to claim 1, wherein a signal obtained from a countdown circuit of the oscillation signal of the VCO is used as a timing signal instead of the timing signal generated by the timing signal generator. 10. The input signal of the first PLL circuit is a synchronizing signal constituting a composite video signal, and the reference signal is a crystal oscillation signal of a chrominance subcarrier reproducing circuit or a frequency-divided signal thereof. The PLL circuit according to claim 3, wherein: 11. An input signal of the first PLL circuit is a video IF signal, and is output from the fI conversion means to the VCO.
5. A P-type storage device according to claim 4, wherein a holding capacity of a means for controlling and holding the oscillation frequency of the F1 and a holding capacity of a means for controlling and holding a convergence point of the fI conversion means are incorporated.
LL circuit.