JPH05299528A - Integrated circuit device - Google Patents

Integrated circuit device

Info

Publication number
JPH05299528A
JPH05299528A JP12259392A JP12259392A JPH05299528A JP H05299528 A JPH05299528 A JP H05299528A JP 12259392 A JP12259392 A JP 12259392A JP 12259392 A JP12259392 A JP 12259392A JP H05299528 A JPH05299528 A JP H05299528A
Authority
JP
Japan
Prior art keywords
substrate
sealing resin
integrated circuit
circuit device
metal substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12259392A
Other languages
Japanese (ja)
Inventor
Hajime Kato
肇 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP12259392A priority Critical patent/JPH05299528A/en
Publication of JPH05299528A publication Critical patent/JPH05299528A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To manufacture the title integrated circuit device having excellent temperature cycle as well as the hardly releasable bonding surface between a substrate and a sealing resin not affecting any electronic elements on the substrate surface even if the bonding surface is releaed from the surface. CONSTITUTION:Within the title integrated circuit device provided with a substrate 1 having at least semiconductor chips 3 on the surface side 1a as well as a sealing resin 6 covering the whole body in the exposed state of the rear surface 1d of the substrate 1, the sides 1b, 1c of the substrate 1 are cut off for providing stepped parts 11, 11 so as to be filled up with a part of the sealing resin 6.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、金属又はセラミック
基板を用いた集積回路装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device using a metal or ceramic substrate.

【0002】[0002]

【従来の技術】金属又はセラミック基板上に半導体チッ
プと抵抗及びコンデンサ等を混載し、樹脂で固めるよう
にした樹脂封止型混成集積回路装置が知られている。こ
のような混載集積回路装置は基板上に載せる抵抗やコン
デンサ等の受動素子の組み合わせを基板上で自由に設計
することにより、ニーズに応じた集積回路が得られる。
これは、例えば、自動車プラグの点火制御用等に用いら
れる。
2. Description of the Related Art A resin-sealed hybrid integrated circuit device is known in which a semiconductor chip, a resistor, a capacitor, and the like are mixedly mounted on a metal or ceramic substrate and hardened with a resin. In such a mixed integrated circuit device, by freely designing a combination of passive elements such as resistors and capacitors to be mounted on the substrate on the substrate, an integrated circuit according to needs can be obtained.
This is used, for example, for ignition control of an automobile plug.

【0003】図4及び図5は従来の樹脂封止型混成集積
回路の一例を示す断面図である。各図において、1は金
属基板、1aは金属基板1の表面、1b,1cは金属基
板1の側面、1dは金属基板1の裏面、2はこの金属基
板1の表面1a上の銅泊パターン、3は銅泊パターン2
に搭載された半導体チップ、4は銅泊パターン2と半導
体チップ3とを結ぶ導電性の金属細線、5は外部リー
ド、6は封止樹脂である。
4 and 5 are sectional views showing an example of a conventional resin-sealed hybrid integrated circuit. In each figure, 1 is a metal substrate, 1a is the front surface of the metal substrate 1, 1b and 1c are side surfaces of the metal substrate 1, 1d is the back surface of the metal substrate 1, 2 is a copper foil pattern on the front surface 1a of the metal substrate 1, 3 is copper night pattern 2
A semiconductor chip mounted on the substrate 4, conductive thin metal wires that connect the copper foil pattern 2 and the semiconductor chip 3, 5 are external leads, and 6 is a sealing resin.

【0004】従来の樹脂封止型混成集積回路装置は上記
のように構成され、図4において、半導体チップ3の搭
載面である金属基板1の表面1a側と両側面1b,1c
は封止樹脂6により被われ封止されるのに対し、上記金
属基板1の裏面1dは半導体チップ3で発生する熱を放
散するために封止樹脂6より外部に露出している。
The conventional resin-encapsulated hybrid integrated circuit device is constructed as described above, and in FIG. 4, the surface 1a side and both side surfaces 1b, 1c of the metal substrate 1 on which the semiconductor chip 3 is mounted are mounted.
Is covered and sealed by the sealing resin 6, whereas the back surface 1d of the metal substrate 1 is exposed to the outside from the sealing resin 6 in order to dissipate the heat generated in the semiconductor chip 3.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、従来の
樹脂封止型混成集積回路装置によれば、長期間使用する
ことにより、熱的ストレスを受け、図5に示すように金
属基板の側面下端側の金属基板と封止樹脂との接着面に
剥がれAが生じ、ここから水分が侵入して回路を破壊す
るという欠点があった。
However, according to the conventional resin-encapsulated hybrid integrated circuit device, it is subjected to thermal stress when it is used for a long period of time, and as shown in FIG. There is a drawback that peeling A occurs on the adhesive surface between the metal substrate and the sealing resin, and moisture penetrates from there to destroy the circuit.

【0006】この発明は、かかる問題点を解決するため
になされたものであり、温度サイクル性が良く金属基板
と封止樹脂との接着面が剥がれにくく、基板表面上の電
子素子に影響を及ぼさない信頼性の高い集積回路装置を
得ることを目的としている。
The present invention has been made in order to solve the above problems, and has good temperature cycle property, and the adhesive surface between the metal substrate and the sealing resin is not easily peeled off, which affects electronic elements on the surface of the substrate. The purpose is to obtain a highly reliable integrated circuit device.

【0007】[0007]

【課題を解決するための手段】この発明に係る集積回路
装置は、少なくとも半導体チップ3及び電極を表面1a
側に有する基板1と、この基板1の裏面1dを露出させ
た状態で全体を被う封止樹脂6とを備えた集積回路装置
において、上記基板1の側面1b,1c下端を切除して
段差部11,11を設け、この段差部11,11を上記
封止樹脂6で埋めるようにしたものである。
An integrated circuit device according to the present invention has at least a semiconductor chip 3 and electrodes on a surface 1a.
In the integrated circuit device provided with the substrate 1 provided on the side and the sealing resin 6 covering the entire back surface 1d of the substrate 1, the side surfaces 1b and 1c of the substrate 1 are cut off to form a step. The parts 11, 11 are provided, and the step parts 11, 11 are filled with the sealing resin 6.

【0008】[0008]

【作用】上記のように構成したので、封止樹脂により封
止する際、封止樹脂が基板に設けられた段差部を埋める
ように封止するので、基板と封止樹脂との一体性が増
し、剥がれが生じにくくなる。
With the above structure, when the sealing resin is used for sealing, the sealing resin seals so as to fill the stepped portion provided on the substrate, so that the integrity of the substrate and the sealing resin is improved. And peeling is less likely to occur.

【0009】[0009]

【実施例】実施例1.以下、本発明の一実施例を図1に
基づいて説明する。図1は、本発明の一実施例を示す断
面図であり、図4及至図5の従来例と同一又は相当する
部分には同一符号を付し説明を省略する。図1におい
て、11は、金属基板1の下端を外周側から内周側へ向
って切除した段差部である。6aは、上記段差部11,
11を埋めた封止樹脂である。本実施例によれば、上記
段差部11,11を形成することによって、上記金属基
板1を封止樹脂6により封止する場合、上記封止樹脂6
の一部が段差部11,11を埋める。これにより上記金
属基板1の裏面1dの中央部のみが封止樹脂6の外部に
露出するように封止する。従って、金属基板1の裏面1
dの露出度が減少し、それに伴って金属基板1と封止樹
脂6との接着面が増加し、上記段差部11,11に封止
樹脂6が回り込むように埋めているので、金属基板1と
封止樹脂6とが密着して、一体性が増し、剥がれにくく
なる。また、万一、剥がれが生じたとしても、上記段差
部11,11が形成されているので、側面1b,1cを
沿って基板表面1aまで剥がれが到達することはなく、
基板表面1aの電子素子に影響を及ぼすことはない。
EXAMPLES Example 1. An embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a cross-sectional view showing an embodiment of the present invention. The same or corresponding parts as those of the conventional example shown in FIGS. In FIG. 1, reference numeral 11 denotes a stepped portion obtained by cutting the lower end of the metal substrate 1 from the outer peripheral side toward the inner peripheral side. 6a is the stepped portion 11,
11 is a sealing resin. According to this embodiment, when the metal substrate 1 is sealed with the sealing resin 6 by forming the step portions 11 and 11, the sealing resin 6 is used.
Partially fill the stepped portions 11, 11. As a result, the metal substrate 1 is sealed so that only the central portion of the back surface 1d is exposed to the outside of the sealing resin 6. Therefore, the back surface 1 of the metal substrate 1
Since the degree of exposure of d is reduced and the bonding surface between the metal substrate 1 and the sealing resin 6 is increased accordingly, the sealing resin 6 is embedded so as to wrap around the step portions 11 and 11. The sealing resin 6 and the sealing resin 6 are in close contact with each other, the integrity is increased, and peeling is less likely to occur. Further, even if peeling occurs, since the step portions 11 and 11 are formed, the peeling does not reach the substrate surface 1a along the side surfaces 1b and 1c.
It does not affect the electronic elements on the substrate surface 1a.

【0010】実施例2.図2は、本発明の他の実施例を
示す断面図であり、図1,図4,図5と同一又は相当す
る部分には同一符号を付し説明を省略する。図2におい
て、12は、基板表面1aより段差部11,11まで延
長するように形成された貫通穴である。6bは、上記貫
通穴12,12を埋めた封止樹脂6である。本実施例に
よれば、金属基板1を封止樹脂6により封止する場合、
上記段差部11,11とともに上記貫通穴12,12も
埋めるように基板全体を封止樹脂で被い、上記金属基板
1の裏面1dの中央部のみを封止樹脂6の外部に露出す
るように封止する。従って、実施例1に示すものより、
更に密着度が増し、金属基板1と封止樹脂6がより剥が
れにくくなる。また、万一、剥がれが生じても、段差部
11,11が形成されているとともに貫通穴12,12
も形成されているので、剥がれが基板側面1b,1cを
伝って基板表面1aにまで剥がれが到達することがな
く、基板表面1aの電子素子に影響を及ぼすことがな
い。
Embodiment 2. FIG. 2 is a cross-sectional view showing another embodiment of the present invention, in which the same or corresponding parts as those in FIGS. 1, 4 and 5 are designated by the same reference numerals and the description thereof will be omitted. In FIG. 2, reference numeral 12 is a through hole formed so as to extend from the substrate surface 1a to the step portions 11, 11. 6b is a sealing resin 6 filling the through holes 12, 12. According to the present embodiment, when the metal substrate 1 is sealed with the sealing resin 6,
The whole substrate is covered with a sealing resin so as to fill the through holes 12, 12 together with the step portions 11, 11, so that only the central portion of the back surface 1d of the metal substrate 1 is exposed to the outside of the sealing resin 6. Seal. Therefore, rather than the one shown in Example 1,
Further, the degree of adhesion increases, and it becomes more difficult for the metal substrate 1 and the sealing resin 6 to come off. Even if peeling occurs, the step portions 11 and 11 are formed and the through holes 12 and 12 are formed.
Also, since the peeling does not reach the substrate surface 1a through the substrate side surfaces 1b and 1c, the peeling does not affect the electronic elements on the substrate surface 1a.

【0011】実施例3.図3は、本発明の他の実施例を
示す断面図であり、図1,図2,図4,図5と同一又は
相当する部分は同一符号を付し説明を省略する。図3に
おいて、13は、金属基板1の側面1b,1cに、内側
に向かって形成された溝である。6cは、上記溝13,
13を埋めた封止樹脂である。本実施例によれば、金属
基板1を封止樹脂6により封止する場合、上記段差部1
1,11とともに上記溝13,13も埋めるように基板
全体を封止樹脂6で被い、金属基板1の裏面1dの中央
部のみを封止樹脂6の外部に露出させて封止した。従っ
て、上記段差部11,11と上記溝13,13とを封止
樹脂6が埋めるように封止しているので、金属基板1と
封止樹脂6との密着度が増し、剥がれにくくなる。ま
た、万一、剥がれが生じても、基板側面1b,1cに沿
って基板表面1aにまで到達することはなく、基板表面
1aの電子素子に影響を及ぼすことがない。この構成で
は、加工上の問題はあるが、一定の効果が得られる。
Embodiment 3. FIG. 3 is a cross-sectional view showing another embodiment of the present invention, in which the same or corresponding parts as those in FIGS. 1, 2, 4, and 5 are designated by the same reference numerals and the description thereof will be omitted. In FIG. 3, 13 is a groove formed inwardly on the side surfaces 1b and 1c of the metal substrate 1. 6c is the groove 13,
13 is a sealing resin. According to this embodiment, when the metal substrate 1 is sealed with the sealing resin 6, the step portion 1
The entire substrate was covered with the sealing resin 6 so as to fill the grooves 13 and 13 as well as 1 and 11, and only the central portion of the back surface 1d of the metal substrate 1 was exposed to the outside of the sealing resin 6 for sealing. Therefore, since the step portions 11 and 11 and the grooves 13 and 13 are sealed so as to be filled with the sealing resin 6, the degree of adhesion between the metal substrate 1 and the sealing resin 6 is increased, and peeling is less likely to occur. Further, even if peeling occurs, it does not reach the substrate surface 1a along the substrate side surfaces 1b and 1c, and does not affect the electronic elements on the substrate surface 1a. With this configuration, there is a problem in processing, but a certain effect can be obtained.

【0012】[0012]

【発明の効果】本発明によれば、基板の側面の下端を切
除して段差部を設け、この段差部を封止樹脂で埋めるよ
うにしたので、基板と封止樹脂との密着性が向上し、接
着性が高い、また、耐熱性においても信頼性の高いもの
が得られる。
According to the present invention, the lower end of the side surface of the substrate is cut off to form a stepped portion, and the stepped portion is filled with the sealing resin, so that the adhesion between the substrate and the sealing resin is improved. However, it is possible to obtain a product having high adhesiveness and high heat resistance.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の集積回路装置の一実施例を示す断面図
である。
FIG. 1 is a sectional view showing an embodiment of an integrated circuit device of the present invention.

【図2】本発明の集積回路装置の他の実施例を示す断面
図である。
FIG. 2 is a sectional view showing another embodiment of the integrated circuit device of the present invention.

【図3】本発明の集積回路装置の他の実施例を示す断面
図である。
FIG. 3 is a cross-sectional view showing another embodiment of the integrated circuit device of the present invention.

【図4】従来の集積回路装置一例を示す断面図である。FIG. 4 is a sectional view showing an example of a conventional integrated circuit device.

【図5】従来の集積回路装置に剥がれが生じた状態を示
す断面図である。
FIG. 5 is a cross-sectional view showing a state in which peeling has occurred in a conventional integrated circuit device.

【符号の説明】[Explanation of symbols]

1 金属基板 1a 金属基板の表面 1b,1c 金属基板の側面 1d 金属基板の裏面 2 銅泊パターン 3 半導体チップ 4 金属細線 5 外部リード 6 封止樹脂 6a 段差部を埋めた封止樹脂 6b 貫通穴を埋めた封止樹脂 6c 溝を埋めた封止樹脂 11 段差部 12 貫通穴 13 溝 1 Metal Substrate 1a Surface of Metal Substrate 1b, 1c Side of Metal Substrate 1d Back of Metal Substrate 2 Copper Side Pattern 3 Semiconductor Chip 4 Metallic Wire 5 External Lead 6 Encapsulation Resin 6a Encapsulation Resin 6b Through Hole Filled sealing resin 6c Sealing resin filling groove 11 Step 12 Through hole 13 Groove

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 少なくとも半導体チップ及び電極を表面
側に有する基板と、この基板の裏面を露出させた状態で
全体を被う封止樹脂とを備えた集積回路装置において、
上記基板の側面下端を切除して段差部を設け、この段差
部を上記封止樹脂で埋めるようにしたことを特徴とする
集積回路装置。
1. An integrated circuit device comprising: a substrate having at least a semiconductor chip and electrodes on the front surface side; and a sealing resin covering the entire surface of the substrate with the back surface thereof exposed.
An integrated circuit device characterized in that a step portion is provided by cutting off a lower end of a side surface of the substrate, and the step portion is filled with the sealing resin.
JP12259392A 1992-04-16 1992-04-16 Integrated circuit device Pending JPH05299528A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12259392A JPH05299528A (en) 1992-04-16 1992-04-16 Integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12259392A JPH05299528A (en) 1992-04-16 1992-04-16 Integrated circuit device

Publications (1)

Publication Number Publication Date
JPH05299528A true JPH05299528A (en) 1993-11-12

Family

ID=14839775

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12259392A Pending JPH05299528A (en) 1992-04-16 1992-04-16 Integrated circuit device

Country Status (1)

Country Link
JP (1) JPH05299528A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012231115A (en) * 2010-10-22 2012-11-22 Panasonic Corp Surface-mounting type light-emitting device, and dry-type unsaturated polyester resin composition, granular material, pellet and crashed processed product used for manufacture thereof
WO2013124988A1 (en) * 2012-02-22 2013-08-29 三菱電機株式会社 Semiconductor device and method of manufacturing semiconductor device
JP2014199960A (en) * 2005-03-11 2014-10-23 ソウル セミコンダクター カンパニー リミテッド Light emitting element having plural light emitting cells
WO2016139890A1 (en) * 2015-03-02 2016-09-09 株式会社デンソー Electronic device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014199960A (en) * 2005-03-11 2014-10-23 ソウル セミコンダクター カンパニー リミテッド Light emitting element having plural light emitting cells
JP2012231115A (en) * 2010-10-22 2012-11-22 Panasonic Corp Surface-mounting type light-emitting device, and dry-type unsaturated polyester resin composition, granular material, pellet and crashed processed product used for manufacture thereof
JP2015233145A (en) * 2010-10-22 2015-12-24 パナソニックIpマネジメント株式会社 Surface mounting type light-emission device and manufacturing method for the same
WO2013124988A1 (en) * 2012-02-22 2013-08-29 三菱電機株式会社 Semiconductor device and method of manufacturing semiconductor device
CN104137252A (en) * 2012-02-22 2014-11-05 三菱电机株式会社 Semiconductor device and method of manufacturing semiconductor device
JPWO2013124988A1 (en) * 2012-02-22 2015-05-21 三菱電機株式会社 Semiconductor device and manufacturing method of semiconductor device
US9466548B2 (en) 2012-02-22 2016-10-11 Mitsubishi Electric Corporation Semiconductor device and method of manufacturing semiconductor device
WO2016139890A1 (en) * 2015-03-02 2016-09-09 株式会社デンソー Electronic device
CN107004646A (en) * 2015-03-02 2017-08-01 株式会社电装 Electronic installation

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