JPH0529509A - Board for semiconductor - Google Patents

Board for semiconductor

Info

Publication number
JPH0529509A
JPH0529509A JP3182614A JP18261491A JPH0529509A JP H0529509 A JPH0529509 A JP H0529509A JP 3182614 A JP3182614 A JP 3182614A JP 18261491 A JP18261491 A JP 18261491A JP H0529509 A JPH0529509 A JP H0529509A
Authority
JP
Japan
Prior art keywords
heat dissipation
multilayer substrate
thermal expansion
semiconductor
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3182614A
Other languages
Japanese (ja)
Inventor
Norimi Kikuchi
紀實 菊池
Hiroyuki Kawamura
裕之 川村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronics Engineering Corp
Original Assignee
Toshiba Corp
Toshiba Material Engineering Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Material Engineering Co Ltd filed Critical Toshiba Corp
Priority to JP3182614A priority Critical patent/JPH0529509A/en
Publication of JPH0529509A publication Critical patent/JPH0529509A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To obtain a board for semiconductor of high reliability wherein heat dissipation plates excellent in thermal conductivity are provided and generation of cracks and warps is little. CONSTITUTION:In a board for semiconductor provided with a multilayered board 1 formed of aluminum nitride sintered body, and heat dissipation plates 2a, 2b transmitting the heat generated from a semiconductor element 4 arranged on the multilayered board 1, the heat dissipation plates 2a, 2b are bonded to the multilayered board 1 to be in a unified body, via stress buffering material 3 having a thermal expansion coefficient being intermediate between the heat dissipation plates 2a, 2b and the multilayered board 1. The heat dissipation plates 2a, 2b are made of copper, and the thermal expansion coefficient of the stress buffering material 3 is preferably set to be 7X10<-6>-11X10<-6>/ deg.C.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は電子機器等を構成する半
導体用基板に係り、特に放熱板を有しているため放熱特
性が優れ、また放熱板との熱膨脹差に起因する基板の割
れや剥離を防止できる信頼性が高い半導体用基板に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate which constitutes an electronic device or the like, and in particular, it has a heat dissipation plate, so that it has excellent heat dissipation characteristics. The present invention relates to a highly reliable semiconductor substrate capable of preventing peeling.

【0002】[0002]

【従来の技術】従来一般的に使用されている半導体用基
板は、絶縁材としてのアルミナ(Al2 3 )グリーン
シート上に所望の回路パターン等を印刷したものを複数
枚積層して一体化し、さらに焼成した多層基板と、その
多層基板に配置された半導体ICチップから発生した熱
をヒートシンク等の冷却部に迅速に伝達するための放熱
板とを備えて構成される。放熱板としてはタングステン
(W)中に10〜20%程度のCu(銅)を合金化した
Cu/W合金が使用されており、このCu/W合金の熱
膨脹係数は、ほぼアルミナ(Al2 3 )と等しく設定
されている。従って、多層基板にCu/W合金製の放熱
板をろう付け等によって一体に接合する場合や電子機器
の運転時において半導体チップが発熱した場合において
も、多層基板に熱応力による割れや剥離を生じることも
少ない。
2. Description of the Related Art Conventionally generally used semiconductor substrates are formed by laminating a plurality of sheets of alumina (Al 2 O 3 ) green sheet as an insulating material on which desired circuit patterns and the like are printed. It further comprises a fired multilayer substrate and a heat radiating plate for rapidly transmitting heat generated from the semiconductor IC chips arranged on the multilayer substrate to a cooling unit such as a heat sink. As the heat dissipation plate, a Cu / W alloy obtained by alloying 10% to 20% Cu (copper) in tungsten (W) is used, and the thermal expansion coefficient of this Cu / W alloy is almost equal to that of alumina (Al 2 O 3 ) is set equal to. Therefore, even when a Cu / W alloy heat dissipation plate is integrally joined to the multilayer substrate by brazing or when the semiconductor chip generates heat during the operation of the electronic device, the multilayer substrate is cracked or peeled due to thermal stress. There are few things.

【0003】ところで、近年半導体を使用した電子機器
および電力機器の高速化、小型化、高集積高性能化がよ
り希求され、例えば動作速度が50〜100ns程度の
高速用(ECL)セラミックス多層基板が主流となりつ
つあり、さらに、消費電力が高く発熱量が大きなバイポ
ーラデバイスなどに使用される半導体用基板において
は、半導体チップからの発熱をより効率的に系外に排出
できる熱設計が求められている。
By the way, in recent years, there has been a strong demand for higher speed, smaller size, and higher integration and performance of electronic devices and power devices using semiconductors. For example, a high speed (ECL) ceramic multilayer substrate having an operating speed of about 50 to 100 ns has been developed. For semiconductor substrates that are becoming mainstream and are used in bipolar devices that consume a large amount of power and generate a large amount of heat, there is a demand for a thermal design that allows the heat generated from the semiconductor chips to be more efficiently discharged to the outside of the system. .

【0004】[0004]

【発明が解決しようとする課題】しかしながら、従来の
多層基板用セラミックス材料として一般に使用されてい
るアルミナ(Al2 3 )は、電気的特性および機械的
特性には優れているものの、熱伝導率(K)が17W/
m・k程度と低い難点があり、高速で消費電力が大きく
発熱量が大きいデバイスには不向きであった。そこでア
ルミナと比較して熱伝導率が極めて高く、放熱性に優れ
たベリリア(BeO)や窒化アルミニウム(AlN)を
使用する場合もある。
However, although alumina (Al 2 O 3 ) generally used as a conventional ceramic material for multilayer substrates has excellent electrical and mechanical properties, it has a high thermal conductivity. (K) is 17W /
Since it has a low difficulty of about m · k, it is not suitable for a device that consumes a large amount of heat and has a high power consumption at a high speed. Therefore, there is a case where beryllia (BeO) or aluminum nitride (AlN), which has an extremely high thermal conductivity as compared with alumina and is excellent in heat dissipation, is used.

【0005】ところがベリリアは、原料調製工程におい
て有毒ガスが発生するため、問題があり、この代替材料
としてBeOとほぼ同等の熱伝導率を有し、特に熱伝導
性に優れた窒化アルミニウム焼結体が注目されている。
However, beryllia has a problem because it emits a toxic gas in the raw material preparation process, and as an alternative material, it has a thermal conductivity almost equal to that of BeO, and an aluminum nitride sintered body having a particularly excellent thermal conductivity. Is attracting attention.

【0006】しかしながら、この窒化アルミニウム焼結
体に従来からのCu/W合金で形成した放熱板をろう接
合しようとすると、窒化アルミニウム製多層基板にクラ
ックが生じたり、放熱板が大きく反ってしまう傾向があ
る。すなわち従来のCu/W合金製放熱板は、アルミナ
の熱膨脹率に等しく設定されており、窒化アルミニウム
製多層基板に接合された場合には、両部材の熱膨脹率が
大きく異なるため、部材相互間に、熱応力を生じクラッ
クや反りを生じてしまうのである。
However, when a conventional heat dissipation plate made of a Cu / W alloy is brazed to this aluminum nitride sintered body, the aluminum nitride multilayer substrate tends to crack or the heat dissipation plate is largely warped. There is. That is, the conventional Cu / W alloy heat dissipation plate is set to have the same thermal expansion coefficient as that of alumina, and when bonded to an aluminum nitride multilayer substrate, the thermal expansion coefficients of both members are greatly different. However, thermal stress is generated, which causes cracks and warpage.

【0007】熱膨脹差を緩和するために、Cuの含有量
を8%程度以下にした場合には、割れを発生することな
く接合は可能となるが、熱伝導性が急激に低下してしま
う問題点がある。
When the content of Cu is set to about 8% or less in order to reduce the difference in thermal expansion, bonding can be performed without cracking, but the thermal conductivity is sharply reduced. There is a point.

【0008】本発明は上記問題点を解決するためになさ
れたものであり、熱伝導性に優れた放熱板を備え、クラ
ックや反りの発生が少なく信頼性が高い半導体用基板を
提供することを目的とする。
The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a highly reliable semiconductor substrate provided with a heat dissipation plate having excellent thermal conductivity and having few cracks and warps. To aim.

【0009】[0009]

【課題を解決するための手段】上記目的を達成するた
め、本発明は窒化アルミニウム焼結体で形成した多層基
板と、この多層基板に配置した半導体素子から発生した
熱を伝達する放熱板とを備えた半導体用基板において、
上記放熱板と多層基板との中間の熱膨脹係数を有する応
力緩衝材を介して上記放熱板を多層基板に一体に接合し
たことを特徴とする。
In order to achieve the above object, the present invention provides a multilayer substrate formed of an aluminum nitride sintered body and a heat dissipation plate for transmitting heat generated from a semiconductor element arranged on the multilayer substrate. In the provided semiconductor substrate,
The heat dissipation plate is integrally joined to the multilayer substrate via a stress buffering material having a thermal expansion coefficient intermediate between the heat dissipation plate and the multilayer substrate.

【0010】また、放熱板を銅で形成する一方、応力緩
衝材の熱膨脹係数を7×10-6〜11×10-6/℃に設
定するとよい。
Further, it is preferable that the heat dissipation plate is made of copper and the thermal expansion coefficient of the stress buffer material is set to 7 × 10 −6 to 11 × 10 −6 / ° C.

【0011】本発明において、多層基板は複数の絶縁層
としての窒化アルミニウム製焼結体とメタライズ層とを
交互に積層して形成され、熱伝導率Kが170W/m・
k以上であり、室温から500℃の温度範囲における熱
膨脹係数が5〜6×10-6/℃である。この多層基板に
応力緩衝材を介して金属製の放熱板が一体に接合され
て、半導体基板が製造される。
In the present invention, the multilayer substrate is formed by alternately stacking a plurality of aluminum nitride sintered bodies as an insulating layer and a metallized layer, and has a thermal conductivity K of 170 W / m.multidot.
k or more, and the coefficient of thermal expansion in the temperature range from room temperature to 500 ° C. is 5 to 6 × 10 −6 / ° C. A metal heat dissipation plate is integrally bonded to the multilayer substrate via a stress buffering material to manufacture a semiconductor substrate.

【0012】応力緩衝材は、多層基板と放熱板との熱膨
脹量の差異によって発生する応力を緩和するために設け
られるものであり、多層基板と放熱板との中間の熱膨脹
係数を有する材料で形成される。
The stress buffering material is provided to relieve stress caused by the difference in thermal expansion amount between the multilayer substrate and the heat sink, and is made of a material having a coefficient of thermal expansion intermediate between the multilayer substrate and the heat sink. To be done.

【0013】一方、放熱板としては、熱伝導率が200
〜280W/m・Kと高く放熱性に優れた厚さ0.5〜
3mm程度の無酸素銅(OFC)板を打ち抜いて形成した
ものを使用するとよい。そして銅製の放熱板(熱膨脹係
数α1=16.7×10-6〜20×10-6/℃)と、窒
化アルミニウム製の多層基板(熱膨脹係数α3 =5×1
-6〜6×10-6/℃)とを組み合せる場合における応
力緩衝材の熱膨脹係数α2 は両者の中間値である7×1
-6〜11×10-6/℃に設定するとよい。
On the other hand, the heat dissipation plate has a thermal conductivity of 200.
~ 280 W / m · K and high heat dissipation with a thickness of 0.5 ~
It is advisable to use a product formed by punching out an oxygen-free copper (OFC) plate of about 3 mm. Then, a heat dissipation plate made of copper (coefficient of thermal expansion α 1 = 16.7 × 10 −6 to 20 × 10 −6 / ° C.) and a multilayer substrate made of aluminum nitride (coefficient of thermal expansion α 3 = 5 × 1)
0 -6 to 6 x 10 -6 / ° C), the thermal expansion coefficient α 2 of the stress buffer material is 7 x 1 which is an intermediate value between the two.
It is recommended to set it in the range of 0 -6 to 11 x 10 -6 / ° C.

【0014】応力緩衝材の具体的材料としては、例えば
鉄53%、ニッケル28%、コバルト18%を含有し、
ガラス材と熱膨脹係数を等しくしたコバール合金(熱膨
脹係数4〜5×10-6/℃)や、ニッケルを42%含有
するニッケル鋼(熱膨脹係数7.9×10-6/℃)また
はCu−W,Cu−Mo等のクラッド材を使用するとよ
い。特に心材としてのWまたはMo板の両面にそれぞれ
同一の熱膨脹係数を有するCu板を合せ材として積層し
た三層構造のクラッド材を応力緩衝材として用いること
により、温度変化による応力緩衝材自体の反りを防止す
ることができる。
As a concrete material of the stress buffer, for example, iron 53%, nickel 28%, cobalt 18% are contained,
Kovar alloy with the same coefficient of thermal expansion as glass (coefficient of thermal expansion 4-5 × 10 -6 / ° C), nickel steel containing 42% of nickel (coefficient of thermal expansion 7.9 × 10 -6 / ° C) or Cu-W , A Cu-Mo clad material may be used. In particular, by using a clad material having a three-layer structure in which a Cu plate having the same coefficient of thermal expansion is laminated on both surfaces of a W or Mo plate as a core material as a joining material as a stress buffer material, the stress buffer material itself warps due to temperature change. Can be prevented.

【0015】[0015]

【作用】上記構成に係る半導体用基板によれば、放熱板
と多層基板との中間の熱膨脹係数を有する応力緩衝材を
介して放熱板を多層基板に一体に接合しているため、温
度変化に伴う放熱板および多層基板の熱膨脹による変位
が応力緩衝材によって拘束されるとともに、多層基板に
作用する放熱板の応力を大幅に緩和することができる。
したがって、放熱板を多層基板に接合する際に、多層基
板に割れ(クラック)や反りが発生することが少なく、
高い信頼性を有する半導体基板が得られる。
According to the semiconductor substrate having the above structure, since the heat sink is integrally bonded to the multilayer substrate through the stress buffer material having a coefficient of thermal expansion that is intermediate between the heat sink and the multilayer substrate, the temperature change is prevented. The accompanying displacement of the heat sink and the multilayer substrate due to thermal expansion is restrained by the stress buffer material, and the stress of the heat sink acting on the multilayer substrate can be relieved significantly.
Therefore, when joining the heat sink to the multi-layer substrate, cracks and warpage are less likely to occur in the multi-layer substrate,
A semiconductor substrate having high reliability can be obtained.

【0016】特に高い熱伝導性を有する窒化アルミニウ
ム基板の特徴を損うことなく、かつ割れ等を発生するこ
となく、放熱特性に優れた放熱板を多層基板にろう接合
することが可能になり、より高速で発熱量が大きなバイ
ポーラ素子に対応することが可能になる。
Particularly, it becomes possible to solder-bond a heat dissipation plate having excellent heat dissipation characteristics to a multi-layer substrate without damaging the characteristics of the aluminum nitride substrate having a high thermal conductivity and without causing cracks or the like. It becomes possible to deal with a bipolar element which is faster and generates a large amount of heat.

【0017】[0017]

【実施例】次に本発明の実施例について、添付図面を参
照して説明する。図1〜2はそれぞれ本発明に係る半導
体用基板の実施例を示す断面図および平面図であり、図
3は各実施例において使用する応力緩衝材の形状例を示
す平面図である。
Embodiments of the present invention will now be described with reference to the accompanying drawings. 1 and 2 are a sectional view and a plan view, respectively, showing an embodiment of a semiconductor substrate according to the present invention, and FIG. 3 is a plan view showing an example of the shape of a stress buffer material used in each embodiment.

【0018】実施例1 図1および図2に示す実施例の半導体用基板で使用する
窒化アルミニウム製多層基板1を以下の工程で100個
製造した。
Example 1 100 aluminum nitride multilayer substrates 1 used in the semiconductor substrates of the examples shown in FIGS. 1 and 2 were manufactured in the following steps.

【0019】すなわちAIN原料粉と、常圧焼結助剤と
しての酸化イットリウム(Y2 3 )3重量%とを含有
する粉体を泥漿化し、スラリーを得た。次に得られたス
ラリーをドクターブレード法によって厚さ0.7mmのグ
リーンシート(GS)に成形後、1辺が53mmで正方形
状となるようにブランク型で多数打ち抜き、さらに配線
パターンを印刷するとともにタングステン(W)を主体
とする導体ペーストで、電極パッド、ワイヤボンディン
グパッドなどの配線部を印刷した。
That is, a powder containing AIN raw material powder and 3% by weight of yttrium oxide (Y 2 O 3 ) as a normal pressure sintering aid was slurried to obtain a slurry. Next, after molding the obtained slurry into a green sheet (GS) with a thickness of 0.7 mm by the doctor blade method, a large number of blanks are punched out so that one side is 53 mm and a square shape is formed, and further a wiring pattern is printed. Wiring parts such as electrode pads and wire bonding pads were printed with a conductive paste mainly composed of tungsten (W).

【0020】そして複数のグリーンシートを熱圧着法で
一体に積層して厚さ3mmの積層体とした後に、脱脂後、
2 ガス雰囲気で温度1800℃で6時間加熱して焼結
を行ない、1辺が42mmの正方形状で厚さが2mmの焼結
体とした。
Then, a plurality of green sheets are integrally laminated by thermocompression bonding to form a laminated body having a thickness of 3 mm, and after degreasing,
Sintering was carried out by heating in an N 2 gas atmosphere at a temperature of 1800 ° C. for 6 hours to obtain a sintered body having a square shape with a side of 42 mm and a thickness of 2 mm.

【0021】一方、厚さ3mmの無酸素銅(OFC)を打
ち抜き、1辺が23mmの正方形状の放熱板2aを調製す
るとともに、ニッケルを42%含有し、熱膨脹係数が
7.9×10-6/℃である厚さ2.5mmのNi鋼を打ち
抜いて図3に示すような幅Wが5mmで1辺が23mmの正
方枠状の応力緩衝材3を多数調製した。
On the other hand, oxygen-free copper (OFC) having a thickness of 3 mm was punched out to prepare a square heat radiating plate 2a having one side of 23 mm, containing 42% nickel and having a coefficient of thermal expansion of 7.9 × 10 −. A 2.5 mm thick Ni steel having a thickness of 6 / ° C. was punched out to prepare a large number of square frame-shaped stress buffer materials 3 having a width W of 5 mm and one side of 23 mm as shown in FIG.

【0022】ここで応力緩衝材32の幅Wは3〜5mm程
度が望ましい。幅Wが3mm未満では応力緩衝作用が不充
分である一方、幅Wが5mmを超えると、クラックや反り
が発生し易くなる。また応力緩衝材3の内外周隅部には
図3に示すようにハンチhおよび面取りcを形成すると
よい。これらのハンチhおよび面取りcにより、該部を
起点とする放射状クラックの発生を防止することができ
る。
Here, the width W of the stress buffer material 32 is preferably about 3 to 5 mm. If the width W is less than 3 mm, the stress buffering effect is insufficient, while if the width W exceeds 5 mm, cracks and warpage are likely to occur. Further, as shown in FIG. 3, a haunch h and a chamfer c may be formed at the inner and outer peripheral corners of the stress buffer material 3. The haunch h and the chamfer c can prevent the generation of radial cracks starting from the portion.

【0023】次にこの放熱板2aに直接LSI回路素子
(半導体素子)4を接合した後に、この放熱板2aおよ
び応力緩衝材3aをさらに多層基板1の中空部の周縁上
に形成した金属化層(メタライズ層)5上に銀ろう材6
を用いて接合した。接合時の温度は800〜850℃に
設定した。そして、放熱板2aの接合時に、多層基板1
に発生したクラックや反りの発生割合を測定するため
に、倍率300倍の金属顕微鏡および倍率2000倍の
走査型電子顕微鏡(SEM)で各半導体用基板を観察し
た。
Next, after the LSI circuit element (semiconductor element) 4 is directly bonded to the heat sink 2a, the heat sink 2a and the stress buffer 3a are further formed on the peripheral edge of the hollow portion of the multilayer substrate 1 to form a metallized layer. (Metalized layer) 5 Silver brazing material 6 on top
Was joined using. The temperature at the time of joining was set to 800 to 850 ° C. Then, when the heat dissipation plate 2a is joined, the multilayer substrate 1
Each semiconductor substrate was observed with a metallographic microscope with a magnification of 300 times and a scanning electron microscope (SEM) with a magnification of 2000 times in order to measure the rate of occurrence of cracks and warpage.

【0024】また各半導体基板について500サイクル
の熱衝撃試験(TCT)を実施した。試験条件は、−5
5℃、室温(RT)および150℃の3温度にそれぞれ
10分間保持する操作を1サイクルとした。また室温
(RT)から450℃に昇熱して10分間保持し、室温
(RT)に戻す1サイクル限りの熱衝撃試験を併せて実
施し、倍率2000倍のSEMにて、多層基板1の割れ
や放熱板2aの反りの発生割合を計数して表1に示す結
果を得た。
A thermal shock test (TCT) of 500 cycles was performed on each semiconductor substrate. The test condition is -5
The operation of holding each of the three temperatures of 5 ° C., room temperature (RT) and 150 ° C. for 10 minutes was set as one cycle. In addition, a thermal shock test for one cycle was performed in which the temperature was raised from room temperature (RT) to 450 ° C. and held for 10 minutes, and then returned to room temperature (RT). The rate of warpage of the heat sink 2a was counted and the results shown in Table 1 were obtained.

【0025】実施例2 実施例2として厚さ1.5mmの無酸素銅(OFC)板を
打ち抜いて放熱板2bを調製したこと、および接合時の
温度を400〜460℃に設定した以外は、実施例1と
同様な条件および工程で半導体用基板を製造した。そし
て、実施例1と同様にして接合時および各熱衝撃試験後
における割れや反りの発生割合を計測して表1に示す結
果を得た。
[0025] Except for setting Example 2 Example thickness 1.5mm oxygen-free copper as a 2 (OFC) that was prepared radiating plate 2b by punching a plate, and the temperature at the time of bonding to from 400 to 460 ° C., A semiconductor substrate was manufactured under the same conditions and processes as in Example 1. Then, in the same manner as in Example 1, the occurrence rates of cracking and warpage were measured during joining and after each thermal shock test, and the results shown in Table 1 were obtained.

【0026】比較例1〜2 比較例1〜2として、応力緩衝材3を介装せずに放熱板
2a,2bをそれぞれ多層基板1のメタライズ層5に直
接的にろう接合した以外は実施例1および実施例2と全
く同一寸法を有する半導体用基板を多数調製し、割れや
反りの発生割合を調査し、下記表1に示す結果を得た。
Comparative Examples 1-2 As Comparative Examples 1-2, Examples were carried out except that the heat dissipation plates 2a and 2b were directly brazed to the metallized layer 5 of the multilayer substrate 1 without interposing the stress buffering material 3. A large number of semiconductor substrates having exactly the same dimensions as those of Example 1 and Example 2 were prepared, and the occurrence ratio of cracks and warpage was investigated, and the results shown in Table 1 below were obtained.

【0027】[0027]

【表1】 [Table 1]

【0028】表1に示す結果から明らかなように、実施
例1〜2に係る半導体用基板では、高い熱伝導率を有す
る窒化アルミニウム基板の特徴を損うことなく、多層基
板に割れを生じたり放熱板に反り等を発生することなく
放熱板を接合することが可能になり、より発熱量が大き
な電子機器等に搭載できることが判明した。
As is clear from the results shown in Table 1, in the semiconductor substrates according to Examples 1 and 2, the multi-layer substrate was cracked without damaging the characteristics of the aluminum nitride substrate having high thermal conductivity. It has become clear that the heat sink can be joined to the heat sink without warping or the like, and the heat sink can be mounted on an electronic device or the like that generates a larger amount of heat.

【0029】一方比較例1〜2においては多層基板と放
熱板との熱膨脹差が著しいため、放熱板の接合時や熱衝
撃によって割れや反りが発生し易く、製品の歩留りおよ
び信頼性がともに低下し、実用には耐えないことが判明
した。
On the other hand, in Comparative Examples 1 and 2, since the difference in thermal expansion between the multilayer substrate and the heat sink is significant, cracks and warps are likely to occur at the time of joining the heat sinks and due to thermal shock, resulting in a decrease in both product yield and reliability. However, it turned out that it could not be put to practical use.

【0030】[0030]

【発明の効果】以上説明の通り本発明に係る半導体用基
板によれば、放熱板と多層基板との中間の熱膨脹係数を
有する応力緩衝材を介して放熱板を多層基板に一体に接
合しているため、温度変化に伴う放熱板および多層基板
の熱膨脹による変位が応力緩衝材によって拘束されると
ともに、多層基板に作用する放熱板の応力を大幅に緩和
することができる。したがって、放熱板を多層基板に接
合する際に、多層基板に割れ(クラック)や反りが発生
することが少なく、高い信頼性を有する半導体基板が得
られる。
As described above, according to the semiconductor substrate of the present invention, the heat sink is integrally bonded to the multilayer substrate through the stress buffer material having a thermal expansion coefficient intermediate between the heat sink and the multilayer substrate. Therefore, the displacement due to the thermal expansion of the heat dissipation plate and the multilayer substrate due to the temperature change is restrained by the stress buffer material, and the stress of the heat dissipation plate acting on the multilayer substrate can be relieved significantly. Therefore, when the heat dissipation plate is bonded to the multilayer substrate, the multilayer substrate is less likely to be cracked or warped, and a highly reliable semiconductor substrate can be obtained.

【0031】特に高い熱伝導性を有する窒化アルミニウ
ム基板の特徴を損うことなく、放熱特性に優れた放熱板
を多層基板にろう接合することが可能になり、より高速
で発熱量が大きなバイポーラ素子に対応することが可能
になる。
It is possible to braze a heat dissipation plate having excellent heat dissipation characteristics to a multi-layer substrate without damaging the characteristics of the aluminum nitride substrate having particularly high thermal conductivity, and thus a bipolar device which is faster and has a large heat generation amount. It becomes possible to correspond to.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る半導体用基板の一実施例を示す断
面図。
FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor substrate according to the present invention.

【図2】図1に示す半導体用基板の平面図。FIG. 2 is a plan view of the semiconductor substrate shown in FIG.

【図3】各実施例において使用する応力緩衝材の形状例
を示す平面図。
FIG. 3 is a plan view showing an example of the shape of a stress buffer material used in each example.

【符号の説明】[Explanation of symbols]

1 多層基板 2a,2b 放熱板 3 応力緩衝材 4 LSI回路素子(半導体素子) 5 金属化層(メタライズ層) 6 銀ろう材 1 Multi-layer board 2a, 2b heat sink 3 stress buffer 4 LSI circuit element (semiconductor element) 5 Metallized layer (metallized layer) 6 silver brazing material

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 窒化アルミニウム焼結体で形成した多層
基板と、この多層基板に配置した半導体素子から発生し
た熱を伝達する放熱板とを備えた半導体用基板におい
て、上記放熱板と多層基板との中間の熱膨脹係数を有す
る応力緩衝材を介して上記放熱板を多層基板に一体に接
合したことを特徴とする半導体用基板。
1. A semiconductor substrate comprising a multilayer substrate formed of an aluminum nitride sintered body and a radiator plate for transmitting heat generated from a semiconductor element arranged on the multilayer substrate, wherein the radiator plate and the multilayer substrate are included. A substrate for semiconductors, wherein the heat dissipation plate is integrally bonded to the multilayer substrate through a stress buffering material having an intermediate coefficient of thermal expansion.
【請求項2】 放熱板を銅で形成する一方、応力緩衝材
の熱膨脹係数を7×10-6〜11×10-6/℃に設定し
たことを特徴とする請求項1記載の半導体用基板。
2. The semiconductor substrate according to claim 1, wherein the heat dissipation plate is made of copper, and the thermal expansion coefficient of the stress buffer material is set to 7 × 10 −6 to 11 × 10 −6 / ° C. .
JP3182614A 1991-07-23 1991-07-23 Board for semiconductor Pending JPH0529509A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3182614A JPH0529509A (en) 1991-07-23 1991-07-23 Board for semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3182614A JPH0529509A (en) 1991-07-23 1991-07-23 Board for semiconductor

Publications (1)

Publication Number Publication Date
JPH0529509A true JPH0529509A (en) 1993-02-05

Family

ID=16121373

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3182614A Pending JPH0529509A (en) 1991-07-23 1991-07-23 Board for semiconductor

Country Status (1)

Country Link
JP (1) JPH0529509A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100764461B1 (en) * 2006-03-27 2007-10-05 삼성전기주식회사 Semiconductor Package Having a Buffer Layer
US7813135B2 (en) * 2007-05-25 2010-10-12 Kabushiki Kaisha Toyota Jidoshokki Semiconductor device
US8925437B2 (en) 2006-12-05 2015-01-06 Smith & Nephew, Inc. Cutting tool having a magnetically controlled pre-load force
US8931388B2 (en) 2006-12-05 2015-01-13 Smith & Nephew, Inc. Cutting tool having a magnetically controlled pre-load force

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100764461B1 (en) * 2006-03-27 2007-10-05 삼성전기주식회사 Semiconductor Package Having a Buffer Layer
US8925437B2 (en) 2006-12-05 2015-01-06 Smith & Nephew, Inc. Cutting tool having a magnetically controlled pre-load force
US8931388B2 (en) 2006-12-05 2015-01-13 Smith & Nephew, Inc. Cutting tool having a magnetically controlled pre-load force
US7813135B2 (en) * 2007-05-25 2010-10-12 Kabushiki Kaisha Toyota Jidoshokki Semiconductor device
EP1995775B1 (en) * 2007-05-25 2015-11-04 Kabushiki Kaisha Toyota Jidoshokki Semiconductor device with stress reducing element

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