JPH05291364A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH05291364A
JPH05291364A JP4116875A JP11687592A JPH05291364A JP H05291364 A JPH05291364 A JP H05291364A JP 4116875 A JP4116875 A JP 4116875A JP 11687592 A JP11687592 A JP 11687592A JP H05291364 A JPH05291364 A JP H05291364A
Authority
JP
Japan
Prior art keywords
wiring pad
gold wire
semiconductor device
ball portion
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4116875A
Other languages
Japanese (ja)
Inventor
Hideo Yamanaka
英雄 山中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP4116875A priority Critical patent/JPH05291364A/en
Publication of JPH05291364A publication Critical patent/JPH05291364A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4807—Shape of bonding interfaces, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H01L2224/48453—Shape of the interface with the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Abstract

PURPOSE:To provide a semiconductor device which can efficiently connect the ball part of a gold wire with a wiring pad. CONSTITUTION:In a semiconductor device 1, where the ball part 51 of a gold wire 5 is pressure-bonded to the wiring pad 4 made on the top of a semiconductor element 2, a projection, which has a projection 41 an external form in plan view larger than the diameter d of the gold wire 5 and smaller than the diameter D of the ball part 51, is provided on the topside of the pad 4 for wiring where the ball part 51 is pressure-bonded. Moreover, the rise face 42 of the projection 41 is contained in a mutual diffusion area 11. Furthermore, a shock absorbing member 43 is provided between the projection 41 and the semiconductor element 2.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、半導体素子上に設けら
れた配線用パッドに金ワイヤーのボール部が圧着された
半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a ball portion of a gold wire is pressure bonded to a wiring pad provided on a semiconductor element.

【０００２】[0002]

【従来の技術】所定の電気回路が形成された半導体素子
と外部リードとを電気的に接続するには、金ワイヤーを
用いたワイヤーボンディングが多く用いられている。こ
のため、シリコン等の半導体素子上には、この金ワイヤ
ーとの接続を得るための配線用パッドが多数形成されて
いる。2. Description of the Related Art In order to electrically connect a semiconductor element having a predetermined electric circuit and an external lead, wire bonding using a gold wire is often used. Therefore, a large number of wiring pads are formed on the semiconductor element such as silicon for obtaining the connection with the gold wire.

【０００３】図３は、従来の半導体装置を説明する断面
図で、配線用パッドの部分を拡大したものである。すな
わち、この半導体装置１は、所定の電気回路が形成され
た半導体素子２と、この半導体素子２上に形成された酸
化シリコン膜等の絶縁層３を介して設けられた配線用パ
ッド４、および配線用パッド４に接続された金ワイヤー
５とから成るものである。配線用パッド４は、アルミニ
ウム等を蒸着したもので、半導体素子２に形成された電
気回路と導通状態に設けられている。FIG. 3 is a sectional view for explaining a conventional semiconductor device, which is an enlarged view of a wiring pad portion. That is, the semiconductor device 1 includes a semiconductor element 2 in which a predetermined electric circuit is formed, a wiring pad 4 provided on the semiconductor element 2 via an insulating layer 3 such as a silicon oxide film, and the like. And a gold wire 5 connected to the wiring pad 4. The wiring pad 4 is formed by vapor-depositing aluminum or the like, and is provided in a conductive state with an electric circuit formed in the semiconductor element 2.

【０００４】この配線用パッド４に金ワイヤー５を接続
するには、金ワイヤー５の先端を溶融して形成したボー
ル部５１をこの配線用パッド４に圧着する、いわゆるネ
ールヘッドボンディングにより行う。これは、キャピラ
リ６に金ワイヤー５を通して、この金ワイヤー５の先端
に火花放電等を用いて球状のボール部５１を形成する。
そして、半導体素子２を２００℃〜３００℃に加熱する
とともに、キャピラリ６を下降させてボール部５１を配
線用パッド４上に加圧接続する。これにより、ボール部
５と配線用パッド４との間で、金−アルミニウムの金属
間相互拡散による固相溶接を行うものである。また、こ
の金属間拡散を促進させるために超音波を用いたり、加
熱と超音波の両方を併用する場合もある。The gold wire 5 is connected to the wiring pad 4 by so-called nail head bonding, in which a ball portion 51 formed by melting the tip of the gold wire 5 is pressure-bonded to the wiring pad 4. In this, the gold wire 5 is passed through the capillary 6, and a spherical ball portion 51 is formed at the tip of the gold wire 5 by using spark discharge or the like.
Then, the semiconductor element 2 is heated to 200 ° C. to 300 ° C., and the capillary 6 is lowered to press-connect the ball portion 51 onto the wiring pad 4. Thereby, solid-phase welding is performed between the ball portion 5 and the wiring pad 4 by intermetallic diffusion of gold-aluminum. In some cases, ultrasonic waves are used to accelerate the intermetallic diffusion, or both heating and ultrasonic waves are used in combination.

【０００５】このようなネールヘッドボンディングで
は、金ワイヤー５に形成されたボール部５１を上方から
キャピラリ６の先端で加圧することにより、ボール部５
１と配線用パッド４との接触面に、金ワイヤー５の直下
を除くドーナツ状の相互拡散領域１１が形成される。し
たがって、この相互拡散領域１１で金−アルミニウムの
金属間拡散が発生し、金ワイヤー５と配線用パッド４と
の接続が成されている。In such nail head bonding, the ball portion 5 formed on the gold wire 5 is pressed from above by the tip of the capillary 6 so that the ball portion 5 is formed.
A donut-shaped interdiffusion region 11 is formed on the contact surface between the wiring pad 1 and the wiring pad 4 except under the gold wire 5. Therefore, intermetallic diffusion of gold-aluminum occurs in the mutual diffusion region 11, and the gold wire 5 and the wiring pad 4 are connected.

【０００６】[0006]

【発明が解決しようとする課題】しかしながら、このよ
うな半導体装置には次のような問題がある。すなわち、
半導体装置の小型化に伴い、配線用パッドの面積を小さ
くした場合、金ワイヤーのボール部の大きさを小さくす
る必要がある。ボール部の大きさが小さくなると、ボー
ル部と配線用パッドとの間の相互拡散領域が小さくな
り、配線に必要な接合強度が得られなくなってしまう。
このため、配線用パッドの面積縮小には限界があり、半
導体装置の小型化を図る場合の妨げとなる。よって、本
発明は金ワイヤーのボール部と配線用パッドとを効率よ
く接続できる半導体装置を提供することを目的とする。However, such a semiconductor device has the following problems. That is,
When the area of the wiring pad is reduced with the miniaturization of the semiconductor device, it is necessary to reduce the size of the ball portion of the gold wire. When the size of the ball portion is reduced, the mutual diffusion area between the ball portion and the wiring pad is reduced, and the bonding strength required for wiring cannot be obtained.
Therefore, there is a limit to the area reduction of the wiring pad, which hinders the miniaturization of the semiconductor device. Therefore, an object of the present invention is to provide a semiconductor device capable of efficiently connecting a ball portion of a gold wire and a wiring pad.

【０００７】[0007]

【課題を解決するための手段】本発明は、このような課
題を解決するために成された半導体装置である。すなわ
ち、半導体素子の上面に形成された配線用パッドに、金
ワイヤーのボール部を圧着したもので、このボール部を
圧着する配線用パッドの上面に、金ワイヤーの直径より
も大きく、ボール部の直径よりも小さい平面視外形を有
する凸部を設けたものである。また、この凸部の立ち上
がり面を、配線用パッドとボール部との接触面に形成さ
れる相互拡散領域内に含ませたものである。さらに、こ
の凸部と半導体素子との間に緩衝部材を設けたものであ
る。The present invention is a semiconductor device made to solve the above problems. That is, the ball portion of the gold wire is crimped to the wiring pad formed on the upper surface of the semiconductor element. It is provided with a convex portion having a plan view outer shape smaller than the diameter. Further, the rising surface of the convex portion is included in the mutual diffusion region formed on the contact surface between the wiring pad and the ball portion. Further, a cushioning member is provided between the convex portion and the semiconductor element.

【０００８】[0008]

【作用】配線用パッドに設けられた凸部により、ボール
部と配線用パッドとの接触面積が増加することになる。
また、配線用パッドとボール部との間の相互拡散領域内
に、配線用パッドに設けられた凸部の立ち上がり面が含
まれているため、相互拡散領域が広くなり、ボール部と
配線用パッドとの接合強度が増加する。さらに、凸部と
半導体素子との間に設けられた緩衝部材により、上方か
らボール部を加圧する際に半導体素子に加わる圧力を緩
和することができる。The convex portion provided on the wiring pad increases the contact area between the ball portion and the wiring pad.
Further, since the rising surface of the convex portion provided on the wiring pad is included in the mutual diffusion area between the wiring pad and the ball portion, the mutual diffusion area is widened and the ball portion and the wiring pad are The joint strength with Further, the buffer member provided between the convex portion and the semiconductor element can reduce the pressure applied to the semiconductor element when the ball portion is pressed from above.

【０００９】[0009]

【実施例】以下に、本発明の半導体装置を図に基づいて
説明する。図１は本発明の半導体装置を説明する図で、
（ａ）は配線用パッド部分の断面図、（ｂ）は配線用パ
ッド部分の平面図である。すなわち、この半導体装置１
は、シリコン等から成る半導体素子２と、この半導体素
子２の上面に窒化シリコン膜等の絶縁層３を介して形成
された配線用パッド４と、この配線用パッド４と電気的
に接続された金ワイヤー５とから構成されている。The semiconductor device of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram illustrating a semiconductor device of the present invention.
7A is a cross-sectional view of a wiring pad portion, and FIG. 7B is a plan view of the wiring pad portion. That is, this semiconductor device 1
Are electrically connected to the semiconductor element 2 made of silicon or the like, the wiring pad 4 formed on the upper surface of the semiconductor element 2 via the insulating layer 3 such as a silicon nitride film, and the wiring pad 4. It is composed of a gold wire 5.

【００１０】配線用パッド４と接続される金ワイヤー５
の先端には、火花放電等により形成されたボール部５１
が設けられている。配線用パッド４は、例えばアルミニ
ウムから成り、金ワイヤー５のボール部５１と配線用パ
ッド４との間に形成される相互拡散領域１１において、
金−アルミニウムの金属間拡散による接合が成されてい
る。Gold wire 5 connected to wiring pad 4
At the tip of the ball portion 51 formed by spark discharge or the like.
Is provided. The wiring pad 4 is made of, for example, aluminum, and in the inter-diffusion region 11 formed between the ball portion 51 of the gold wire 5 and the wiring pad 4,
A gold-aluminum intermetallic diffusion bond is formed.

【００１１】また、ボール部５１が圧着される配線用パ
ッド４の上面には、金ワイヤー５の直径ｄよりも大き
く、ボール部５１の直径Ｄよりも小さい平面視外形寸法
Ｒを有する凸部４１が設けられている。この凸部４１の
平面視外形は、ボール部５１を上方から加圧するための
キャピラリ（図３参照）の先端面の形状とほぼ同形であ
り、例えば円形より成るものである。また、凸部４１の
立ち上がり面４２は、相互拡散領域１１（図１（ｂ）斜
線部分）内に含まれており、配線用パッド４が平面であ
る場合に比べ、その表面積が広くなっている。Further, on the upper surface of the wiring pad 4 to which the ball portion 51 is pressure-bonded, the convex portion 41 having a plan view outer dimension R larger than the diameter d of the gold wire 5 and smaller than the diameter D of the ball portion 51. Is provided. The external shape of the convex portion 41 in plan view is substantially the same as the shape of the tip surface of the capillary (see FIG. 3) for pressing the ball portion 51 from above, and is, for example, circular. In addition, the rising surface 42 of the convex portion 41 is included in the mutual diffusion region 11 (hatched portion in FIG. 1B), and has a larger surface area than when the wiring pad 4 is a flat surface. ..

【００１２】また、この凸部４１と半導体素子２との間
には、ポリシリコンや酸化シリコン、窒化シリコン等か
ら成る緩衝部材４３が設けられており、ボール部５１を
キャピラリにて加圧する際に、半導体素子２に加わる圧
力を緩和している。したがって、この緩衝部材４３に
は、弾性係数の高い材質のものが適している。A buffer member 43 made of polysilicon, silicon oxide, silicon nitride, or the like is provided between the convex portion 41 and the semiconductor element 2, and when the ball portion 51 is pressed by the capillary. The pressure applied to the semiconductor element 2 is relaxed. Therefore, a material having a high elastic coefficient is suitable for the buffer member 43.

【００１３】このような、配線用パッド４と金ワイヤー
５のボール部５１とを接合するには、先ず、ボール部５
１を上方からキャピラリ（図３参照）にて加圧し、配線
用パッド４の上面に押し付ける。そして、半導体素子２
を２００℃〜３００℃に加熱して、ボール部５１と配線
用パッド４との間の相互拡散領域１１における金属間拡
散を利用して熱圧着を行う。また、熱圧着とともに、相
互拡散領域１１に超音波を加え、金属間拡散を促進して
もよい。To bond the wiring pad 4 and the ball portion 51 of the gold wire 5 as described above, first, the ball portion 5 is joined.
1 is pressed from above by a capillary (see FIG. 3) and pressed against the upper surface of the wiring pad 4. Then, the semiconductor element 2
Is heated to 200 ° C. to 300 ° C., and thermocompression bonding is performed by utilizing intermetallic diffusion in the mutual diffusion region 11 between the ball portion 51 and the wiring pad 4. In addition to the thermocompression bonding, ultrasonic waves may be applied to the mutual diffusion region 11 to promote intermetallic diffusion.

【００１４】このように、ボール部５１と配線用パッド
４との接合は、相互拡散領域１１における金属間拡散に
て行われており、この相互拡散領域１１は、キャピラリ
にて加圧される部分に発生するものである。すなわち、
相互拡散領域１１は、金ワイヤー５の直下にはほとんど
存在せず、金ワイヤー５の直下を除いたドーナツ状に形
成される。したがって、この相互拡散領域１１内に凸部
４１の立ち上がり面４２を含ませることでその表面積が
増加することになり、ボール部５１と配線用パッド４と
の接合強度の増加を図ることができる。As described above, the bonding between the ball portion 51 and the wiring pad 4 is performed by intermetallic diffusion in the interdiffusion region 11, and the interdiffusion region 11 is a portion that is pressed by the capillary. It occurs in. That is,
The interdiffusion region 11 almost does not exist immediately below the gold wire 5 and is formed in a donut shape excluding the area immediately below the gold wire 5. Therefore, by including the rising surface 42 of the convex portion 41 in the mutual diffusion region 11, its surface area is increased, and the joint strength between the ball portion 51 and the wiring pad 4 can be increased.

【００１５】ここで、金ワイヤー５の直径ｄを２５μ
ｍ、ボール部５１の直径Ｄを１００μｍとした場合の具
体的な一例を説明する。この場合、相互拡散領域１１
は、金ワイヤー５の周囲に約２０μｍ〜３０μｍの幅の
ドーナツ状に形成される。したがって、この相互拡散領
域１１内に凸部４１の立ち上がり面４２を含ませるに
は、約５０μｍの平面視外形寸法Ｒを有する凸部４１を
設ければよい。すなわち、金ワイヤー５の直径ｄの約２
倍〜２．５倍の大きさの凸部４１を設け、ボール部５１
の中心と凸部４１の中心とがほぼ一致した場合に、凸部
４１の立ち上がり面４２が相互拡散領域１１の略中央に
位置することになる。Here, the diameter d of the gold wire 5 is 25 μm.
m and the diameter D of the ball portion 51 is 100 μm, a specific example will be described. In this case, the mutual diffusion region 11
Is formed in a donut shape with a width of about 20 μm to 30 μm around the gold wire 5. Therefore, in order to include the rising surface 42 of the convex portion 41 in the mutual diffusion region 11, the convex portion 41 having the plan view external dimension R of about 50 μm may be provided. That is, about 2 of the diameter d of the gold wire 5
2 to 2.5 times the size of the convex portion 41, and the ball portion 51
When the center of the convex portion 41 and the center of the convex portion 41 substantially coincide with each other, the rising surface 42 of the convex portion 41 is located substantially at the center of the mutual diffusion region 11.

【００１６】一方、金ワイヤー５が位置ズレして接続さ
れた状態を図２の断面図に基づいて説明する。すなわ
ち、配線用パッド４に金ワイヤー５を接続する際、ワイ
ヤーボンディング装置の位置決め精度により、凸部４１
の中心とボール部５１の中心との位置ズレが発生する場
合がある。On the other hand, the state where the gold wire 5 is displaced and connected will be described with reference to the sectional view of FIG. That is, when the gold wire 5 is connected to the wiring pad 4, depending on the positioning accuracy of the wire bonding device, the convex portion 41 is formed.
There may be a displacement between the center of the ball and the center of the ball portion 51.

【００１７】例えば、前述の具体例のように、金ワイヤ
ー５の直径ｄを２５μｍ、凸部４１の平面視外形寸法Ｒ
を５０μｍとすると、凸部４１の中心とボール部５１の
中心とがほぼ一致した状態で、凸部４１の立ち上がり面
４２が相互拡散領域１１の略中央に位置するように凸部
４１が設けられている。この場合、金ワイヤー５の位置
ズレが凸部４１に対して±１０μｍ程度であれば、凸部
４１の立ち上がり面４２が相互拡散領域１１から外れる
ことがない。したがって、ワイヤーボンディング装置に
よる金ワイヤー５の位置ズレがこの範囲内であれば、金
ワイヤー５と配線用パッド４との接合強度が低下するこ
とはない。For example, as in the above-described specific example, the diameter d of the gold wire 5 is 25 μm, and the external dimension R of the projection 41 in plan view is R.
Is 50 μm, the convex portion 41 is provided so that the rising surface 42 of the convex portion 41 is located substantially in the center of the mutual diffusion region 11 in a state where the center of the convex portion 41 and the center of the ball portion 51 are substantially aligned. ing. In this case, if the positional deviation of the gold wire 5 is about ± 10 μm with respect to the convex portion 41, the rising surface 42 of the convex portion 41 does not come off from the mutual diffusion region 11. Therefore, if the positional deviation of the gold wire 5 by the wire bonding device is within this range, the bonding strength between the gold wire 5 and the wiring pad 4 will not be reduced.

【００１８】なお、本実施例において、配線用パッド４
の略中央部に一つの凸部４１を設けたものについて説明
したが、相互拡散領域１１内であれば、他の凸部４１を
設けてもよい。In this embodiment, the wiring pad 4 is used.
Although one convex portion 41 is provided in the substantially central portion of the above description, another convex portion 41 may be provided as long as it is in the mutual diffusion region 11.

【００１９】[0019]

【発明の効果】以上説明したように、本発明の半導体装
置によれば次のような効果がある。すなわち、ボール部
と配線用パッドとの接触面積が増加するとともに、相互
拡散領域の表面積が増加するため、配線用パッドのサイ
ズを小さくしても、金ワイヤーと配線用パッドとの配線
に必要な接合強度を得ることができる。したがって、半
導体装置を小型化することが可能となる。As described above, the semiconductor device of the present invention has the following effects. That is, since the contact area between the ball portion and the wiring pad increases and the surface area of the mutual diffusion region increases, even if the size of the wiring pad is reduced, it is necessary for wiring between the gold wire and the wiring pad. Bonding strength can be obtained. Therefore, the semiconductor device can be downsized.

【００２０】さらに、相互拡散領域の表面積の増加によ
り、効率よく接合が行えるため、熱圧着の際の設定温度
や、超音波の印加条件を緩和することができる。しか
も、凸部と半導体素子との間に設けられた緩衝部材によ
り、ワイヤーボンディングの際、キャピラリの加圧によ
り半導体素子に加わる圧力を緩和することができるた
め、半導体素子に生じるクレータリング等のダメージを
低減することができる。これにより、半導体装置の品質
向上を図ることが可能となる。Further, since the surface area of the interdiffusion region is increased, the bonding can be performed efficiently, so that the set temperature at the time of thermocompression bonding and the application conditions of ultrasonic waves can be relaxed. Moreover, since the buffer member provided between the convex portion and the semiconductor element can relieve the pressure applied to the semiconductor element by the pressure of the capillary during wire bonding, damage to the semiconductor element such as cratering. Can be reduced. This makes it possible to improve the quality of the semiconductor device.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の半導体装置を説明する図で、（ａ）は
配線用パッド部分の断面図、（ｂ）は配線用パッド部分
の平面図である。FIG. 1 is a diagram illustrating a semiconductor device of the present invention, in which (a) is a cross-sectional view of a wiring pad portion and (b) is a plan view of the wiring pad portion.

【図２】金ワイヤーの位置ズレ状態を説明する断面図で
ある。FIG. 2 is a cross-sectional view for explaining a positional deviation state of a gold wire.

【図３】従来の半導体装置を説明する断面図である。FIG. 3 is a cross-sectional view illustrating a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

１ 半導体装置 ２ 半導体素子 ３ 絶縁層 ４ 配線用パッド ５ 金ワイヤー ６ キャピラリ １１ 相互拡散領域 ４１ 凸部 ４２ 立ち上がり面 ４３ 緩衝部材 ５１ ボール部 DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor element 3 Insulating layer 4 Wiring pad 5 Gold wire 6 Capillary 11 Mutual diffusion area 41 Convex part 42 Rising surface 43 Buffer member 51 Ball part

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 半導体素子の上面に形成された配線用パ
ッドに、金ワイヤーのボール部が圧着された半導体装置
において、 前記ボール部が圧着される前記配線用パッドの上面に
は、前記金ワイヤーの直径よりも大きく、前記ボール部
の直径よりも小さい平面視外形を有する凸部が設けられ
ていることを特徴とする半導体装置。1. A semiconductor device in which a ball portion of a gold wire is crimped to a wiring pad formed on an upper surface of a semiconductor element, wherein the gold wire is provided on an upper surface of the wiring pad to which the ball portion is crimped. The semiconductor device is characterized in that a convex portion having a contour in plan view larger than the diameter of the ball portion and smaller than the diameter of the ball portion is provided. 【請求項２】 前記配線用パッドと前記ボール部との接
触面に形成される相互拡散領域に、前記凸部の立ち上が
り面が含まれていることを特徴とする請求項１記載の半
導体装置。2. The semiconductor device according to claim 1, wherein an interdiffusion region formed on a contact surface between the wiring pad and the ball portion includes a rising surface of the convex portion. 【請求項３】 前記凸部と前記半導体素子との間には、
緩衝部材が設けられていることを特徴とする請求項１記
載の半導体装置。3. Between the convex portion and the semiconductor element,
The semiconductor device according to claim 1, further comprising a buffer member.
JP4116875A 1992-04-08 1992-04-08 Semiconductor device Pending JPH05291364A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4116875A JPH05291364A (en) 1992-04-08 1992-04-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4116875A JPH05291364A (en) 1992-04-08 1992-04-08 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH05291364A true JPH05291364A (en) 1993-11-05

Family

ID=14697800

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4116875A Pending JPH05291364A (en) 1992-04-08 1992-04-08 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH05291364A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008294159A (en) * 2007-05-23 2008-12-04 Denso Corp Manufacturing method of semiconductor device and semiconductor device
WO2022114185A1 (en) * 2020-11-30 2022-06-02 住友大阪セメント株式会社 Optical waveguide element, optical modulator, optical modulation module, and optical transmission device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008294159A (en) * 2007-05-23 2008-12-04 Denso Corp Manufacturing method of semiconductor device and semiconductor device
WO2022114185A1 (en) * 2020-11-30 2022-06-02 住友大阪セメント株式会社 Optical waveguide element, optical modulator, optical modulation module, and optical transmission device

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