JPH0218956A - Lead frame for semiconductor device - Google Patents

Lead frame for semiconductor device

Info

Publication number
JPH0218956A
JPH0218956A JP16934888A JP16934888A JPH0218956A JP H0218956 A JPH0218956 A JP H0218956A JP 16934888 A JP16934888 A JP 16934888A JP 16934888 A JP16934888 A JP 16934888A JP H0218956 A JPH0218956 A JP H0218956A
Authority
JP
Japan
Prior art keywords
lead
inner lead
bonding
lead frame
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16934888A
Other languages
Japanese (ja)
Other versions
JPH07120743B2 (en
Inventor
Takaaki Mitsui
孝昭 三井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui High Tec Inc
Original Assignee
Mitsui High Tec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui High Tec Inc filed Critical Mitsui High Tec Inc
Priority to JP63169348A priority Critical patent/JPH07120743B2/en
Publication of JPH0218956A publication Critical patent/JPH0218956A/en
Publication of JPH07120743B2 publication Critical patent/JPH07120743B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Abstract

PURPOSE:To prevent the mechanical breakdown of a chip and the connection failure by providing a deformed part extending inside the same plane near the end in an inner lead of a lead frame. CONSTITUTION:In a lead frame that the end of an inner lead 1 has a bump 11a and that the bump 11a is connected directly to the bonding pad of a semiconductor element, the inner lead 1 connected to the bonding pad is equipped with a deformed part 12 extending inside the same plane near the end. Accordingly, the deformed part 12 provided at the end of the inner lead 1 absorbs the expansion and contraction of the lead caused by heat history at the time of bonding or in a mold process, etc. Hereby, the mechanical breakdown of a chip and the connection failure can be prevented.

Description

【発明の詳細な説明】 (発明の目的) (産業上の利用分野) 本発明は゛+’4体装置用リードフレームに係り、特に
そのリードフレームの先端部の形状に関する。
DETAILED DESCRIPTION OF THE INVENTION (Objective of the Invention) (Industrial Application Field) The present invention relates to a lead frame for a four-body device, and particularly to the shape of the tip of the lead frame.

(従来の技術) リードフレームと半導体素子(チップ)との接続方式は
ワイヤを用いるワイヤボンディング方式と、ワイヤを用
いることなく半導体素子を導体パターン而に直接固着づ
るワイヤレスボンディング方式とに大別される。
(Prior art) Connection methods between lead frames and semiconductor elements (chips) are broadly divided into wire bonding methods that use wires and wireless bonding methods that directly bond semiconductor elements to conductive patterns without using wires. .

これらのうちワイヤボンディング方式は、第6図に示す
ようなリードフレームのダイパッド10に、第7図に示
す如くチップ20を熱圧着によりあるいは導電性接着剤
等により固着し、このチップ20のボンディングパッド
とリードフレームのインナーリード1の先端とを金線等
を用いて電気的に接続するもので、1本ずつ接続するた
めボンディングに要する片間が長く信頼性の面でも問題
があった。
Among these, the wire bonding method is a method in which a chip 20 is fixed to a die pad 10 of a lead frame as shown in FIG. 6 by thermocompression bonding or with a conductive adhesive as shown in FIG. and the tips of the inner leads 1 of the lead frame are electrically connected using a gold wire or the like, and since the wires are connected one by one, the distance required for bonding is long, which also poses problems in terms of reliability.

また、ワイヤレス4;ンディング方式にもいろいろな方
式があるが、その代表的なものの1つに、第8図に示す
如く、インナーリード1の先端に伸長づる肉薄のパター
ン11の先端に形成されたバンプ11aをチップ20の
ボンディングパッドに直接接続することによりチップ2
0とインナーリード1とを電気的に接続するダンプ式ボ
ンディングh式(バンブ付TAB方式)がある。
In addition, there are various types of wireless ending methods, and one of the typical ones is a thin pattern 11 formed at the end of a thin pattern 11 extending from the end of the inner lead 1, as shown in FIG. By directly connecting the bumps 11a to the bonding pads of the chip 20, the chip 2
There is a dump type bonding h type (TAB type with bump) which electrically connects the inner lead 0 and the inner lead 1.

上記ダンプ式ボンディングは、ワイヤボンディングのよ
うに1本づつボンディングするのではなく、チップに全
リードの先端を1度にボンディングすることができるた
め、ボンディング時間の大幅な短縮を図ることができる
上、ワイヤボンディング方式で必要であったワイヤルー
プ分の高さが不要となり半導体装置の小形化をはかるこ
とができる。
The dump type bonding described above can bond the tips of all leads to the chip at once instead of bonding one lead at a time like wire bonding, so it can significantly shorten the bonding time. The height of the wire loop required in the wire bonding method is no longer necessary, and the semiconductor device can be made smaller.

(yP、明が解決しようとする課題) しかしながら、このようなダンプ式ボンディングにおい
ては、ワイヤボンディングのように1本づつボンディン
グするのではなく、チップに全リードの先端を1度にボ
ンディングでるため、ボンディング時の熱も、ワイヤボ
ンディングでは170℃〜200″Cぐあるのに対し、
このダンプ式ボンディングでは400℃〜600℃と高
熱となる。
(Problem that yP and Akira are trying to solve) However, in such dump type bonding, the tips of all the leads are bonded to the chip at once, instead of bonding one lead at a time like in wire bonding. The heat during bonding is 170℃ to 200''C in wire bonding,
This dump type bonding generates high heat of 400°C to 600°C.

インナーリード(よ剛体であるため、この熱によりイン
ナーリードが伸長し、ボンディングパッドとの接続部分
にストレスが集中し、チップの□械的破損や接続不良を
生じるという問題があった。
Since the inner lead is a relatively rigid body, the heat causes the inner lead to elongate, and stress concentrates on the connection part with the bonding pad, causing mechanical damage to the chip and poor connection.

また、ボンディング後にチップ保護のために樹脂ケース
内にチップを封止するモールド工程を経なければならな
いが、このモールド工程で受ける熱によっても同様にデ
ツプの機械的破損や接続不良の問題があった。
Additionally, after bonding, a molding process must be performed to seal the chip in a resin case to protect the chip, but the heat received during this molding process also causes problems such as mechanical damage to the depth and poor connections. .

本発明は前記実情に篤みてなされたもので、上記ダンプ
式ボンディングにおける問題点を解決し、信頼性の高い
半導体装置を提供することのできる半導体¥装置用リー
ドフレームを提供することを目的とする。
The present invention has been made in consideration of the above-mentioned circumstances, and an object of the present invention is to provide a lead frame for a semiconductor device that can solve the problems in the dump type bonding and provide a highly reliable semiconductor device. .

(問題点を解決するための手段) そこで本発明では、リードフレームのインナーリードに
、その先端近傍で同一平面内に伸びる変形部を配設して
いる。
(Means for Solving the Problems) Therefore, in the present invention, the inner lead of the lead frame is provided with a deformable portion extending in the same plane near the tip thereof.

(作用) 上記構成により、インナーリードの先端に設けられた変
形部が、ボンディング時やモールド工程等における熱履
歴によるリードの伸縮を吸収するため、チップの濾械的
破損や接続不良を防止することができる。
(Function) With the above configuration, the deformed portion provided at the tip of the inner lead absorbs expansion and contraction of the lead due to thermal history during bonding, molding process, etc., thereby preventing mechanical damage to the chip and poor connection. I can do it.

(実施例) 以F、本発明の実施例について、図面を参照しつつ、詳
細に説明する。
(Embodiments) Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

この半導体装置用リードフレームは、第1図に要部説明
図を示すように、インナーリード1の先端に伸長する肉
薄のパターン11が交互に両側部から3つの矩形の切欠
12を有していることを特徴とするもので、他の部分に
ついては、従来のリドフレームと同様に形成されている
As shown in FIG. 1, which is an explanatory view of the main part, this lead frame for a semiconductor device has a thin pattern 11 extending from the tip of an inner lead 1 and three rectangular notches 12 alternately formed on both sides. Other parts are formed similarly to conventional lid frames.

すなわら、第2図に示すように、この半導体装置用リー
ドフレームは、インナーリード1と、これを一体向に支
持するタイバー2と、インナーリード1に連設されたア
ウターリード3と、これらを支持する枠体4とから構成
されている。
In other words, as shown in FIG. 2, this lead frame for a semiconductor device includes an inner lead 1, a tie bar 2 that integrally supports the inner lead 1, an outer lead 3 connected to the inner lead 1, and an outer lead 3 connected to the inner lead 1. It is composed of a frame body 4 that supports the.

また、インナーリード1の先端にはバンブ付パターン1
1が一体成形されていることはいうまでもない。
In addition, the tip of the inner lead 1 has a bump pattern 1.
1 is integrally molded.

そして、このリードフレームへのチップの実装に際して
は、第3図に示すように、まず支持台(図示せず)上に
載置されたチップ20のボンディングパッド上に、イン
ナーリード1の先端のバンブ付パターン11のバンブが
当接するようにインナーリードを位置決めした後、イン
ナーリード1の裏面側から加圧しつつ加熱して、バンブ
表面にあらかじめ形成されている半田層を溶融すること
により両者が固着接続される。
When mounting a chip on this lead frame, as shown in FIG. After positioning the inner lead so that the bumps of the attached pattern 11 are in contact with each other, heat is applied while applying pressure from the back side of the inner lead 1 to melt the solder layer previously formed on the bump surface, thereby firmly connecting the two. be done.

そしてこの後、モールド工程を経て半導体装置が完成す
るわけであるが、リードフレームへのチップの実装に際
してチップのボンディングパッドとインナーリードの先
端のバンブ付パターンのバンブとの固着工程における熱
履歴によってもモルド工程における熱履歴によっても、
バンブ付パターン11aの変形部が熱歪を吸収するため
、チップにクラックを生じたり、接続不良を生じたりす
ることはない。
After this, the semiconductor device is completed through a molding process, but when mounting the chip on the lead frame, heat history during the bonding process between the bonding pad of the chip and the bump of the bumped pattern at the tip of the inner lead may cause Depending on the thermal history during the molding process,
Since the deformed portion of the bumped pattern 11a absorbs thermal strain, cracks in the chip and connection failures do not occur.

なお、前記実施例では、インナーリード先端の両側部に
矩形の切欠を形成して熱歪吸収用の変形部を構成したが
、この形状に限定されることなく、変形例として第4図
に示すようにインナーリード先端の両側部に円形の切欠
22を形成して変形部を構成したもの、第5図に示すよ
うにインナーリドの先端を同一面内で鋭角をなすように
曲がった曲折部32を形成して変形部を構成したもの等
も有効である。
In the above embodiment, a rectangular notch was formed on both sides of the tip of the inner lead to constitute a deformable part for absorbing thermal strain. However, the shape is not limited to this, and a modified example shown in FIG. As shown in FIG. 5, circular notches 22 are formed on both sides of the tip of the inner lead to form a deformed part, and as shown in FIG. It is also effective to form a deformed portion by forming a deformed portion.

(発明の効果) 以上説明したように本発明によれば、リードフレームの
インナーリードに、その先端近傍で同一平面内に伸びる
変形部を配設しているため、この変形部が熱履歴による
リードの伸縮を吸収して、チップの機械内破1や接続不
良を防止し、信頼性の高い半導体装置を得ることができ
る。
(Effects of the Invention) As explained above, according to the present invention, the inner lead of the lead frame is provided with a deformed portion that extends in the same plane near the tip of the inner lead. It is possible to absorb the expansion and contraction of the chip, prevent mechanical implosion 1 of the chip and poor connection, and obtain a highly reliable semiconductor device.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係る半導体装置用リードフレームの要
部図、第2図は同半導体装置用リードフレームを示す図
、第3図は同リードフレームのボンディング後の状態を
示す図、第4図および第5図は、本発明のリードフレー
ムの変形例を示す図、第6図は従来のリードフレームの
一例を示す平面図、第7図はワイヤボンディングの説明
図、第8図は従来のダンプ式ボンディングの説明図であ
る。 1・・・インナーリード、2・・・タイバー 3・・・
アウターリード、4・・・枠体、10・・・ダイパッド
、11a・・・バンプ、11・・・肉薄のパターン、1
2・・・切欠、20・・・チップ、22・・・切欠、3
2・・・曲折部。 第1図 第3図 第4図 ! 第2図 第5図
FIG. 1 is a diagram showing the main parts of a lead frame for a semiconductor device according to the present invention, FIG. 2 is a diagram showing the lead frame for a semiconductor device, FIG. 3 is a diagram showing the state of the lead frame after bonding, and FIG. 5 and 5 are diagrams showing a modified example of the lead frame of the present invention, FIG. 6 is a plan view showing an example of a conventional lead frame, FIG. 7 is an explanatory diagram of wire bonding, and FIG. 8 is a diagram showing a conventional lead frame. It is an explanatory view of dump type bonding. 1... Inner lead, 2... Tie bar 3...
Outer lead, 4... Frame body, 10... Die pad, 11a... Bump, 11... Thin pattern, 1
2... Notch, 20... Chip, 22... Notch, 3
2...Bending part. Figure 1 Figure 3 Figure 4! Figure 2 Figure 5

Claims (1)

【特許請求の範囲】 インナーリードの先端にバンプを有し、当該バンプを半
導体素子のボンディングパッドに直接接続するダイレク
トボンド用のリードフレームにおいて、 前記ボンディングパッドに接続されるインナーリードは
、その先端近傍で同一平面内に伸びる変形部を具備して
なることを特徴とする半導体装置用リードフレーム。
[Claims] In a lead frame for direct bonding, which has a bump at the tip of an inner lead and directly connects the bump to a bonding pad of a semiconductor element, the inner lead connected to the bonding pad is located near the tip of the inner lead. A lead frame for a semiconductor device, comprising a deformable portion extending in the same plane.
JP63169348A 1988-07-07 1988-07-07 Lead frame for semiconductor device Expired - Fee Related JPH07120743B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63169348A JPH07120743B2 (en) 1988-07-07 1988-07-07 Lead frame for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63169348A JPH07120743B2 (en) 1988-07-07 1988-07-07 Lead frame for semiconductor device

Publications (2)

Publication Number Publication Date
JPH0218956A true JPH0218956A (en) 1990-01-23
JPH07120743B2 JPH07120743B2 (en) 1995-12-20

Family

ID=15884900

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63169348A Expired - Fee Related JPH07120743B2 (en) 1988-07-07 1988-07-07 Lead frame for semiconductor device

Country Status (1)

Country Link
JP (1) JPH07120743B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6075282A (en) * 1997-06-02 2000-06-13 Sgs-Thomson Microelectronics S.A. Leadframe for a semiconductor device and associated method
US6208017B1 (en) * 1994-10-07 2001-03-27 Nec Corporation Semiconductor device with lead-on-chip structure
JP2018046200A (en) * 2016-09-15 2018-03-22 アイシン精機株式会社 Element unit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57117264A (en) * 1980-11-28 1982-07-21 Western Electric Co Capsule device for semiconductor integrated circuit chip

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57117264A (en) * 1980-11-28 1982-07-21 Western Electric Co Capsule device for semiconductor integrated circuit chip

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6208017B1 (en) * 1994-10-07 2001-03-27 Nec Corporation Semiconductor device with lead-on-chip structure
US6075282A (en) * 1997-06-02 2000-06-13 Sgs-Thomson Microelectronics S.A. Leadframe for a semiconductor device and associated method
JP2018046200A (en) * 2016-09-15 2018-03-22 アイシン精機株式会社 Element unit

Also Published As

Publication number Publication date
JPH07120743B2 (en) 1995-12-20

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