JPH0528528B2 - - Google Patents

Description

[Detailed description of the invention] [Technical field of the invention]
The present invention relates to a MOS semiconductor device including the following highly miniaturized MOS transistors.

[Technical background of the invention and its problems] In general, the development of MOS type semiconductor devices including MOS transistors has been remarkable, and in the latter half of the 1960s, the degree of integration using MOS transistors with an effective channel length of about 10 μm was in the tens of tens of meters. Devices with hundreds of elements have been realized. Furthermore, with advances in microfabrication and higher integration, in recent years the effective channel length has become 1.5μm.
The number of elements has continued to evolve into VLSI with hundreds of thousands of elements, and even higher speed and lower power consumption semiconductor devices have been realized using highly integrated MOS transistors with an effective channel length of 1 μm or less. Ta.

By the way, in conventional MOS semiconductor devices, the internal functional circuits are operated directly by external power supply, and the supply power supply voltage also constitutes the internal functional circuits.
It has been reduced as the effective channel length of MOS transistors has been reduced. For example, the device with an effective channel length of 1.5 μm is operated under a single 5V power supply.

However, from the viewpoint of reliability, it is difficult to operate a further miniaturized MOS element under the same power supply voltage as before. because,
As the electric field in the MOS device increases, carriers with high energy jump into the oxide film.
This is because the reliability of the element is impaired. Also, traditional
In MOS type semiconductor devices, in order to solve problems such as leakage current below the threshold voltage and undershoot of nodes including diffusion layers, and to reduce the junction capacitance of diffusion layers, for example, in the case of N-channel devices, In other words, the semiconductor substrate was biased to a potential lower than the ground potential and the device junctions were reverse biased.
(See Figure 8).

However, as shown in FIG.
-ch), this bias generation circuit wastes power, and even during standby, extra power is consumed. Also,
For example, when applying the substrate bias using a CMOS element, an NPN transistor formed by an N ⁺ diffusion layer in the source and drain regions of an N-channel MOS transistor, a P well region, and an N substrate or a
Between the emitter and base of the NPN transistor formed by the N ⁺ diffusion layer, P substrate, and N well region,
Since a high impedance substrate bias generation circuit is involved, it has the disadvantage of being prone to latch-up, a problem unique to CMOS.

[Object of the Invention] The present invention has been made in view of the above points. For example, even when the degree of integration of elements is miniaturized to a high density, it is possible to achieve highly reliable operation without being directly supplied with an external power supply voltage. This also makes it possible to significantly reduce power consumption during standby.
The purpose is to provide a MOS type semiconductor device.

[Summary of the Invention] That is, the MOS type semiconductor device according to the present invention lowers the power supply voltage supplied from the external power supply terminal through a constant voltage drop circuit whose voltage drop exhibits nonlinearity with respect to the current. A dropped voltage is supplied to an internal power supply terminal of a MOS type main circuit formed on the same substrate, and the substrate region or its well region is connected to the external power supply terminal.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows its conceptual block configuration. This MOS type semiconductor device is composed of a MOS type main circuit 11 whose effective channel length is miniaturized to 1 μm or less, for example, and a constant voltage drop circuit 12. . The internal power supply terminal Vs of the main circuit 11 is connected via a constant voltage drop circuit 12 to the external power supply terminal Vss, which is at ground potential. Further, the external power supply terminal Vss on the side to which the constant voltage drop circuit 12 is connected is connected to the substrate region or well region of the element constituting the MOS type main circuit 11.

Next, FIG _. 2 shows a specific circuit configuration of the embodiment circuit shown in _FIG . connects the external power supply terminal Vss at ground potential via the constant voltage drop circuit 12.
This constant voltage drop circuit 12 is constructed by connecting in series a MOS transistor Q ₁ whose gate electrode and source electrode are connected, and diodes D ₁ and D ₂ , respectively. Here, the current-voltage characteristics of the constant voltage drop circuit 12 are, for example, as shown in FIG.
It has a constant voltage characteristic with small dependence on the current passing through it, that is, a characteristic in which the voltage drop V is nonlinear with respect to the current I. That is, although the main circuit current I _A varies greatly depending on each operating mode, the associated voltages Vs1 and Vs2 corresponding to points A and B are suppressed to voltage variations only within a small range. Here, the transistor Q ₁ is, for example, the main circuit 11
even if it is in standby mode with no current flowing.
This is to set a potential difference of, for example, about 0.7V per diode _D1 between the power supply terminals Vs and Vss to supply a substrate bias. In this case, the current consumption becomes extremely small. Further, as a result, a negative substrate bias is supplied to each of the MOS transistors Q ₂ to _{Q 6} via the external power supply terminal Vss immediately after power is turned on. Further, the constant voltage drop circuit 12 has a current driving ability capable of supplying a large current consumed by the main circuit 11, and thereby the voltage supplied to the MOS type main circuit 11 is, for example, The voltage is now lowered to Vs2, which corresponds to point A in FIG. Therefore, high operational reliability of the miniaturized MOS type circuit 11 can be obtained.

Here, FIG. 4 shows the diode structure of the constant voltage drop circuit 12 in FIG.
The above terminal K is connected to Vss, and the above terminal A is connected to Vs and high resistance R.
Connected to Vcc via. In other words, by surrounding the P-type diffusion layer, which serves as the base region, with the N-type collector region, electrons injected from the N ⁺ region through the K terminal can be completely collected in the collector region, and simply Unlike when a PN junction is formed, problems such as latch-up are prevented because minority carriers do not diffuse into the substrate.

Next, other embodiments of the present invention are shown in FIGS. 5 to 7, respectively.

First, in the example circuit shown in FIG.
In the type circuits I ₁ , I ₂ , I ₃ , only the power supply terminal of the input stage circuit I ₁ that needs to detect a particularly small amplitude is directly connected to the power supply terminal Vss of the constant voltage drop circuit 12.
Connect to. As a result, the input stage circuit _I1 becomes
It is not affected by the voltage drop Vs of the constant voltage drop circuit 12, which fluctuates even if slightly. Here, only the MOS transistor in the input stage _I1 is made to have a high breakdown voltage. In this case, since the input stage _I1 occupies an extremely small area on the substrate, it hardly affects the integration density of the elements.

The embodiment circuit shown in FIG. 6 shows the case where the present invention is applied to a memory device, and only one memory cell is shown in the memory cell array MCA in the figure, but in reality, such a circuit is shown. It is assumed that a large number of memory cells are arranged in rows and columns. In other words, in this memory cell array MCA, the word line WL running in the row direction turns on/off the selection transistor Q to select a memory cell, and the bit line BL running in the column direction writes and calls signals. . Here, voltage drop circuit 1 is connected to the power supply terminal of bit line drive circuit D _B.
2, and the level of the bit line BL and the memory cell node M are set to the above-mentioned voltage drop.
Avoid dropping below Vs. As a result, the bit line BL is always maintained at a level higher than the substrate potential, and its junction capacitance reduces stray capacitance. In addition, the common terminal voltage Vp in the capacitive element Cm of each memory cell
When the late changes, the memory node M also changes due to capacitive coupling, but if the above capacitive element
If the terminal voltage Vp late of Cm fluctuates in the negative direction due to, for example, noise entering the power supply, the memory node M becomes a voltage lower than the written lowest potential. In other words, even in such a case, the output voltage Vs of the voltage drop circuit 12
Since there is a difference between the substrate potential Vss and the substrate potential Vss, forward bias does not occur between the PN junctions of the element.

In each of the above embodiments, a case has been described in which the constant voltage drop circuit 12 is interposed between the external power supply terminal Vss on the constant voltage side and the internal power supply terminal Vs of the MOS type main circuit 11, but for example, C (complementary) interposed between the external power supply terminal Vcc on the high potential side and the internal power supply terminal of the main circuit 11, respectively.
The substrate bias of a P-channel MOS transistor in a MOS type circuit may be obtained. In the example circuit of the memory device shown in FIG. 7, a constant voltage drop circuit 12 is provided between the external power supply terminal Vcc on the high potential side and the internal power supply terminal Vc of the bit line drive circuit D _B of the memory cell array MCA. Interpose and compose. As a result, the potential of the bit line BL is lowered, and the voltage applied to the MOS transistor of the drive circuit D _B , especially the voltage applied between the source and the drain, is lowered, and the reliability is improved in the same way as in the above embodiment. This also allows the word line WL
There is no need to use a bootstrap circuit to raise the high-voltage potential of Vcc to a level higher than the power supply voltage Vcc.

[Effects of the Invention] As described above, according to the present invention, the power supply voltage supplied from the external power supply terminal is lowered through a constant voltage drop circuit whose voltage drop exhibits nonlinearity with respect to the current, and this drop is reduced. Voltage is supplied to the internal power supply terminals of the MOS type main circuit formed on the same substrate, and the substrate region or its well region is connected to the external power supply terminals. Even when miniaturized, it is possible to provide a MOS semiconductor device that can operate with high reliability without being directly supplied with an external power supply voltage, and can significantly reduce power consumption during standby. .

[Brief explanation of the drawing]

FIG. 1 is a schematic block configuration diagram showing a MOS type semiconductor device according to an embodiment of the present invention, FIG. 2 is a circuit configuration diagram showing a specific example of the MOS type semiconductor device in FIG. 1, and FIG. In Figure 2 above
A diagram showing the current-voltage characteristics of a constant voltage drop circuit in a MOS type semiconductor device, Figure 4 is the same as in Figure 2 above.
5 to 7 are cross-sectional views of substrates showing the diode structure of a constant voltage drop circuit in a MOS semiconductor device.
The figures show other embodiments of the invention, and FIG. 8 shows a conventional MOS type semiconductor device. 11...MOS type main circuit, 12...constant voltage drop circuit, Vss, Vcc...external power supply terminal, Vs, Vc...
...internal power supply terminal, Q ₁ to _{Q 6} ...MOS transistor, D ₁ , D ₂ ... diode, I ₁ ... input stage circuit,
D _B ...Bit line drive circuit.

Claims (1)

[Scope of Claims] 1. An external power supply terminal to which a power supply voltage is supplied from the outside; and 1 or 2 terminals connected in series in which the voltage drop caused by the voltage supplied from the external power supply terminal exhibits nonlinearity with respect to the current. a constant voltage drop circuit having at least 10 diodes, a MOS type bit line drive circuit for memory cells formed on the same substrate as this constant voltage drop circuit, and and a power supply terminal of the MOS type bit line drive circuit for the memory cell to which voltage is supplied, and a substrate region where the MOS type bit line drive circuit for the memory cell is formed or its well region is connected to the external power supply terminal. MOS type semiconductor device characterized in that the level of the bit line is maintained at a level higher than the substrate potential.