JPS62208496A - Mos integrated circuit - Google Patents

Abstract

PURPOSE:To contrive a stable action by setting the low potential of an external power source to a substrate bias, boosting the low potential in a chip through a power source/voltage conversion circuit and supplying it as the source power source voltage of an internal circuit. CONSTITUTION:A VccExt directly inputs as the internal drain power source voltage 110 of the internal circuit 109 in the chip, is boosted to a 2V by the power source voltage conversion circuit 115 in the chip, and inputted to the internal circuit 109 as a VssInt. 116. The VssExt. 107 outside the chip is connected to a package seat 101 on the conductive surface, and acts as the substrate potential VBB 117. Since a Vssext. with a high power source capacity is used as a VBB, the malfunction is considerably improved, and at the time of discharging a bit line the VccExt and VssExt with high power source capacities are directly resistance-divided. Thus a Vref is stabilized, and the power source voltage conversion circuit including the substrate bias is only of one system, whereby the internal circuit 109 including an address buffer circuit main body can be resistant to noise.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention is directed to a dynamic RAM (CDRAM) equipped with a source power voltage conversion circuit in a chip.
Regarding S integrated circuits.

[Technical background of the invention and its problems]

MO8 integrated circuits and memories are rapidly becoming more highly integrated and larger in capacity.

Along with this, the devices used are being miniaturized. For this reason, device breakdown voltage, reliability, etc. have become issues, and in terms of process, LDD (Lightly Doped)
Although improvements have been made to the drain structure, etc., there are limits to the device's withstand voltage and reliability, and low voltage technology is essential for circuit design.

For example, in the case of dynamic [{AM(L)RAM),
5Veli-power supply method is 64 as external input supply voltage
Adopted from KDRAM, 256. IM has also been commercialized using this method. The number of users using DRAM is also 4M.

I strongly hope for this 5v Rinichi power supply system for 16M as well. For this reason, in the 4Ivi DRAM, a step-down circuit is installed inside the chip in consideration of the resistance and reliability of the device mentioned above, and the external source width voltage of 5V is reduced to about 3V, and the internal drain width voltage is applied to the chip. A method of supplying power to each internal circuit is being tested.

However, in the method of incorporating a step-down circuit, the chip has both a step-down circuit and a substrate bias conversion circuit.
This hinders high integration and increases current consumption. Furthermore, if the outputs of both circuits fluctuate due to noise during chip operation, there is a risk of circuit malfunction. This problem becomes more noticeable as the capacity of memory cells increases. This is because the transient current during chip operation increases as the capacity increases, and as the wiring width decreases, the inductance υ inside the chip also tends to decrease vc.

(Purpose of the Invention) This Yumei was developed in consideration of the above problems, and while it improves the withstand voltage and reliability of the device, it also reduces the risk of circuit malfunction due to power supply noise and enables stable operation (I )S
The purpose of the ink is to provide a drop habit circuit.

[Summary of the invention]

In the present invention, a source power voltage conversion circuit is built inside the chip, and its output is converted to the source power voltage inside the chip.
The source power supply voltage outside the chip is input as the chip's substrate bias, and the drain power supply voltage outside the chip is input as the chip's substrate bias.
The main idea is to use it directly as a drain source pressure inside the chip.

〔Effect of the invention〕

According to the present invention, by using a source power supply voltage conversion circuit, the source power supply voltage inside the chip can be increased by, for example, 2 VIC from Ov, and the voltage applied to the device can be relatively reduced, and the withstand voltage and reliability of the device can be sufficiently guaranteed. .

In addition, while reducing the voltage applied to the device in this way, the external source power supply voltage is used directly as the substrate bias for the chip, which eliminates the need for the substrate bias generation circuit that was conventionally built inside the chip. It is possible to reduce the area and the current consumption during standby.

Furthermore, in DRAMs, fluctuations in the reference potential (Vrei) of address buffer circuits and the like are a major problem, but it is possible to stabilize the substrate bias, which is highly effective in preventing malfunctions.

[Embodiments of the invention]

Embodiments of the invention will be described below with reference to the drawings.

FIG. 1 schematically shows a system block diagram of a DRAM.

The surface of the pedestal 101 of the IC package is coated with a conductive layer, and the JRAM chip 102 is mounted on the back surface [10] in contact with the conductive layer. Chip drain power supply voltage pad 10
3 and the source power supply pad 104 are connected to the drain external power supply voltage (VccExt
) 106 and the source external voltage (Vss Ext
) 107 respectively. 108 is a blocking capacitor, and here VccExt is 5 V,
VssExt is Ov.

VccExt Vi Direct internal drain power supply voltage of internal circuit 109 inside chip (Vcc Int, ) 110
Enter as .

The internal circuit 1()9 is the basic tarlock generation circuit ill and Dt.
(AM circuit 112≠1 et al. 11) 1, l) R, AM
The circuit 112 consists of a core circuit 113 such as a DR memory cell and a sense amplifier, and peripheral circuits 114 such as a precharge circuit, a decoder circuit, an address buffer circuit, and a 110 circuit.

On the other hand, sVssExt is boosted up to 2V from the power supply conversion circuit 115 inside the chipf'L, VssInt,
116 and input it to the internal circuit 109. In addition, the chip external chip (CI) VssExt, 107 is connected to the conductive surface package pedestal 101K, and the chip 1
Works as 020 board 7E VBB (1).

The source power supply voltage conversion circuit 115 has a block configuration shown in FIG. 201 is a reference potential generation circuit, 202 is an error amplification circuit, and 203 is an internal source potential load circuit. The chip internal source potential VssInt, 116 and the reference potential 204 set by the reference potential generation circuit 201V.
The error amplifier circuit 202 amplifies the potential difference, and the internal source potential load circuit 203VC controls the current consumption of the internal circuit 109 to stabilize the chip internal source potential VssInt.

Figure i3 is the actual circuit diagram of Figure 2. That is, VccE
xt, , VssF; xt, 5V, OV is connected to resistor R1
+R2 and a reference potential 204 is provided. The error Vθ width circuit 202 is p −ch K) SFFW Q
1~Q a and n-ch MO8FE″rQ4, Q
Q6 is a current mirror type error amplification circuit (4).
-chMO8FET.

In Fig. 3, the CMO8fN configuration is shown, but it is also possible to configure it with n-chMO8FETs as shown in Fig. 4).

Here, Ql-Q3 are D type MOSFETs, and Q4 to Q6 are E type MOSFETs.

In FIGS. 3 and 4, the chip internal source reference t is set to 204 by resistor division, but as shown in FIG. 5, for example, n-channel 5FETs Q7 to Qto may be used.

FIG. 6 shows a circuit diagram of the address buffer circuit described above. That is, the middle of the interpupillary distance Tff obtained by resistance-dividing the address input signal Ain of minute amplitude at the T'rL level,
Ain detects whether it is high by comparing it with the reference potential Vref set at
o u ts A complementary signal Aout is obtained.

Conventionally, in a circuit using a substrate bias circuit, the substrate potential VnB tends to fluctuate due to the junction capacitance of the diffusion layer of the memory cell that contacts the bit line photodischarge FRfrfrc bit line.
This causes a problem in that the Vref line, which is opposite to this via the oxide film on the surface of the substrate, fluctuates, causing the address buffer circuit to malfunction.

FIG. 7 shows an operational waveform diagram of the address buffer circuit of FIG. 6, and the operation will be briefly explained below.

First, clock signal φ1. φ2. φ3. If φ4 moves each L H"'f("L'"L", then ("f("=5V,
"L"=2V), the MO8FETs Ql 3 and Ql4 become conductive, the node Nl is brought to the address input terminal level, and the node N2 is brought to the reference potential. - 10,000, Nυ
Do'h'T Q211Q221Q23 also becomes conductive, and the node N5 +N6 is photoelectronized to ``[('' and N'tosF
h, 'T Qly+Qts*Qza+Qz7 is also in the conductive state ic fx, φ3. Since φ4 is “L”, N3. N
4. Aout and Aout are all +LH.

Next, clock signal φ1. φ2 is ``H'H' level L''
The level VC changes, and then the clock (Fj signal φ3 becomes L)
"to H". Then, MOSFET Q ty
, Q t s Ic husband to node N3 rN4 to φ3
Try to transfer the level of.

However, the nodes Nl, N2 tj force SF'ET Qt
l + Qt 2 leads to 1! ! 1, and the level is sufficient to cause the node N1t/-)'N21Ci v level difference y)=;p) 7'c MEML) SFET Qt t
Since there is a difference in conductance between Qtz and Qtz, node N3
There is a level difference between N4 VC and N4 VC. Here A1n=″
N4'''H'' + N3'''L'' because of H''.This potential difference is increased by the free lag frog consisting of MO8F'E'r Qt s +Qt a, and at the same time the iCM
OSFET Ql91Q20 transfers the state of node N3 +N4 to node N5eN6. N4@H”.

Since N3 is "L", %t) SFET (h 9 is non-conductive, Q20 is conductive, node Ns remains "H", and becomes L# from node N6-IH#. Nodes N5 and wN6 are respectively Qt s IQI Since they are connected to the gates of 7 and 7, when the node N6'''L'' becomes ■5FETQ1
This reduces the conductance of N3 and increases the level difference between N3"L" and N4"H". Due to the above feedback system, N3*Ns becomes "L" level and N
4 + N5 becomes ``H''.

When the next VC clock No. 4m φ4 changes from "L" to I(", Ns J6 is "H" and "L" respectively, so M) SF wire Q26 is conductive, and Q27 is non-conductive, so it goes to Aout. The level of φ4 is transferred, and Aout is
f(", MOSFET Q 1s becomes conductive, Aous becomes @L#, and the address signal Aout"
H', Aout''L# are output.

Reference potential Vrof is generated by reference potential generation circuit 601.

This reference potential generation circuit 601 is composed of a resistance divider circuit using resistors R3+R4 made of polysilicon film,
Also, it takes a long time to input Vre to each address buffer.
There is fAJ wiring, and there is large capacitive coupling between it and the semiconductor substrate. This value is generally larger than the capacitance between interconnects. Therefore, in a conventional circuit using a substrate bias generation circuit, there is a problem in that the IC VBB fluctuates during charging and discharging of the pin D, which causes fluctuations in Vref and causes a malfunction of the address buffer circuit with a small margin. Ta. This appears as a malfunction of the Ain input for specifying column addresses and row addresses after bit line charging and discharging.

However, in the present invention, *VBB is Vi, which has a large power supply capacity.
This problem can be greatly improved by using ``sext'' as VnB. -Also, when charging and discharging the bit line.

There is also the problem that Vcc and Vss fluctuate due to the excessive current, but as shown in the f2Wt diagram and Figure 6, there is a large current in the power supply 8. D i Chemotaxis: /i is significantly produced.

In addition, since the L source voltage changing circuit, including the substrate bias, is set in one system, the internal circuit 109, including the address buffer circuit itself, is sensitive to noise.

2 in FIG. 1, 602 is Ain's signal human power pad. Incidentally, the reference 4th position generating circuit 601 may be replaced by a MOSFET as shown in Fig. 5.

As explained above, according to the present invention, it is possible to improve device breakdown voltage and reliability, downsize the power supply circuit, reduce power consumption, and significantly improve chip noise malfunction. It is something that can be done.

Other aspects of the invention are not limited to the above embodiments, and can be implemented with various modifications.

[Brief explanation of drawings]

=a The figure is a system block diagram showing an actual example of the present invention, Figure 2 is a block diagram of the source power supply, t+, and pressure conversion circuit, Figures 3 and 41 are block diagrams, and Figure 5 is its circuit diagram. FIG. 6 is a circuit diagram of the address buffer circuit, and FIG. 7 is a timing chart of its operation. In the figure, 105... external power supply, 115... source voltage conversion circuit, 109... internal circuit. Agent Patent Attorney Noriyuki Ken Yudo Takehana Bank Hisao No.1 Figure No.11 Town No.7

Claims (5)

[Claims] (1) The high potential of the external power supply is used as the drain power supply voltage of the internal circuits of the chip, and the low potential of the external power supply is used as the substrate bias, and the low potential is boosted within the chip via the power supply voltage conversion circuit to boost the internal circuits. 1. A MOS integrated circuit characterized in that the source voltage is supplied as a source power supply voltage. (2) The MOS integrated circuit according to claim 1, which is a dynamic RAM chip. (3) The MOS integrated circuit according to claim 1, wherein the external power supplies are 5V and 0V, respectively, and the output of the power supply voltage conversion circuit is 2V. (4) The MOS integrated circuit according to claim 1 or 2, characterized in that it comprises an address buffer circuit. (5) The MOS integrated circuit according to claim 4, wherein the reference potential of the address buffer circuit is obtained by dividing the power supply voltage of an external power supply.