JPS6383994A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the malfunction of level discriminating means accompanied with the variance of a substrate bias potential by generating such variable reference potential that two level discriminating means are normally operated at each time when an external signal is taken in at different times and is compared with the reference potential. CONSTITUTION:A reference potential VREF used for level comparison in address buffers 10 and 20 is supplied from a reference potential generating circuit 30 provided commonly for both address buffers 10 and 20. The reference potential generating circuit 30 sets the reference potential VREF so that the value of this reference potential is different between the time when the row address buffer 10 takes in an external address input signal AINC and compares it wit the reference potential and the time when the column address buffer 20 takes in an external address input signal AINR and compares it with the reference potential. Thus, the reference potential VREF set to an optimum value is used to discriminate the level of the external address input signal when the row address buffer 10 is operated, and the occurrence of malfunction is prevented.

Description

[Detailed Description of the Invention] [Objective of the Invention (Industrial Application Field) The present invention is directed to a reference potential generation circuit, and is capable of generating an external signal by comparing an external signal with a reference potential obtained by this circuit. The present invention relates to a semiconductor integrated circuit that determines the logic level of a semiconductor device and incorporates the result into the semiconductor integrated circuit.

(Prior Art) In recent years, semiconductor integrated circuits have rapidly become highly integrated due to miniaturization of elements, and as a result, transient currents during operation tend to increase. In particular, in semiconductor memories, chip sizes are becoming increasingly longer than before due to restrictions on package dimensions.

As a result, the width of the power supply wiring inside the chip becomes thinner and longer (and the impedance component inside the chip tends to increase).

The miniaturization of such elements, the increase in transient current during operation, and the increase in impedance components inside the chip are having a significant impact on the operation of circuits including sense amplifiers, such as semiconductor memories. For example, the problems of a dynamic RAM (hereinafter referred to as DRAM) having a storage capacity of 1 Mbit will be specifically explained. Now, 1
It is assumed that 128 memory cells are connected to one bit line and the chip adopts a divided operation type. This split operation type is designed to reduce peak current and current consumption during access.
This method divides the memory cell array into multiple regions and operates only the memory cell array region selected at the time of access. For example, in a chip with 4 array configuration, 2 of them are
Control is performed such that array areas are selectively activated. In the case of a 1M bit DRAM, the number of bit line zero failures is 819 out of 4096 pairs, excluding redundant bit lines.
There are two bit lines, but half of them, 4096 bit lines of 2048 pairs, do not operate at all due to the split operation method, and the remaining half of the 4096 bit lines that operate are charged during precharging.
Further, when active, half of the 4096 bit lines, ie, 2048 bit lines, are discharged based on data read from the memory cells.

By the way, memories such as DRAMs are integrated on semiconductor substrates, and in order to stabilize the threshold voltage of MOS transistors formed within the substrate, a predetermined bias voltage is usually applied to the substrate. There is. Such an effect is generally known as a substrate bias effect.

Incidentally, the substrate on which the DRAM is integrated has junction capacitance between the power supply voltage, the ground voltage, and the diffusion layer of the bit line. Therefore, the substrate bias potential also fluctuates in response to changes in the potential of the bit line that is charged and discharged during operation. In general, the capacitive coupling ratio rb(
The bootstrap ratio (commonly referred to as the bootstrap ratio) is approximately 0.14 culm.

Therefore, the bit line potential changes from the ground voltage VSS to the power supply voltage VSS.
The variation ±ΔVSUB in the substrate potential VSUB when changing to CC or from the power supply voltage VCC to the ground voltage VSS is:
When VCC is 5V and VSS is OV, it is given by the following equation.

±Δvs U B ””±(Vcc Vss)Xrb
-±5X0. 14 1±0. 7 (V)...1 On the other hand, in address buffers, data-in buffers, etc. in DRAMs composed of MOS transistors, it is necessary to convert externally input TTL level data to MOS level data for internal use. Therefore, MOS
- In a DRAM configured with transistors, a level comparison circuit is provided at the first stage of these address buffers, data-in buffers, etc. In these level comparison circuits, the base or potential used for level comparison is generated by a reference potential generation circuit. Furthermore, in this reference potential generation circuit, these reference potentials are generally formed by resistance division using a number of stages of resistors made of polycrystalline silicon.

FIG. 5 is a circuit diagram showing the configuration of a portion of a DRAM, showing the reference potential generation circuit used in the DRAM together with an address buffer, a data in buffer, and the like.

In the reference potential generation circuit 60, a plurality of resistors 61 each made of polycrystalline silicon are connected in series between the node of the voltage rl+X voltage VCC and the node of the ground voltage VSS. A parasitic capacitance 63 is selectively connected between each series connection point of these resistors and the substrate 62. The reference potential VR generated by this reference potential generation circuit 60
The EF is supplied to an address buffer 80, a data in buffer 100, etc. via a wiring 70 made of aluminum or the like. The address buffer 80 and the data-in buffer 100 include MOS1-transistors 81 to 84, as exemplified by one address buffer 80, a flip-flop circuit 85 for comparing a pair of potentials, and a control signal for this flip-flop circuit 85. External address input signal AIN is synchronized with φ.
Two MOS transistors 8B that input and supply
, 87, and similarly, the flip-flop circuit 85 is manually supplied with the reference potentials v, , E F in synchronization with the Hil control signal 2
The circuit includes a switch circuit 91 formed of MOS transistors 89 and 90, a buffer circuit 92 for holding the comparison result of the flip-flop circuit 85, and the like.

Here, a parasitic resistor 71 is also connected in series to the wiring 70, and parasitic capacitors -72, 73, and 74 are also connected between the power supply voltage Vcc, the ground voltage VSS, and the substrate 62, respectively. Therefore, a capacitive coupling ratio also exists between the reference potential generation circuit 60 and the substrate 62, and this value is approximately 0.5.
It is about 8 Ji. Therefore, when the substrate bias potential VSUB applied to the substrate 62 changes, the reference potential vRε
F also varies, and the variation ΔvRE F is as follows.

ΔvRεF =0. 58'X (±0°7)-±0.
41 (V) ... 2 That is, when the bit line potential changes due to charging, discharging, etc., the substrate bias potential vs. changes.

A typical reference potential variation is ±0.41 (V).

FIG. 6 is a waveform diagram showing the relationship between the row address strobe signal RAS and column address strobe signal CAS, which are external input signals in the DRAM, and the L substrate bias potential VSUB and the reference potential ~'REF. When the signal RAS falls to the "L" level and becomes active, the bit line is then discharged. Due to this discharge of the bit line, the substrate bias potential VSUB, which was previously -3V, drops to -3.7V, for example. With this potential drop, for example, the reference potential v, which was previously 1.6
RεF drops to 1.19V.

After this, the reference potential VREF changes from 1°19V to the original value due to the influence of the parasitic resistance 71 and the parasitic capacitance 2.73.74 which exist in the middle of the wiring 70 in FIG. Return to 1.6V. However, the substrate bias potential vsua
does not return to its original level of 13V unless minority carriers are injected into the substrate and subjected to capacitive coupling due to charging and discharging of the bit line.

On the contrary, when the signal RAS rises to the "H" level and becomes inactive, precharging of the bit line is then started. With this charging, until now -3.7■
The substrate bias potential VSUB, which had been 1.6V, rises again to -3V, and in conjunction with this, the reference potential VREF, which has been 1.6V, rises to 2.01V.

Thereafter, the reference potential vRεF is set to 2. Return from OIV to the original 1.6V.

When the bit line potential changes in this way, the reference potential vRεF
As a result, in the circuit shown in FIG. 5, malfunctions occur in the logic level judgment operation of external signals in the address buffer 80, data-in buffer 100, etc.

Figure 7 shows the elapsed time T from the fall of the signal RAS.
(nS) and the reference potential vRεF (V).゛Depending on the value of the hair source voltage VCC, it takes 30 (nS) to 40 seconds from the fall of the signal RAS.
(nS), the sense amplifier connected to the bit line operates, the bit is discharged, and the value of the reference potential VREF decreases. If the column address buffer operates when the value of the reference potential VREF decreases, the margin for determining the logical "L" level of the column address human input signal from the outside decreases, causing the column address buffer to malfunction. This is because the external address human input signal AIH's logic "L" standard VIL -I is determined to be within 0.8V, and the values of the reference potentials VRF and F, including variations in the sense amplifier, are If the voltage drops below 0.8V, it will malfunction.

Figure 8 shows the elapsed time T from the rise of the signal RAS.
FIG. 3 is a characteristic diagram showing the relationship between (nS) and radical $71 position VREF (V). In this case as well, charging of the bit line starts, depending on the value of the power supply voltage VCC, or about 40 (ns) after the rise of the signal RAS, and the value of the reference potential VREF increases by 4. Therefore, the next active cycle starts while the reference potential VREF is rising, and for example, about 70 (nS
), when the signal RAS falls and the row address buffer starts operating, the margin for determining the logic "H" level of the row address input signal from the outside decreases, causing the row address buffer to malfunction. This is the standard VIH of the logic “H” of the external address human input signal AIH, or 2.4■ to 6
．． This is because the range is determined to be 5V, and the reference potential v
The value of RεF is 2.4■ including the variation of the sense amplifier.
If it increases by 1 or more, it will malfunction.

(Problem to be solved by the invention) As described above, it has a reference potential generation circuit, and by comparing the external signal with the base Q potential obtained by this circuit, the logical level of the external signal is determined and taken into the internal. In conventional semiconductor integrated circuits, the reference potential is set to one value, so as the substrate bias potential fluctuates, a certain circuit may malfunction due to a drop in the reference potential at one time, and the reference potential may malfunction at another time. There is a problem that one circuit cage operates due to a rise in potential.

This invention was made in consideration of the above-mentioned circumstances, and its purpose is to provide a semiconductor integrated circuit that can prevent malfunctions of circuits that use the base and potential formed in the base potential generation circuit. It is about providing.

[Structure of the Invention] (Means and Effects for Solving the Problems) The semiconductor integrated circuit of the present invention takes in an external signal at at least two different times, compares it with a reference potential, and determines the logic level of the external signal at that time. and a reference potential generating means that generates a reference potential having a different value at 1-marking time and supplies it to the 1-marking level judging means. According to the present invention, by generating reference potentials having different values such that the two level determining means operate normally at each time, malfunction of the level determining means due to fluctuations in the substrate bias potential is prevented.

Further, the semiconductor integrated circuit of the present invention includes a plurality of level determination means for taking in an external signal and comparing it with a reference potential to determine the logic level of the external signal at that time, and corresponding to each of the plurality of level determination means. and a plurality of reference potential generation means for supplying independently set reference potentials to the respective level determination means. According to this invention, by setting the base/$ potential generated by each reference potential generating means to a value that allows each level determining means to operate normally, each level determining means is adjusted as the base bias potential changes. Malfunctions are prevented.

(Example) Hereinafter, the present invention will be explained with reference to drawings of embodiments.

FIG. 1 is a block diagram showing the configuration of a circuit according to an embodiment of the present invention.

In the figure, IO is a row address buffer in a DRAM, for example, and 20 is a column address buffer. Each of these address buffers 10 and 20 is composed of a flip-flop circuit, a switch circuit, a buffer circuit, etc., similarly to the one shown in FIG.
By comparing with F, for example, the logic of the external address manual signal AIN input at the TTL level is determined,
It is converted to the MOS transistor level and held in the buffer circuit.

The reference potential vREF used for level comparison in both address buffers 10.20 is supplied from a reference potential generation circuit 30 provided in common to both address buffers 10.20. This reference potential generation circuit 30 is also basically similar to the one shown in FIG. The reference potential vREF is generated by dividing the voltage by resistance, and in this reference potential generation circuit 30,
The reference potential VREF is determined by the time when the row address buffer 10 takes in the external address input signal AINC and compares it with the reference potential, and the time when the column address buffer 20 takes in the external address input signal AINR and compares it with the reference potential. are set to different values. For example, conventionally, the value of VRF, F is the specified value VII (and 1
It is set to a value Vo1, that is, Vo-1/2 (VI H-VI L), which is exactly between the specified value VIL of λ principle "L".However, in this embodiment, 1J and potential generation In the case of the circuit 30, as shown in the waveform diagram of FIG. 2, there is a time T1 when the row address buffer 10 takes in the external address cuff No. 5 AINR and compares it with the reference potential.
In the vicinity, a potential lower than Vo above by Δ■ is set as the reference potential v
generated as RεF and column address buffer 20
Near time T2 when the external address input signal AINC is taken in and compared with the reference potential, a potential higher than the above-mentioned VO by ΔV is generated as the reference potential VREF. Note that the external address input signals are taken into the address buffers 10 and 20 based on the row address strobe signal RAS and the column address strobe signal CAS, as in the conventional case.

Here, as shown in FIG. 8, the reference potential VRE
The value of F is approximately 40 (nS) from the rise and fall of the signal RAS.
) has passed, it becomes about 2.01V, which is 1 in the steady state.
．． It increases by about 0.41V from 6V. ``-H'' of this reference potential VREF coincides with the operation start time of the row address buffer. Therefore, near time T1, the reference potential vRBF is set to a potential that is Δ■ lower than Vo, and the value of ΔV is set to 0.41 V, which is the increase in the reference potential caused by the fluctuation of the substrate bias potential. If this is done, the actual value of the reference potential VREF in consideration of the fluctuation of the substrate bias potential will match Vo. Therefore, when the row address buffer 10 operates, it is possible to judge the level of the external address input signal using the reference potential VREF set to the optimum value. This prevents malfunctions from occurring in the logic level determination operation in the address buffer.

On the other hand, as shown in FIG. 7, the observation potential vRεF
The value becomes about 1.19V when approximately 30 (nS) to 40 (nS) have elapsed since the fall of the signal RAS, which is 0.41V lower than the steady state of 1.6V. This decrease in the reference potential VREF coincides with the operation start time of the column address buffer. Therefore, around this time T2, the reference potential VRE F becomes ΔV with respect to Vo.
If the value of ΔV is set to 0°41V, which corresponds to the decrease in the reference potential due to fluctuations in the substrate bias potential, the actual reference potential VREFO value that takes into account fluctuations in the substrate bias potential is V.

matches. Therefore, when the column address buffer 20 operates, the reference potential vRε is set to the optimum value.
F can be used to determine the level of an external address input signal, thereby increasing the margin for determination than in the past and preventing malfunctions in logic level determination operations in column address buffers.

As described above, according to the embodiment described above, a reference potential is generated for a plurality of circuits, such as the row address buffer lO and the column address buffer 20, which compare the external address manual signal with the base potential and make a logical judgment. A circuit 30 is provided in common, and the value of the reference potential generated by the reference potential generation circuit 30 is transmitted to the row address buffer IO and the column address buffer 2.
Since the times at which the level comparison is performed at 0 are set to be different, it is possible to prevent the row address buffer 10 and the column address buffer 20 from malfunctioning when determining the logic level.

In the above embodiment, the circuit using the reference potential generated by the reference potential generation circuit 30 or the row address buffer 1
0 and the column address buffer 20, but it may also be supplied to two or more circuits, and if these circuits perform level comparisons at different times, may be set so that the value of the reference potential is different for each time.

FIG. 3 is a block diagram showing the configuration of a circuit according to another embodiment of the invention. In the figure, IO is a row address buffer, and 20 is a column address buffer.

The reference potential VREF used for level comparison in both address buffers 10.20 is supplied from uQ'l-1i position generation circuits 40.50 provided corresponding to both address buffers 10.20. Ru.

One of the reference potential generation circuits 40 has a plurality of resistors made of polycrystalline silicon connected in series, and has a power supply voltage VCC and a ground voltage VSS, similar to the one shown in FIG.
By dividing the voltage between the reference potential VR and
E F R is formed, and its value is Δ smaller than the value Vo, which is exactly between the specified value VEH of the logic “H#” and the specified value VIL of the logic “L” of the external address input signal AIN.
Only V is lowered. The other reference potential generation circuit 50 is also configured similarly to that shown in FIG. 5, and the value of the reference potential VREFC is determined by the external address input signal AI.
The specified value VIH of logic “H” and the specified value V of logic “L’”
It is set higher than the value VO, which is exactly in the middle with IL, by Δ■. That is, the values of the reference potential generation circuits 40 and 50 are set independently from each other.

In this embodiment circuit, when the row address buffer 10 starts operating at time T1 in the waveform diagram of FIG. 4, the reference potential changes from the steady state of 1.6 to 0.1 due to the fluctuation of the substrate bias potential as described above. It increases by about 41V. However, the quasi-potential VREFR formed by the reference potential generation circuit 40 is V.

The potential is always set to ΔV lower than that of ΔV.
If the value of V is set to 0.41 V, which corresponds to the increase in the reference potential due to the variation in the substrate bias potential, the actual reference potential VR takes into account the variation in the substrate bias potential at time T1.
The value of E F R matches Vo. Therefore, when the row address buffer 710 operates, the level of the external address manual signal can be determined using the observation potential VRεF set to the optimum value. This prevents malfunctions from occurring in logic level determination operations in the address buffer.

Similarly, the reference potential vREFC generated by the reference potential generation circuit 50 is always set to a potential higher than Vo by ΔV, and the value of this ΔV is set as the reference potential due to fluctuations in the substrate bias potential. If the decrease is set to 0.41V, the actual values of the reference potentials VRE and FC, taking into account the fluctuation of the substrate bias potential at time T2, will match Vo. Therefore, when the column address buffer 20 operates, the reference potential vREF set to the optimum value is
C can be used to determine the level of the external address input signal, thereby increasing the margin for determination than in the past, and preventing malfunctions during logic level determination in the column address buffer. Note that the solid line in FIG. 4 shows the change in reference potential in the conventional circuit.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a semiconductor integrated circuit that can prevent malfunctions of a circuit that uses a reference potential formed by a base potential generation circuit. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a circuit according to an embodiment of the present invention, FIG. 2 is a waveform diagram of the circuit according to the above embodiment, and FIG. Figure 4 is a waveform diagram of the embodiment circuit shown in Figure 3 above, Figure 5 is a circuit diagram showing a part of the configuration of the DRAM, Figure 6 is a waveform diagram of various signals in the DRAM, and Figures 7 and 8 are Each DRA
It is a characteristic diagram in M. 10... Row address buffer, 20... Column address buffer, 30.40.5G... Reference potential generation circuit. Applicant's representative Patent attorney Takehiko Suzutsuta Figure 1 Figure 3 Figure 5 Figure 6

Claims (1)

[Scope of Claims] 1. At least two level determination means that captures an external signal at at least two different times and compares it with a reference potential to determine the logic level of the external signal at that time, and the value is different at each of the times. 1. A semiconductor integrated circuit comprising: reference potential generating means for generating a reference potential and supplying it in parallel to each of the level determining means. 2. A plurality of level judgment means that take in an external signal and compare it with a reference potential to judge the logic level of the external signal at that time, and a plurality of level judgment means provided corresponding to each of the plurality of level judgment means and set independently. 1. A semiconductor integrated circuit comprising a plurality of reference potential generation means for supplying a reference potential to each level determination means. 3. The semiconductor integrated circuit according to claim 1, wherein the level determining means is any one of a row address buffer, a column address buffer, and a data-in buffer.