JPH0334251B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a MOS type switch circuit in a MOS (insulated gate type) integrated circuit, and particularly to a circuit for switching signals in a wide voltage range.

[Technical background of the invention]

Usually, the substrate of a MOS transistor formed in a bulk semiconductor has a PN connection between the source and drain.
The junction is biased so that it is not forward biased. For example, in the case of an N-channel MOS transistor, the source and drain are of N ⁺ type, so the P-type substrate or P ^- well is biased to the lowest power supply potential or source side potential.

[Problems with background technology]

By the way, in the case of a MOS transistor used in a circuit in which the relationship between the potential levels between the source and the drain is reversed, the potential of the substrate cannot be directly connected to the source side. In addition, in MOS integrated circuits, signals that exceed the voltage range of the circuit power supply that is regularly applied (for example, N-channel MOS
In the case of , a signal with a potential lower than the lowest potential of the circuit power supply that is constantly applied. ) is applied to the source or drain of the transistor, then
The substrate bias becomes higher, resulting in a forward bias between the source and the substrate or between the drain and the substrate, causing a large current to flow, making it impossible to obtain normal operation.
Here, a conventional MOS type switch circuit in a MOS integrated circuit will be explained with reference to FIG. In this switch circuit, 1 and 2 are each N
It is a channel enhancement type transistor, and its sources are connected to each other to form an output node.The drain of transistor 2 is constantly supplied with a power supply voltage V ₁ (for example, 5V), and the drain of transistor 1 is connected to the output node. is given a high voltage signal V ₂ (eg 20V) from outside the integrated circuit. The switch circuit is for switching and selecting the V ₁ and V ₂ and outputting it to the output node 3, and complementary control signals V _H and V _L are applied to the gates of the transistors 1 and 2. . in this case,
Substrate potential V _SUB is the lowest potential of the circuit power supply
It is biased to GND (0V), and even if _V2 , which has a higher potential than _V1 , is applied to the drain of transistor 1, forward bias will not occur between the drain and the substrate. By the way, when selecting V ₂ by switching, V _L is set to 0 V and V _H is set to a high potential as control signals to make transistor 1 conductive. ₁₂ becomes lower than the potential of _VH by the threshold voltage _VTHl of transistor 1. Therefore, there is a drawback that the potential of V _H generally needs to be boosted to a voltage sufficiently higher than V ₂ +V _TH using a booster circuit with a complicated configuration. Furthermore, the same thing can be said about the case where _V1 is selected by switching. That is, in order to make transistor 2 conductive, V _H is set to 0 V and V _L is set to a high potential, but the high potential of V _L must be boosted to a voltage that is sufficiently higher than V ₁ + V _TH2 (V _TH2 is the threshold voltage of transistor 2). It is necessary to supply the voltage constantly by the circuit or to use a depletion (D) type transistor whose threshold voltage V _TH2 is negative as the transistor 2. However, when a D-type MOS transistor is used, the manufacturing process becomes complicated. Therefore, even if a P-channel MOS transistor is used so as not to take the source follower format, the potential V ₁₂ of the output node 3 will be higher or lower than V ₁ and V ₂ , so the connection between the substrate, drain, and source will be The junction becomes forward biased. In this case, with an SOS structure, that is, an element in which a MOS transistor is formed on a semiconductor layer isolated in an island shape on a sapphire substrate, no problem occurs even if the forward bias is applied as described above, but SOS is extremely The cost will be higher. On the other hand, in a normal integrated circuit, a MOS transistor has a source and a drain formed on the surface of a semiconductor substrate, but the source and drain are formed in a well formed on the surface of the semiconductor substrate and has a conductivity type opposite to that of the substrate.
It forms the drain, and in any case, problems will occur if the junction between the source or drain and the substrate becomes forward biased. In other words, when a source or drain is formed in a semiconductor substrate, the semiconductor substrate is usually fixed at a specific potential, and if the junction becomes forward biased, the potential of the source or drain becomes immobile. . In addition, when a source and drain are formed in a well, a parasitic bipolar transistor based on the well region is activated, and the potential of the source and drain is fixed, or in the case of a MOS switch circuit in a CMOS integrated circuit. A malfunction (latch-up) occurs in which the parasitic thyristor becomes conductive.

[Purpose of the invention]

The present invention was made in view of the above circumstances, and
between two nodes including a node whose potential is higher or lower than the circuit power supply voltage of the MOS integrated circuit.
MOS transistors enable high-speed switching without malfunction, and the manufacturing process is not complicated, and there is no need for a boost circuit for the switching control signal, making it easy to implement.
It provides a MOS type switch circuit.

[Summary of the invention]

That is, the MOS type switch circuit of the present invention is a MOS type switch circuit.
A well is formed in a semiconductor substrate of an integrated circuit, and first to third substrates each having the same conductivity type but not a depletion type, each having the well as a common substrate area.
A MOS transistor is formed, one end of each of the second and third transistors is connected to the well, and the other end of the second transistor has a potential equal to or higher than the potential _{V a} applied to one end of the first transistor. A bias potential is applied to the other end of the third transistor, and the potential applied to the other end of the first transistor is applied to the other end of the third transistor.
Apply a bias potential equal to or higher than V _b ,
A control signal is applied to the gates of the second and third transistors to make the second and third transistors conductive or non-conductive in a complementary manner depending on the level relationship between the two potentials V _a and V _b . It is configured.

Thereby, even if the potential V _a or V _b is higher than the power supply voltage regularly applied to the integrated circuit, the substrate region of the first transistor is
Since the potential lower than either of the potentials V _a and V _b does not reach through the conductive transistor of the third transistor, the junction between the substrate region and the source and drain of the first transistor does not become conductive. Normal switching operation becomes possible. In this case, the circuit configuration becomes very simple because the conventionally required complex booster circuit (usually 40 to 50 MOS transistors are required) can be omitted. Furthermore, since no depletion type transistor is used, the manufacturing process does not become complicated. Moreover, since the MOS type switch circuit is a source-grounded type circuit, the speed of voltage step-up and step-down by switching operation is extremely fast.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

Figure 2 shows a MOS type switch circuit for switching between two nodes, including a node whose potential may be higher than the power supply voltage normally applied in a MOS integrated circuit. , P ₁ to _{P 3} are P-channel enhancement type first to third MOS transistors, and each substrate region is a well (an N-type well in this example) in a MOS integrated circuit semiconductor substrate.
It is formed by first transistor P ₁
are connected in series between the first node 4 and the second node 5 and used for switching, and the second and third transistors P ₂ and P ₃ are connected to the substrate of the switching transistor P _1. Used to determine the bias potential of a region.

V _a is the voltage applied to the first node 4, V _b is the voltage applied to the second node 5, and the maximum value of the voltage V _a or a bias voltage V ₂ equal to V _a is applied to the node 6. and the voltage V _b is applied to node 7.
A bias voltage V ₃ equal to the maximum value of or V _b is applied. Transistors P ₂ and P ₃ are connected in series between the nodes 6 and 7, and a connection point 8 between the drains of the transistors P ₂ and P ₃ is connected to the substrate region of each of the transistors P ₁ to _{P 3} . ing.

The transistors P ₂ and P ₃ are connected to the nodes 4 and 5.
It is controlled by the relationship between the voltages V _a and V _b , and when V _a ≧ V _b , transistor P ₂ is conductive and transistor P ₃ is non-conductive; conversely, when V _a <
When _the voltage is V _b , transistor P ₂ is non-conductive and transistor P ₃ is conductive.
A complementary control signal is applied to the gate of _P3 .
By this, P channel transistor P ₂ ,
The potential at the interconnection point 8 of _P3 is equal to the higher potential of V _a or V _b , and the substrate region of switching transistor P ₁ does not have a potential lower than either V _a or V _b . , the junction between the substrate region and the source and drain of the switching transistor _P1 is never reverse biased. Therefore, the switching transistor _P1 can perform a normal switching operation in response to the switching control signal applied to its gate. Further, since the junction between the well, which is the substrate region, and the integrated circuit semiconductor substrate is reverse biased, the well can have a potential independent of that of the semiconductor substrate.

Note that the circuit for generating complementary control signals for the transistors P ₂ and P ₃ detects the polarity of the potential difference between V _a and V _b applied to the nodes 4 and 5, and performs the above control signal according to the detection result. The configuration may be such that the level relationship between the potentials of the control signals is determined.

According to the MOS type switch circuit as described above,
Forming a well in the semiconductor substrate of a MOS integrated circuit,
The first to third substrates, each of the same conductivity type and non-depletion type, use this well as a common substrate area.
A MOS transistor is formed, one end of each of the second and third transistors is connected to the well, and the other end of the second transistor has a potential equal to or higher than the potential _{V a} applied to one end of the first transistor. A bias potential is applied to the other end of the third transistor, and the potential applied to the other end of the first transistor is applied to the other end of the third transistor.
Apply a bias potential equal to or higher than V _b ,
A control signal is applied to the gates of the second and third transistors to make the second and third transistors conductive or non-conductive in a complementary manner depending on the level relationship between the two potentials V _a and V _b . It is configured.

Thereby, even if the potential V _a or V _b is higher than the power supply voltage regularly applied to the integrated circuit, the substrate region of the first transistor is
Since the potential lower than either of the potentials V _a and V _b does not reach through the conductive transistor of the third transistor, the junction between the substrate region and the source and drain of the first transistor does not become conductive. Normal switching operation becomes possible. In this case, the circuit configuration becomes very simple because the conventionally required complicated booster circuit (usually 40 to 50 MOS transistors are required) can be omitted. Furthermore, since no depletion type transistor is used, the manufacturing process does not become complicated. Moreover, since the MOS type switch circuit is a source-grounded type circuit, the speed of voltage step-up and step-down by switching operation is extremely fast.

Note that the above embodiment uses a P-channel transistor, but when using an N-channel transistor, the drains of the second and third transistors are connected to the substrate region, and the source of the second transistor is connected to the first node. A bias voltage equal to or lower than the voltage V _a is applied to the source of the third transistor, a bias voltage equal to or lower than the voltage V _b at the second node is applied to the source of the third transistor, and when V _a <V _b , the second and third transistors The gates of the second and third transistors are made conductive and non-conductive, respectively, and the gates of the second and third transistors are made non-conductive and conductive, respectively, when V _a > V _b . A complementary control signal may be applied to the first transistor so that the potential of the substrate region of the first transistor does not become higher than either of the potentials V _a and V _b .

FIG. 3 shows a MOS type switch in which nodes 6 and 7 are respectively connected to nodes 4 and 5 in the circuit of FIG. 2, and the gates of transistors P ₂ and P ₃ are connected to the substrate region. Shows the circuit.
In this circuit, the above transistors P ₂ and P ₃
The potential of the interconnection point 8, i.e. the potential of the substrate area
V _s is lower than the higher potential of V _a or V _b by the threshold voltage of transistor P ₂ or P ₃ ,
The junction between the source or drain of the switching transistor _P1 and the substrate region is forward biased only up to the threshold voltage. Therefore, the absolute value of the threshold voltage of the transistors P ₂ and P ₃ is
Voltage at which the junction between the source or drain of switching transistor _P1 and the substrate region becomes conductive
If it is made smaller than V _F , the above-mentioned problem due to forward bias will not occur.

FIG. 4 shows nodes 6 and 7 in the circuit of FIG.
A MOS type switch circuit is shown in which the transistors P2 and P3 are connected to nodes 4 and 5, respectively, the gate of transistor _P2 is connected to node 5, and the gate of transistor _P3 is connected to node 4. Note that Ca is a stray capacitance between the node 4 and the substrate region, and Cb is a stray capacitance between the node 5 and the substrate region.

Next, the operation of the circuit shown in FIG. 4 will be explained. As shown in FIG. 5a, the voltage V _a at node 4
Let us consider the case where the voltage V _b at node 5 changes from a voltage sufficiently higher than V _a to a voltage sufficiently lower than V a while keeping V a constant. Before time t ₁ , V _b − | V _TP2 | ≧
V _a (where |V _TP2 | is the absolute value of the threshold voltage of transistor P ₂ ), and transistor P ₂ is non-conducting,
Since transistor P ₃ is conductive, the potential V _s of the substrate region of transistor P ₁ is equal to V _b . From time t ₁ to _{t 2} , V _b − | V _TP2 | < V _a < V _b + | V _TP3
| (However, |V _TP3 | is the absolute value of the threshold voltage of transistor P _3. ) Both transistors P ₂ and P ₃ become non-conductive, and the potential V _s of the substrate region decreases due to the effects of stray capacitances Ca and Cb. It goes down as shown by the dotted line at a slower speed than V _b . After time _t2 , V _a ≧V _b +
|V _TP3 |, transistor P ₂ is conductive and transistor P ₃ is non-conductive, so the potential V _s of the substrate region becomes equal to V _a . In this way, the potential V _s in the substrate region is never lower than either V _a or V _b and the aforementioned forward bias problem in transistor P ₁ does not occur.

On the other hand, as shown in FIG. 5b, the voltage V _a at node 4 is kept constant and the voltage V _b at node 5 is
Let us consider the case where the voltage changes from a voltage sufficiently lower than V _a to a voltage sufficiently higher. Before time t ₁ , V _a
≧V _b + | V _TP2 | and transistor P ₂ is conductive,
Since the transistor P ₃ is non-conductive, the potential V _s in the substrate region becomes equal to V _a . At time _t1 to _t2 ,
V _b + | V _TP2 | > V _a > V _b − | V _TP3 | and transistors P ₂ and P ₃ are both non-conductive, so Ca,
Due to the capacitance division of Cb, the potential V _s in the substrate region rises at a slower rate than V _b as shown by the dotted line in the figure. In this case, if CaCb is used, the rising speed of the potential V _s in the substrate region is approximately 1/2 of the rising speed of V _b , so V _s
It can never be lower than V _b . On the other hand, Ca
<Cb, the rising speed of the above potential V _s is 1/2 of the above
V _s < V _b , V _s between times t ₁ and t ₂
V _b changes in the order of V _s < V _b , and at time t ₂ the potential difference between V _s and V _b is the largest, but this potential difference causes the junction between the source or drain of transistor P ₁ and the substrate region to become conductive. If the values of Ca and Cb are set so that they are lower than the voltage V _F , the transistor
The problem of forward bias in P ₁ does not arise. time t ₂
After that, V _b + | V _TP3 | ≧ V _a and the transistor
Since P ₂ is non-conductive and transistor P ₃ is conductive,
The potential V _s of the substrate region becomes equal to V _b . In this way, _the potential _{V s} of _the substrate region is set _as
It never becomes lower than either V _a or V _b , and even when V _s < V _b , the potential difference between V _b and V _s is kept lower than V _F as described above. ,
The aforementioned forward bias problem in transistor _P1 does not occur.

FIG. 6 shows the structure of the transistor of the MOS type switch circuit of FIG. 4 formed in a MOS integrated circuit, in which an N-type well 62 is formed on a P-type semiconductor substrate 61, and P ⁺ type diffusion layers 63, 64, 65, 66 are formed in the well 62, and N ⁺ type diffusion regions 67, 6 are formed as electrode regions of the well 62.
8 is formed. 69 is a gate oxide film, 70,
71 and 72 are gate electrodes, and gate electrode 70
and the diffusion layer 65 are connected to the node 5 in FIG. 4, and the gate electrode 72 and the diffusion layer 64 are connected to the node 4 in FIG.
and the diffusion region 67 are connected, and the diffusion layer 66 and the diffusion region 68 are connected. That is, the diffusion layer 6
4, 65 and the gate electrode 71 form the transistor _P1 of FIG. 4, and the region of the diffusion layers 63, 64 and the gate electrode 70 form the transistor P1 of FIG.
P ₂ is formed, diffusion layers 65 and 66 and gate electrode 7 are formed.
2 forms the transistor _P3 of FIG. Due to the structure described above, the area occupied by the MOS type switch circuit is extremely small.

Figure 7 shows an example of a voltage switching circuit for selecting two types of power supply voltage by applying the MOS type switch circuit of Figure 4.
Applicable to type EPROM (Electrically Programmable Sword Only Memory). That is, in FIG. 7, S ₁ and S ₂ are respectively switch circuits as described above with reference to FIG.
Voltage V _PP is applied to node 5 of S ₁ and voltage V _CC is applied to node 5 of switch circuit S ₂ . The above voltage V _CC is 5V, which is the power supply voltage during normal reading or standby, and the above voltage V _PP is
It is approximately 20V during program operation to write data to PROM, and 0 to 5V at other times.
During a read operation, the switch circuit _S2 is turned on because 0V is applied as a control signal to the gate of the transistor _P1 , and V _CC (5V) of the node 5 is supplied. At this time, in the switch circuit _S2 , 5 to 20V is applied as a control signal to the gate of the transistor _P1 , and at this time, the potentials of the output node 70 are both
Since it is 5V or less, it is non-conductive. On the other hand, there are program operations (a write mode in which data is actually written to the memory cell, and a verify mode in which the data is checked to see if it has been written correctly).
In the write mode, switch circuit S ₂ is non-conductive because 20V is applied as a control signal, and switch circuit S ₁ is non-conductive as 0V is applied as a control signal.
is applied, conduction occurs, and the V _PP of node 5
(20V at this time) is supplied to the output node 70.
In addition, in the verify mode of the program operation, switch circuit S ₁ makes sure that V _PP of node 5
20V, but since 20V is applied as a control signal, it becomes non-conductive, and switch circuit _S2 becomes conductive because 0V is applied as a control signal, and its node 5
V _CC (5V) is supplied to output node 70 .

FIG. 8 shows an example of a voltage switching circuit for generating a switching control signal for the voltage switching circuit shown in FIG. ₇ as another application example of the MOS type switch circuit of the present invention. S ₅ is the first to fifth switch circuits described above with reference to FIG. 4, N ₁ and N ₂ are N-channel enhancement type transistors, 80 is an input node, and 8
1 is an output node. That is, transistor N ₁
is connected at one end to input node 80 and to the gate.
V _CC voltage is applied, transistor N ₂ has its gate connected to input node 80 and its source connected to V _SS power supply (ground potential). The first switch circuit _S1 has a node 5 supplied with the _VPP voltage, a node 4 connected to the other end of the transistor _N1 , and a switching control input node (i.e.,
The gate of the switching transistor _P1 ) is connected to the output node 81. Further, in the second switch circuit _S2 , the _VPP voltage is applied to the node 5, the switching control input node is connected to the other end of the transistor _N1 , and the node 4 is connected to the node ₅ of the third switch circuit S3. It is connected to the. This third switch circuit S ₃ has a switching control input node supplied with the V _CC voltage, and a node 4 connected to an output node 81 . Further, in the fourth switch circuit _S4 , the V _CC voltage is applied to the node 5, and the switching control input node is connected to the transistor.
_N1 is connected to the other end, and node 4 is connected to node ₅ of the fifth switch circuit S5. This fifth
The switch circuit S ₅ has the V _PP voltage applied to the switching control input node, and the node 4 is connected to the output node 82 .

Therefore, V _CC is 5 V, V _PP is 5 to 20 V during program operation, and 0 to 5 V at other times. _VPP
>5V and the input node 80 is at the V _SS potential, transistor N ₂ becomes non-conducting and transistor N ₁ becomes conductive, so that the second switch circuit S ₂
conducts and the third switch circuit _S3 also conducts, but
The fourth switch circuit _S4 becomes non-conductive, and the fifth switch circuit _S5 also becomes non-conductive. This brings the output node 81 to the V _PP potential (>5V), and the first switch circuit S ₁ becomes non-conductive. On the contrary,
When the input node 80 reaches the V _SS potential when V _PP ≦5V, the transistor N ₂ becomes non-conductive, the transistor N ₁ becomes conductive, and the third switch circuit S ₂ becomes conductive regardless of whether the second switch circuit S 2 is conductive. The circuit _S3 becomes non-conductive, the fourth switch circuit _S4 becomes conductive, and the fifth switch circuit _S5 also becomes conductive. This brings the output node 81 to V _CC potential, and the first switch circuit
S ₁ becomes non-conducting. Note that input node 80 is connected to V _CC
At this potential, transistor N ₁ is non-conductive and transistor N ₂ is conductive, so that output node 81 is at V _SS potential.

FIG. 9 shows another example of the voltage switching circuit according to the applied example of the present invention, and S ₁ and S ₂ are respectively the first and second switch circuits described above with reference to FIG. 4, for example. It is. That is, in the first switch circuit, the V _PP voltage is applied to the node 5 , the V _CC voltage is applied to the switching control input node, and the node 4 is connected to the output node 90 . Second
In the switch circuit S ₂ , the V _CC voltage is applied to the node 5 , the V _PP voltage is applied to the switching control input node, and the node 4 is connected to the output node 90 .

Therefore, when V _CC =5V and V _PP =20V, the first switch circuit S ₁ becomes conductive, the second switch circuit S ₂ becomes non-conductive, and the output node 90 becomes V _{PP .}
Becomes electric potential. On the other hand, when V _PP ≦5V, the first switch circuit S ₁ becomes non-conductive and the second
switch circuit _S2 becomes conductive, and the output node 90 becomes
Becomes V _CC potential.

Further, when the _VPP voltage is in the range of 5V to 20V, it is possible to form a voltage switching circuit as shown in FIG. 10 by applying the MOS type switch circuit of the present invention. That is, S ₁ and S ₂ are, for example, the fourth
The first and second MOS type switch circuits described above with reference to the figures, _N1 to _N3 are N-channel enhancement type transistors. The above transistor
_N1 has one end connected to the input node 100, the V _CC voltage applied to the gate, and the other end connected to the transistor
Connected to one end of _N2 . this transistor
_N2 has its gate supplied with V _PP potential and its other end connected to the first
is connected to the node 4 of the second switch circuit _S1 and the switching control input node of the _second switch circuit S2. In the first switch circuit _S1 , the _VPP voltage is applied to the node 5, and the switching control input node is connected to the output node 101. In the second switch circuit S ₂ , the V _PP voltage is applied to the node 5 and the node 4 is connected to the output node 101 . Further, the transistor N ₃ has a gate connected to the input node 100 , a source connected to the V _SS power supply, and a drain connected to the output node 101 .

Therefore, since V _CC =5V and V _PP ≧5V, when the input node 100 reaches the V _SS potential, the transistor
N ₃ becomes non-conductive, but transistor N ₁ becomes conductive,
Transistor _N2 also conducts and the second switch circuit
S ₂ becomes conductive, the output node 101 goes to V _PP potential, and the first switch circuit S ₁ becomes non-conductive. When the input node 100 is at V _CC potential, the transistor
N ₁ becomes non-conductive, but transistor N ₃ becomes conductive and the output node 101 goes to V _SS potential. At this time,
The first switch circuit S ₁ becomes conductive and the second switch circuit S ₂ becomes non-conductive.

〔Effect of the invention〕

As described above, the MOS type switch circuit of the present invention is capable of normally and quickly switching between two nodes, including a node whose potential is higher or lower than the power supply voltage regularly applied to the MOS integrated circuit. It has the advantage that the process does not become complicated, a booster circuit for the switching control signal is not required, and it can be realized with a simple configuration.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a conventional MOS switch circuit, FIG. 2 is a circuit diagram showing an embodiment of a MOS switch circuit according to the present invention, and FIGS. A circuit diagram showing an embodiment, FIGS. 5a and 5b are characteristic diagrams shown to explain the operation of the circuit in FIG. 4, and FIG. 6 is a structure on a semiconductor substrate corresponding to the circuit in FIG. 4. 7 to 10 are circuit diagrams showing application examples of the present invention. 4...first node, 5...second node, P1 _~
P ₃ ... P channel transistor, V _a ... 1st
Potential of the node, V _b ... Potential of the second node, V _s ...
... Potential of substrate region, 61 ... Semiconductor substrate, 62 ...
...well, 63-66...diffusion layer, 67,68...
...Diffusion region, 69...Gate oxide film, 70-72
...Gate electrode.

Claims (1)

[Scope of Claims] 1. First, second, and third MOS transistors formed in a well region in a semiconductor substrate and insulated from the semiconductor substrate by a PN junction, each of which is a P-channel type and is not a depletion type. death,
The drains of the second and third transistors are connected to the first transistor.
a bias voltage equal to or higher than the voltage at the first terminal of the first transistor is applied to the source of the second transistor; A bias voltage equal to or higher than the voltage at the second terminal of the first transistor is applied, and the voltage at the first terminal Va and the voltage at the second terminal of the first transistor
When the height relationship with Vb is Va>Vb, the second and third transistors become conductive and non-conductive, and when the above-mentioned height relationship is Va<Vb, the second and third transistors become conductive and non-conductive. A complementary control signal is applied to each gate of the second and third transistors so that the transistor becomes non-conductive and conductive, and a switching control signal is applied to the gate of the first transistor. MOS type switch circuit. 2. The first and second terminals of the first transistor are respectively connected to the sources of the second and third transistors, and the gates of the second and third transistors are connected to the substrate region of the first transistor. 2. The MOS type switch circuit according to claim 1, wherein the MOS switch circuit is connected to the MOS switch circuit. 3. The first and second terminals of the first transistor are respectively connected to the sources of the second and third transistors and the gates of the third and second transistors. A MOS type switch circuit according to claim 1. 4 having first, second, and third MOS transistors each of an N-channel type and not a depletion type, formed in a well region in a semiconductor substrate and insulated from the semiconductor substrate by a PN junction;
The drains of the second and third transistors are connected to the first transistor.
a bias voltage equal to or lower than the voltage at the first terminal of the first transistor is applied to the source of the second transistor; A bias voltage equal to or lower than the voltage at the second terminal of the transistor is applied, and the voltage at the first terminal Va and the voltage at the second terminal of the first transistor are
When the height relationship with Vb is Va<Vb, the second and third transistors become conductive and non-conductive, and when the above-mentioned height relationship is Va>Vb, the second and third transistors become conductive and non-conductive. A complementary control signal is applied to each gate of the second and third transistors so that the transistor becomes non-conductive and conductive, and a switching control signal is applied to the gate of the first transistor. MOS type switch circuit. 5. The first and second terminals of the first transistor are respectively connected to the sources of the second and third transistors, and the gates of the second and third transistors are connected to the substrate region of the first transistor. 5. The MOS type switch circuit according to claim 4, wherein the MOS switch circuit is connected. 6. The first and second terminals of the first transistor are respectively connected to the sources of the second and third transistors and the gates of the third and second transistors. A MOS type switch circuit according to claim 4.