JP3180608B2 - Power supply selection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply selection circuit.

[0002]

2. Description of the Related Art Conventionally, for example, in a semiconductor integrated circuit device having a built-in semiconductor nonvolatile memory, a voltage VPP equal to or higher than a power supply voltage VCC (up to 7 V) usually used when erasing or writing data in a memory cell. (8
~ 15V) is required. At this time, it is not possible to operate the circuit section other than the semiconductor nonvolatile memory at the high voltage VPP due to problems such as reliability and breakdown voltage. Therefore, the normal power supply voltage VCC is used for the logic circuit, and the memory cells are operated at the voltage VPP. For example, two power supply voltages are prepared according to the circuit function. In addition, even if a semiconductor nonvolatile memory is taken, a relatively high voltage VPP is not always necessary. For example, when reading the memory, a relatively low power supply voltage is sufficient for the source and the drain, but the gate side of the memory cell is sufficient. Power supply voltage V
A voltage higher than CC must be applied, and a booster circuit is provided for that purpose. That is, several types of power supplies having different voltages must be prepared. The power supply selection circuit has a circuit function for selecting a desired power supply voltage from several power supply voltages already prepared.

FIG. 11 shows a configuration of a conventional power supply selection circuit. In FIG. 11, reference numeral 1101 denotes a first power supply potential VCC.
1102 is a voltage source for supplying the second power supply potential VPP, 1103 to 1105 are terminals, 1106
Is an output terminal, 1107 is a P-channel MOS field effect transistor, the source is connected to the voltage source 1102, the gate is connected to the voltage source 1101, and the drain is the terminal 1101.
3 is connected. An N-channel MOS field-effect transistor 1108 has a source connected to the ground potential 0 V, a gate connected to the voltage source 1101, and a drain connected to the terminal 1103. As the P-channel MOS field effect transistor 1107, a MOS field effect transistor having a higher current driving capability than the N channel MOS field effect transistor 1108 is used. An inverter 1109 has an input connected to the terminal 1103 and an output connected to the terminal 1104. An inverter 1110 has an input connected to the terminal 1104 and an output connected to the terminal 1105. Reference numeral 1111 denotes an N-channel MOS field-effect transistor having a source connected to the voltage source 1101, a gate connected to the terminal 1104, and a drain connected to the output 1106. Reference numeral 1112 denotes a P-channel MOS type field effect transistor, the source of which is connected to the voltage source 1101,
The gate is connected to the terminal 1105, and the drain is connected to the output 110.
6 is connected. Reference numeral 1113 denotes a P-channel MOS field-effect transistor having a source connected to the voltage source 1102, a gate connected to the terminal 1104, and a drain connected to the output 1.
106. 1114 is an N-channel MOS
In the type field effect transistor, the source is connected to the voltage source 1102, the gate is connected to the terminal 1105, and the drain is connected to the output 1106. Reference numeral 1115 denotes a voltage detection circuit.
It comprises a P-channel MOS type field effect transistor 1107 and an N-channel MOS type field effect transistor 1108.

The operation of the power supply selection circuit shown in FIG. 11 will be briefly described. First, when the potential VCC of the voltage source 1101 is equal to the potential VPP of the voltage source 1102, the P-channel M
The OS type field effect transistor 1107 has its source
The gate-to-gate voltage becomes 0 V and becomes non-conductive, and the gate voltage of N-channel MOS field effect transistor 1108 becomes conductive at power supply potential VCC. As a result, the potential of the terminal 1103 becomes 0 V through the N-channel MOS field effect transistor 1108.
The inverter 1109 outputs the power supply potential VCC to the terminal 1104 because the input terminal 1103 has the ground potential of 0 V. Since the input terminal 1104 is at the power supply potential VCC, the inverter 1110 outputs a ground potential of 0 V to the terminal 1105. N-channel MOS field effect transistor 1
Reference numeral 111 denotes a P-channel MOS type field effect transistor which is turned on when the gate voltage is at the power supply potential VCC.
No. 2 becomes conductive when the gate voltage is 0 V. As a result, the output 1106 is supplied to the potential VC of the voltage source 1101 through the N-channel MOS field-effect transistor 1111 and the P-channel MOS field-effect transistor 1112.
Become C. At this time, the gate voltage of the P-channel MOS field effect transistor 1113 is turned off at the power supply potential VCC, and the N-channel MOS field effect transistor 1113 is turned off.
Reference numeral 114 denotes a non-conductive state where the gate voltage is 0 V of the ground potential.

Next, when the potential VPP of the voltage source 1102 is higher than the potential VCC of the voltage source 1101, the source-gate voltage of the P-channel MOS field effect transistor 1107 becomes (VPP-VCC). The transistor 1108 is turned on, and the gate voltage of the N-channel MOS field effect transistor 1108 is turned on at the power supply potential VCC. As a result, a through current always flows through the P-channel MOS field-effect transistor 1107 and the N-channel MOS field-effect transistor 1108 of the voltage detection circuit 1115, and the potential of the terminal 1103 becomes equal to the P-channel MOS field-effect transistor 1107 The intermediate potential is determined by the ratio of the current driving capability of the channel MOS field effect transistor 1108. Since the current driving capability of the P-channel MOS field effect transistor 1107 is larger than the current driving capability of the N-channel MOS field effect transistor 1108, the potential of the terminal 1103 is lower than the ground potential of 0 V by the voltage source 1
The intermediate potential becomes a value close to the potential VPP of 102. Since the terminal 1103 which is an input of the inverter 1109 has a value close to the second power supply potential VPP, the ground potential 0 V is applied to the terminal 1104.
Output to Inverter 1110 has input terminal 11
04 is ground potential 0V, the power supply potential VCC is connected to the terminal 11
Output to 05. The P-channel MOS field-effect transistor 1113 is turned on when the gate voltage is 0 V and the N-channel MOS field-effect transistor 1113 is turned on.
Reference numeral 114 turns on when the gate voltage is at the power supply potential VCC. As a result, the output 1106 becomes the potential VPP of the voltage source 1102 through the P-channel MOS field effect transistor 1113 and the N-channel MOS field effect transistor 1114. At this time, the gate voltage of the N-channel MOS field effect transistor 1111 is set to the ground potential 0V.
, The P-channel MOS field effect transistor 1112 is in a non-conductive state when the gate voltage is at the power supply potential VCC.

As described above, when the potential of the voltage source 1102 that outputs the second power supply potential VPP is the same as the potential of the voltage source 1101 that outputs the first power supply potential VCC, the output 11
06, the first power supply potential VCC is output. When the potential of the voltage source 1102 that outputs the second power supply potential VPP is higher than the potential of the voltage source 1101 that outputs the first power supply potential VCC, the output 1106 is output. The second power supply potential VPP is output. At this time, a through current constantly flows through the P-channel MOS field effect transistor 1107 and the N-channel MOS field effect transistor 1108 of the voltage detection circuit 1115. That is, conventionally,
In order to switch between the first power supply and the second power supply, it is necessary to detect the second power supply potential, and at that time, there is a problem that a through current must be constantly flowed.

FIG. 12 is a block diagram of a conventional power supply selection circuit including a booster circuit. In the figure, reference numeral 1202 denotes an input terminal;
Reference numeral 03 denotes a terminal, 1205 denotes an output terminal, 1206 denotes a booster circuit which outputs a potential higher than the power supply potential in response to an input up to the power supply potential, and 1208 denotes a decoder group which selects and outputs an input potential. When a power supply voltage is applied to the input terminal 1202, the power supply voltage is boosted to a power supply voltage or higher by the booster circuit 1206 and output to the terminal 1203, and the output is given to the decoder group 1208 and output from the output terminal 1205.
Taken out.

FIG. 13 shows a booster circuit 1206 in FIG.
An example of the circuit configuration of FIG. 13, reference numeral 1301 denotes an input terminal for receiving a voltage from the ground potential to the power supply potential;
1302, an output terminal for outputting a potential higher than the power supply potential;
303, a capacitor having the first electrode connected to the input terminal 1301 and the second electrode connected to the output terminal 1302;
Is a voltage source that supplies the power supply potential VCC, and 1305 is a diode that supplies the potential of the voltage source 1304 to the output terminal 1302.

FIG. 14 is a time chart showing the operation of the booster circuit of FIG. Hereinafter, the circuit operation of the booster circuit shown in FIG. 13 will be described with reference to FIG.

Assume that a ground potential of 0 V is applied to input terminal 1301. The output terminal 1302 has a potential lower than the potential of the voltage source 1304 by about 0.7 V (a physically determined voltage drop of the diode) due to the forward current of the diode 1305. At this time, capacitor 1
Reference numeral 303 indicates that the potential between the electrodes is about (VCC-0.7 V). When the potential of the input terminal 1301 is changed to the power supply potential VCC from this state, the potential of the output terminal 1302 is boosted by the capacitor 1303. The potential at this time is represented by VCC−0.7 V + VCC × (CC / CA), where CC is the capacitance of the capacitor 1303 and CA is all capacitance components connected to the output terminal 1302.

FIG. 15 shows the decoder group 12 in FIG.
08 shows an example of the circuit configuration. In FIG.
Is a power input terminal for supplying an output potential,
Reference numeral 1505 denotes a selection signal for selecting an output. All of the selection signals 1502 to 1505 have a ground potential of 0 V, or one of the selection signals 1502 to 1505 has a power supply potential VCC, and the other three have a ground potential of 0 V. It has become.
Reference numerals 1506 to 1509 denote outputs selected by the selection signals 1502 to 1505. An inverter 1510 has an input terminal connected to the selection signal 1502. Reference numeral 1511 denotes an N-channel MOS field-effect transistor whose gate is connected to the selection signal 1502, whose source is connected to the ground potential 0 V, and whose drain is connected to the terminal 1512. 151
Numeral 3 denotes an N-channel MOS field effect transistor whose gate is connected to the output terminal of the inverter 1510, whose source is connected to the ground potential 0 V, and whose drain is connected to the output 1506. Reference numeral 1514 denotes a P-channel MOS field-effect transistor having a gate connected to the output 1506, a source and a substrate connected to the power input terminal 1501, and a drain connected to the terminal 1512. 1515 is P channel MO
An S-type field effect transistor having a gate connected to the terminal 1512, a source and a substrate connected to the power input terminal 1501,
The drain is connected to output 1506. Reference numeral 1516 denotes a decoder including an inverter 1510, N-channel MOS field-effect transistors 1511 and 1513, and P-channel MOS field-effect transistors 1514 and 1515. 1517 to 1519 are also decoders having the same circuit configuration as 1516.

The operation of the decoder 1516 in FIG. 15 will be described briefly. First, consider a state in which the output 1506 is not selected, that is, a case where the selection signal 1502 is at the ground potential 0V. N-channel MOS field effect transistor 151
Reference numeral 1 denotes a non-conductive state in which the gate potential is the ground potential 0V.
Inverter 1510 outputs power supply potential VCC since the input is ground potential 0V. Therefore, the gate of the N-channel MOS field effect transistor 1513 is turned on when the potential of the VCC is VCC, and the potential of the output 1506 is set to the ground potential 0V. Since the potential of the output 1506 becomes the ground potential 0 V, P
When the potential of the gate of the channel MOS type field effect transistor 1514 becomes conductive at the ground potential of 0 V, the terminal 15
Twelve potentials are made equal to the potential of the power input terminal 1501. Since the potential of the terminal 1512 becomes equal to the potential of the power input terminal 1501, the gate potential of the P-channel MOS field effect transistor 1515 is changed to the power input terminal 1501.
And the output 1506 is at the ground potential of 0 V
Will be maintained. Thus, when the selection signal 1502 is at the ground potential 0 V, the output 1506 is at the ground potential 0 V
Is output.

Next, consider a state in which the output 1506 is selected, that is, when the selection signal 1502 is at the power supply potential VCC.
Since the input of the inverter 1510 is VCC, the ground potential is 0V.
Is output. Therefore, the N-channel MOS type field effect transistor 1513 is turned off when the gate potential is 0 V. The gate potential of the N-channel MOS field effect transistor 1511 is turned on when the potential of the gate is VCC, and the potential of the terminal 1512 is set to the ground potential 0V. Terminal 1
Since the potential of 512 becomes the ground potential 0V, the P channel M
The potential of the gate of the OS-type field effect transistor 1515 is turned on at the ground potential of 0 V, and the potential of the output 1506 is made equal to the potential of the power input terminal 1501. Output 150
6 becomes equal to the potential of the power supply input terminal 1501, so that the P-channel MOS field effect transistor 1514
The gate potential is turned off at the potential of the power supply input terminal 1501 and the terminal 1512 is maintained at the ground potential of 0V. Thus, when the selection signal 1502 is at VCC, the potential of the power supply input terminal 1501 is output to the output 1506.

Since the decoders 1517 to 1519 have the same circuit configuration, they operate in the same manner as the decoder 1516. As described above, the selection signals 1502 to 1505
Of the outputs 1506 to 1509, only one of them has the power supply potential VCC.
The potential of the power input terminal 1501 can be output to only one corresponding to 1505.

However, during the operation of the decoder, power is supplied through the P-channel MOS field effect transistor 1514 and the N-channel MOS field effect transistor 1511 or through the P-channel MOS field effect transistor 1515 and the N-channel MOS field effect transistor 1513. A through current flows from the input terminal 1501 to the ground potential.

FIG. 16 is a time chart showing the operation of the power supply selection circuit of FIG. Hereinafter, the operation of the power supply selection circuit of FIG. 12 will be described with reference to FIG.

Consider a state in which a ground potential of 0 V is applied to the input terminal 1202 and a ground potential of 0 V is also applied to the signal lines of the decoder group 1208 as an initial state. Terminal 1
Reference numeral 203 denotes a power supply potential of about 0.7 V (voltage drop of a diode which is physically determined) and a low potential (VCC-0.7).
V). Since the signal lines of the decoder group 1208 are all 0V, the ground potential 0V is output to the output terminal 1205.

In this state, when the potential of the input terminal 1202 is changed to the power supply potential VCC, the potential of the terminal 1203 becomes VC
C or more. Hereinafter, the potential of the terminal 1203 at this time is set to V
BT. Next, when one of the signals of the decoder group 1208 is selected, the potential VBT of the terminal 1203 is changed to the output terminal 1.
205. However, at this time, the decoder group 1
Since a through current flows inside the terminal 208, the terminal 1203
Is lowered. Hereinafter, the potential of the terminal 1203 at the time of this decrease is referred to as VBD.

Finally, when the potential of the input terminal 1202 is returned to the ground potential 0 V, the potential of the terminal 1203 is changed from VBT to VBD.
Therefore, the potential of the terminal 1203 is lower than the potential (VCC-0.7 V) of the terminal 1203 in the initial state. As a result, there arises a problem that a drop in the input power supply potential to the decoder group 1208 causes a malfunction of the circuits of the decoder group 1208 and a sufficient boosted potential of the booster circuit 1206 cannot be obtained.

FIG. 17 shows a configuration of a conventional power supply selection circuit. In the figure, 1701 is a voltage source for supplying a first power supply potential VCC, 1702 is a VCC internal circuit using the voltage source 1701 as a power supply, and 1703 is a first power supply potential V
CC or a second power supply potential V higher than the first power supply potential
A voltage source for supplying PP, 1705 is a VPP-based internal circuit using a voltage source 1703 as a power supply voltage, 1706 is a semiconductor nonvolatile memory, 1707 is a cell array of the semiconductor nonvolatile memory, 1708 is a VCC-based internal circuit 170
Signal line group between 2 and VPP internal circuit 1705, 17
09 denotes a VCC internal circuit 1702 and a cell array 1707.
1710 is a signal line group between the cell array 1707 and V
This is a signal line group connected to the PP-system internal circuit 1705.

The voltage source 1701 is directly connected to the VCC internal circuit 1
702, and the voltage source 1703 is directly
Since it is used as a power supply for the PP-related internal circuit 1705, it is not allowed to set the voltage sources 1701 and 1703 to the ground potential 0V. In other words, the voltage required for the read operation of the semiconductor nonvolatile memory is only one first power supply potential VCC, but the first power supply potential VCC must be applied from two terminals of the voltage source 1701 and the voltage source 1703. No.

FIG. 18 shows input terminals Vin1 and Vin2.
1 shows an example of a conventional power supply selection circuit using an exclusive OR, in which either the power supply voltage VCC or the ground potential 0 V can be taken to the output terminal Vout depending on the signal level given to the output terminal Vout. As shown in the figure, an inverter INV requires two MOS field-effect transistors in order to configure a logic circuit in an exclusive OR operation, so that a total of 12 MOS transistors are required.
Type field effect transistor was required.

[0023]

That is, the present invention provides:
A power supply selection circuit that eliminates the need to detect a second power supply potential in order to switch between a first power supply and a second power supply, and to constantly pass through current at that time. It is.

[0024]

According to a first aspect of the present invention, a power supply selection circuit includes a first input terminal connected to a source of a first field effect transistor and a gate of a second field effect transistor. The second input terminal is connected to the source of the second field-effect transistor and the gate of the first field-effect transistor, and the output terminal is connected to the drain of the first field-effect transistor and the second field-effect transistor. It is configured to be connected to the drain.

A power supply selection circuit according to a second invention comprises the power supply selection circuit according to the first invention, wherein a voltage source is connected to the first input terminal, and a booster circuit is connected to the second input terminal. Things.

A power supply selection circuit according to a third invention includes the power supply selection circuit according to the first invention, wherein a first booster circuit is connected to a first input terminal, and a second booster circuit is connected to a second input terminal. It is configured by connecting.

A power supply selection circuit according to a fourth aspect includes the power supply selection circuit according to the first aspect, wherein the first input terminal is connected to the first voltage source, and the second input terminal is also used as a signal input terminal. And a second voltage source connected thereto.

The power supply selection circuit of the fifth invention uses two power supply selection circuits of the first invention, connects a first signal to a first input terminal of the first power supply selection circuit, and provides a first power supply selection circuit. Connect the second signal to the second input terminal of the circuit, connect the first signal to the first input terminal of the second power supply selection circuit, and to the second input terminal of the second power supply selection circuit It is configured by connecting the logically inverted signal of the second signal and connecting the output terminal of the first power supply selection circuit and the output terminal of the second power supply selection circuit.

[0029]

According to the first aspect of the present invention, any of the plurality of field-effect transistors is turned on by the above-described configuration, and the maximum or minimum potential among the plurality of inputs is output.

According to the second aspect of the present invention, the potential of the output does not drop below the potential of the voltage source even when the boosting operation is performed.

According to the third aspect of the present invention, since the booster circuits are alternately operated by the above configuration, a sufficient time can be taken from the end of boosting to the start of boosting.

According to the fourth aspect of the present invention, with the above-described configuration, it is possible to apply a voltage from the ground potential to a voltage higher than the first voltage source to the second input terminal.

According to the fifth aspect of the present invention, the exclusive OR of two input signals can be output by the above configuration.

[0034]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a power supply selection circuit according to an embodiment of the present invention;

FIG. 1 is a circuit diagram of the present embodiment. In FIG. 1, 101 is an input terminal for supplying a first power supply potential VCC1, 102 is an input terminal for supplying a second power supply potential VCC2, 103 is an output terminal for outputting the selected potential VO, and 104 and 105 are output terminals. It is a P-channel MOS field effect transistor.

The first input terminal 101 is connected to the source of the first P-channel MOS field effect transistor 104,
Second P-channel MOS field effect transistor 10
5 gate. Second input terminal 102
Is connected to the source of the second P-channel MOS field effect transistor 105 and the gate of the first P-channel MOS field effect transistor 104. The output terminal 103 is connected to the drain of the first P-channel MOS field effect transistor 104 and the drain of the second P-channel MOS field effect transistor 105. The drains of the P-channel MOS field effect transistors 104 and 105 are connected to a semiconductor substrate (not shown) in which the transistors are formed.

FIG. 2 shows input / output terminal characteristics showing the circuit operation of FIG. The horizontal axis in FIG.
The vertical axis represents the potential difference between the input terminal 101 and the output terminal 103 (VO-VCC).
1). VT in FIG. 2 is a threshold voltage of the P-channel MOS field effect transistors 104 and 105. Hereinafter, the threshold voltage of the P-channel MOS field-effect transistors 104 and 105 is VT. VP is P
Channel MOS field effect transistors 104 and 10
5 between the source of No. 5 and the semiconductor substrate (not shown)
This is the built-in potential of the N junction. Hereinafter, the built-in potential of the PN junction between the sources of the P-channel MOS field-effect transistors 104 and 105 and the substrate is defined as VP. A region where the potential difference (VCC2-VCC1) between the input terminals 101 and 102 is -VT or less is defined as a region A, a region where the potential difference is greater than -VT and less than VT is defined as a region B, and a region where it is greater than or equal to VT is defined as a region. Region C is assumed.

The circuit operation of the embodiment shown in FIG. 1 will now be described with reference to FIG.
This will be described with reference to FIG. In a region A where the potential difference (VCC2-VCC1) between the input terminals 101 and 102 is -VT or less, the P-channel MOS field effect transistor 104
Becomes conductive because the potential of the gate thereof is lower than the potential of the source by VT or more. At this time, the potential of the gate of the P-channel MOS field-effect transistor 105 is higher than the potential of the source, so that the P-channel MOS transistor 105 is turned off.
As a result, the input terminal 101 via the P-channel MOS field effect transistor 104 which is in a conductive state
Appears at the output terminal 103. That is, VO = VCC1 VO−VCC1 = 0, and the characteristics of the region A in FIG. 2 are obtained.

The potential difference between the input terminals 101 and 102 (VC
In a region B where C2−VCC1) is larger than −VT and smaller than VT, the P-channel MOS field effect transistor 104 is non-conductive because the difference between the gate potential and the source potential is smaller than VT. The P-channel MOS field effect transistor 105 is also in a non-conductive state because the difference between the gate potential and the source potential thereof is also less than VT. As a result, the output terminal 10
3 is not uniquely determined. However, output terminal 10
3 is higher than the potential of the gate of the P-channel MOS field-effect transistor 104 or the gate of the P-channel MOS field-effect transistor 105 by VT or more, the P-channel MOS field-effect transistor 1
04 or the P-channel MOS field effect transistor 105 becomes conductive, and the potential of the output terminal 103 decreases. Therefore, the potential of the output terminal 103 does not become higher than VT as compared with the gate potential of the P-channel MOS field-effect transistor 104 or the P-channel MOS field-effect transistor 105. When the potential of the output terminal 103 is lower than the potential of the source of the P-channel MOS field-effect transistor 104 or the P-channel MOS field-effect transistor 105 by VP or more, the P-channel MOS field-effect transistor 104 Alternatively, the PN between the source of the P-channel MOS field effect transistor 105 and the semiconductor substrate is
A voltage is applied in the forward direction of the junction. Therefore, the potential of the output terminal 103 increases. The potential of the output terminal 103 is P
It does not become lower than VP as compared with the source potential of the channel MOS field effect transistor 104 or the P channel MOS field effect transistor 105. That is, when VCC2≤VCC1, VCC1-VP≤VO≤VCC2 + VT-VP≤VO-VCC1≤VCC2-VCC1 + VT When VCC2> VCC1, VCC2-VCC1-VP≤VO-VCC1≤VT. Thus, the characteristics of the region B can be obtained.

The potential difference between the input terminals 101 and 102 (VC
In the region C where (C2−VCC1) is equal to or higher than VT, the P-channel MOS field effect transistor 104 is turned off because the gate potential is higher than the source potential. On the other hand, the P-channel MOS field effect transistor 105 is turned on because the potential of the gate thereof is lower than the potential of the source by VT or more. As a result, the potential of the input terminal 102 appears at the output terminal 103 via the P-channel MOS field effect transistor 105 which is in a conductive state. That is, VO = VCC2 VO-VCC1 = VCC2-VCC1, and the characteristics of the region C in FIG. 1 are obtained.

The above is the description of the operation of the power supply selection circuit of the present invention shown in FIG. As is apparent from the above, the power supply selection circuit of the present invention does not need to include a voltage detection circuit that has been required conventionally. Therefore, there is no need to pass through current. That is, according to the present invention, the higher one of the input terminals 101 and 102 can be taken out to the output terminal 103.

FIG. 3 shows a power supply selection circuit constituted by using a plurality of stages of the power supply selection circuit of FIG. First power supply selection circuit 3
01 is an input terminal 302, an input terminal 303, and an output terminal 3
04. The second power supply selection circuit 305 includes an input terminal 306, an input terminal 307, and an output terminal 308. The third power supply selection circuit 309 includes an input terminal 310, an input terminal 311 and an output terminal 312. The output terminal 304 of the first power selection circuit 301 is connected to the input terminal 310 of the third power selection circuit 309, and the output terminal 308 of the second power selection circuit 305 is connected to the third power selection circuit 30.
9 is connected to the input terminal 311.

With this configuration, the input terminal 302 of the first power supply selection circuit 301, its input terminal 303,
The highest potential of the input terminal 306 of the second power supply selection circuit 305 and the input terminal 307 can be transmitted to the output terminal 312 of the third power supply selection circuit 309.

FIG. 4 shows P-channel MOS type field effect transistors 104 and 105 in the power supply selection circuit of FIG.
Are replaced with N-channel MOS transistors 404 and 405, respectively. With this configuration, the lower one of the input terminals 401 and 402 can be transmitted to the output terminal 403.

A power supply selection circuit according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 5 shows P-channel MOS type field effect transistors 104 and 105 in the power supply selection circuit of FIG.
Is not connected to the output terminal. When a potential higher than the potentials of the input terminals 501 and 502 is obtained, the obtained high potential is connected to the substrate potentials of the P-channel MOS field-effect transistors 504 and 505, and the output terminal 503 is connected to the P-channel MOS field-effect transistor. It is not necessary to connect to the substrate potentials 504 and 505.

In FIG. 5, reference numeral 501 denotes a first power supply potential V
An input terminal for supplying CC1, 502 is a second power supply potential V
An input terminal for supplying CC2, 503 is a selected potential V
Output terminals 504 and 505 from which O is output are P-channel MOS field effect transistors.

FIG. 6 shows input / output terminal characteristics showing the circuit operation of FIG. The horizontal axis in FIG. 6 indicates the potential difference (VCC2-VCC1) between the input terminals 501 and 502, and the vertical axis indicates the input terminal 50.
1 and a potential difference (VO-VCC1) between the output terminal 503 and the output terminal 503. VT in FIG. 5 is a threshold voltage of the P-channel MOS field effect transistors 504 and 505. Hereinafter, a P-channel MOS field effect transistor 50
The threshold voltage of 4,505 is VT. VP is a built-in potential of a PN junction between the sources of the P-channel MOS field effect transistors 504 and 505 and a semiconductor substrate (not shown). Hereinafter, the built-in potential of the PN junction between the sources of the P-channel MOS field effect transistors 504 and 505 and the substrate is defined as VP. A region where the potential difference (VCC2-VCC1) between the input terminals 501 and 502 is -VT or less is defined as a region A, a region where the potential difference is greater than -VT and less than VT is defined as a region B, and a region where it is greater than or equal to VT is defined as a region. Area C
And

The circuit operation of the embodiment shown in FIG. 5 will now be described with reference to FIG.
This will be described with reference to FIG. In a region A where the potential difference (VCC2-VCC1) between the input terminals 501 and 502 is -VT or less, the P-channel MOS field effect transistor 504
Becomes conductive because the potential of the gate thereof is lower than the potential of the source by VT or more. At this time, the potential of the gate of the P-channel MOS field-effect transistor 505 is higher than the potential of the source, so that the transistor is turned off.
As a result, the input terminal 501 passes through the P-channel MOS field effect transistor 504 which is in a conductive state.
Appears at the output terminal 503. That is, VO = VCC1 VO−VCC1 = 0, and the characteristics of the region A in FIG. 6 are obtained.

The potential difference between the input terminals 501 and 502 (VC
In a region B where C2−VCC1) is larger than −VT and smaller than VT, the P-channel MOS field effect transistor 504 is non-conductive because the difference between the gate potential and the source potential is smaller than VT. State, and the P-channel MOS field effect transistor 505 also becomes non-conductive because the difference between the potential of the gate and the potential of the source becomes less than VT. As a result, the potential of the output terminal 503 is not determined. However, when the potential of the output terminal 503 is P
If the potential of the gate of the channel MOS type field effect transistor 504 or the P channel MOS type field effect transistor 505 is higher than VT by more than VT, the P channel MOS type field effect transistor 504 or P
The channel MOS field-effect transistor 505 becomes conductive, and the potential of the output terminal 503 decreases. Therefore, the potential of the output terminal 503 is set to the P-channel MOS type
Compared with the gate potential of the field-effect transistor 505,
It will not be higher than VT. That is, when VCC2 ≦ VCC1, VO ≦ VCC2 + VT VO−VCC1 ≦ VCC2-VCC1 + VT When VCC2> VCC1, VO ≦ VCC1 + VT VO−VCC1 ≦ VT, and the characteristics of the region B in FIG. 6 are obtained.

The potential difference between the input terminals 501 and 502 (VC
In a region C where C2−VCC1) is equal to or higher than VT, the P-channel MOS field effect transistor 504 is turned off because the gate potential is higher than the source potential. On the other hand, the P-channel MOS field-effect transistor 505 is turned on because the potential of the gate thereof is lower than the potential of the source by VT or more. As a result, the potential of the input terminal 502 appears at the output terminal 503 via the P-channel MOS field effect transistor 505 which is in a conductive state. That is, VO = VCC2 VO-VCC1 = VCC2-VCC1, and the characteristics of the region C in FIG. 6 are obtained.

The above description shows the basic operation of the power supply selection circuit shown in FIG. It is characterized in that a voltage detection circuit is unnecessary as compared with the related art. For this reason, the higher one of the input terminals 501 and 502 can be taken out to the output terminal 503 without flowing useless current.

By replacing the P-channel MOS field-effect transistors 504 and 505 in FIG. 5 with N-channel MOS field-effect transistors, the lower potential of the input terminals 501 and 502 is applied to the output terminal 5.
03, and by making the potentials of the input terminals 501 and 502 the same, a circuit that does not affect the input terminals 501 and 502 even when the potential of the output terminal 503 increases can be configured.

It is also possible to connect the power supply selection circuits of FIG. 5 in multiple stages as shown in FIG.

Next, an embodiment corresponding to claims 4 and 5 will be described with reference to the drawings.

FIG. 7 is a block diagram of this embodiment. FIG.
701 is a voltage source for supplying the power supply potential VCC,
Reference numeral 702 denotes an input terminal, reference numerals 703 and 704 denote terminals, reference numeral 705 denotes an output terminal, reference numeral 706 denotes a booster circuit having the circuit configuration shown in FIG. 13 described in the conventional example, and reference numeral 707 denotes a circuit configuration shown in FIG. A power supply selection circuit 708 is a decoder group having a circuit configuration as shown in FIG.

FIG. 8 is a time chart showing the operation of the booster circuit of FIG. The circuit operation of the embodiment shown in FIG. 7 will be described below with reference to FIG.

Consider a state in which a ground potential of 0 V is applied to input terminal 702 and a ground potential of 0 V is also applied to the signal lines of decoder group 708 as an initial state. Terminal 703
Becomes lower than the power supply potential by about 0.7 V (voltage drop of the diode which is physically determined). Power supply selection circuit 70
Since 7 outputs the higher voltage of the two input terminals, the terminal 704 is at the power supply potential VCC. Now decoder group 7
Since the signal lines 08 are all 0 V, the ground potential 0 V is output to the output terminal 705.

In this state, when the potential of the input terminal 702 is changed to the power supply potential VCC, the potential of the terminal 703 becomes higher than VCC. Hereinafter, the potential of the terminal 703 at this time is set to VBT. As a result, the power supply selection circuit 707 outputs the higher potential VBT of the terminal 703 to the terminal 704. Next, when one of the signals of the decoder group 708 is selected, the potential VBT of the terminal 704 is output to the output terminal 705.
However, at this time, since a through current flows inside the decoder group 708, the potentials of the terminals 703 and 704 decrease. Hereinafter, the potential of the terminals 703 and 704 at the time of this decrease is referred to as VBD.

Finally, the potential of the input terminal 702 is set to the ground potential 0.
When the voltage is returned to V, the potentials of the terminals 703 and 704 are changed from VBT to V
Since the voltage has decreased to BD, the potential of the terminal 703 is lower than the potential (VCC-0.7 V) of the terminal 703 in the initial state. However, since the potential of the voltage source 701 is the power supply potential VCC, the power supply selection circuit 707 outputs the higher power supply potential VCC to the terminal 704. As a result, the input power supply potential to the decoder group 708 does not decrease.

The voltage source 701 shown in FIG.
The same effect can be obtained even if the booster circuit is operated alternately, and the time required for the booster circuit to be in the stationary state can be taken for the alternate operation, so that the boosted potential of the booster circuit cannot be sufficiently obtained. That doesn't happen either.

Next, an embodiment corresponding to claim 6 will be described with reference to the drawings. In FIG. 9, 90
1 is a voltage source for supplying the first power supply potential VCC, 902 is a VCC internal circuit using the voltage source 901 as a power supply, 9
03 is a voltage source for supplying the second power supply potential VPP,
In addition, it is a voltage source and signal line that may also be used as an internal signal. Reference numeral 904 denotes a power supply selection circuit having two input terminals connected to a voltage source 901 and a voltage source / signal line 903, respectively, as shown in FIG.
This is a VPP-based internal circuit that uses the output of circuit 04 as the power supply voltage of the circuit. 906 is a semiconductor nonvolatile memory, 90
7 is a cell array of a semiconductor nonvolatile memory, and 908 is V
A signal line group between the CC internal circuit 902 and the VPP internal circuit 905, 909 is a signal line group between the VCC internal circuit 902 and the cell array 907, and 910 is a cell array 90
7 is a signal line group between the internal circuit 7 and the VPP system internal circuit 905.

When the VPP system internal circuit 905 must be operated at the second power supply potential VPP, the voltage source / signal line 903 outputs the second power supply potential VPP. Since the power supply selection circuit 904 outputs the higher voltage of the two inputs, it outputs the second power supply potential VPP and operates the VPP system internal circuit 905. When the VPP system internal circuit 905 must be operated at the first power supply potential VCC, the voltage source / signal line 903 outputs the first power supply potential VCC or the ground potential 0V. Since the power supply selection circuit 904 outputs the higher voltage of the two inputs, it outputs the first power supply potential VCC and operates the VPP system internal circuit 905. When the voltage source / signal line 903 outputs the ground potential 0 V, the power supply selection circuit 9
04 outputs the higher voltage of the two inputs, so that it outputs the first power supply potential VCC, and the VPP system internal circuit 905 can operate.

As described above, the VCC internal circuit 902 and V
When both the PP-related internal circuits 905 are operated at the first power supply potential VCC, the voltage source 901 supplies the first power supply potential V
If CC is output, it is not necessary to output the first power supply potential VCC to the voltage source / signal line 903, and the ground potential 0 V
And an arbitrary potential of the first power supply potential VCC, which can be used as a signal line.

Next, an embodiment corresponding to claim 7 will be described with reference to the drawings. FIG. 10 is a circuit diagram of the present embodiment. In FIG. 10, reference numeral 1001 denotes a first input terminal, 1002 denotes a second input terminal, and 1003 denotes an inverter having the input terminal 1002 as an input. Reference numeral 1004 denotes a power supply selection circuit as shown in FIG. 1 (however, the substrate of each P-channel MOS field effect transistor is not connected to an output terminal), and two input terminals are connected to an input terminal 1001 and an input terminal 1002, respectively. Connected. 10
Reference numeral 05 denotes a power supply selection circuit as shown in FIG.
The substrate of the channel MOS field effect transistor is not connected to the output terminal), and two input terminals are connected to the input terminal 1001 and the output of the inverter 1003. An output terminal 1006 is connected to the output terminals of the power supply selection circuit 1004 and the power supply selection circuit 1005.

The operation of the circuit shown in FIG. 10 will be described. First, when both the input terminal 1001 and the input terminal 1002 are at the ground potential of 0 V, the power supply selection circuit 1004 does not output the potential to the output terminal 1006 because the two input terminals are both at the ground potential of 0 V. Inverter 1003 outputs power supply potential VCC because the input is ground potential 0V. Power supply selection circuit 1
005 have two input terminals, a ground potential 0 V and a power supply potential VC.
Since it is C, the ground potential 0 V, which is the lower potential, is output to the output terminal 1006. As a result, the potential of the output terminal 1006 becomes the ground potential 0V.

Next, when the input terminal 1001 is at the ground potential 0 V and the input terminal 1002 is at the power supply potential VCC, the power supply selection circuit 1004 has the higher power supply potential since the two input terminals are the ground potential 0 V and the power supply potential VCC. VCC
Is output to the output terminal 1006. Inverter 1003 outputs ground potential 0 V because the input is power supply potential VCC.
Since both input terminals of the power supply selection circuit 1005 have a ground potential of 0 V, there is no potential output to the output terminal 1006.
As a result, the potential of the output terminal 1006 becomes the power supply potential VCC.

Next, the input terminal 1001 is connected to the power supply potential VCC.
When the input terminal 1002 is at the ground potential 0 V, the power supply selection circuit 1004 has the higher potential of the power supply potential VCC since the two input terminals are the ground potential 0 V and the power supply potential VCC.
Is output to the output terminal 1006. Inverter 1003 outputs power supply potential VCC because the input is ground potential 0V.
Since the two input terminals of the power supply selection circuit 1005 are both at the power supply potential VCC, there is no potential output to the output terminal 1006. As a result, the potential of the output terminal 1006 becomes the power supply potential VC.
Become C.

Next, the input terminal 1001 and the input terminal 100
2 are both at power supply potential VCC, power supply selection circuit 1
004 has no potential output to the output terminal 1006 because both input terminals have the power supply potential VCC. Inverter 1
003 outputs the ground potential 0 V because the input is the power supply potential VCC. Since two input terminals of the power supply selection circuit 1005 have the ground potential of 0 V and the power supply potential VCC, the lower potential of the ground potential 0 V is output to the output terminal 1006. As a result, the potential of the output terminal 1006 becomes the ground potential 0V.

As described above, the output of the exclusive OR of the input terminal 1001 and the input terminal 1002 can be output to the output terminal 1006 with a total of six transistors including the two transistors constituting the inverter 1003. I can do it.

By exchanging the power supply selection circuit 1004 with the power supply selection circuit 1005, the exclusive OR can be negated by using only six transistors.

In FIGS. 10 and 11, the connection of the input terminals of the power supply selection circuits 1004 and 1005 is not particularly limited unless the logic is inverted, and can be arbitrarily configured.

[0073]

According to the power supply selection circuit of the first invention, there is no need to supply a through current when switching the power supply selection.

The power supply selection circuit according to the second invention can suppress the fluctuation of the output potential at the end of boosting.

The power supply selection circuit according to the third aspect of the present invention can suppress the fluctuation of the output potential at the end of boosting, and can suppress the decrease of the boosted potential.

In the power supply selection circuit according to the fourth invention, the second power supply terminal can be used as it is as a signal terminal.

The power supply selection circuit according to the fifth invention can realize an exclusive OR circuit having a small number of elements or negation of the exclusive OR.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a power supply selection circuit according to an embodiment of the first invention.

FIG. 2 is an input / output characteristic diagram for explaining an operation in the embodiment of the first invention.

FIG. 3 is a diagram showing a configuration of a power supply selection circuit configured by combining a plurality of stages of the embodiment of the first invention.

FIG. 4 is a diagram showing a configuration of a power supply selection circuit according to another embodiment of the first invention.

FIG. 5 is a diagram showing a configuration of a power supply selection circuit according to another embodiment of the first invention.

FIG. 6 is an input / output terminal characteristic diagram for explaining an operation in another embodiment of the first invention.

FIG. 7 is a diagram showing a configuration of a power supply selection circuit according to an embodiment of the second invention.

FIG. 8 is a timing chart for explaining the operation in the embodiment of the second invention.

FIG. 9 is a diagram showing a configuration of a power supply selection circuit according to an embodiment of the fourth invention.

FIG. 10 is a diagram showing a configuration of a power supply selection circuit according to an embodiment of the fifth invention;

FIG. 11 is a diagram showing a configuration of a power supply selection circuit of a conventional example.

FIG. 12 is a diagram showing a configuration including a booster circuit in a power supply selection circuit of a conventional example.

FIG. 13 is a diagram showing a configuration of a booster circuit in a conventional power supply selection circuit.

FIG. 14 is a timing chart for explaining the operation of a booster circuit in a conventional power supply selection circuit.

FIG. 15 is a diagram showing a configuration of a decoder in a conventional power supply selection circuit.

FIG. 16 is a timing chart for explaining an operation in a conventional power supply selection circuit.

FIG. 17 is a diagram showing a configuration of a conventional power supply selection circuit.

FIG. 18 is a diagram showing a configuration of a power supply selection circuit of a conventional example.

[Explanation of symbols]

101, 102 input terminal 103 output terminal 104, 105 P-channel MOS field effect transistor 301 power supply selection circuit 302, 303 input terminal 304 output terminal 305 power supply selection circuit 306, 307 input terminal 308 output terminal 309 power supply selection circuit 310, 311 input Terminal 312 Output terminal 401, 402 Input terminal 403 Output terminal 404, 405 N-channel MOS type field effect transistor 501, 502 Input terminal 503 Output terminal 504, 505 P-channel MOS type field effect transistor 701 Voltage source 702 Input terminal 703, 704 terminal 705 output terminal 706 booster circuit 707 power supply selection circuit 708 decoder group 901 voltage source 902 VCC system internal circuit 903 voltage source / signal line 904 power supply selection circuit 905 VPP system Department circuit

Claims (7)

(57) [Claims] A first input terminal connected to a source of the first field-effect transistor and a gate of the second field-effect transistor, and a second input terminal connected to the source of the second field-effect transistor and the source of the second field-effect transistor. A power supply selection circuit connected to a gate of a first field-effect transistor, and an output terminal connected to a drain of the first field-effect transistor and a drain of the second field-effect transistor. 2. The power supply selection circuit according to claim 1, wherein a substrate of the first field-effect transistor and a substrate of the second field-effect transistor are connected to the output terminal. 3. The power supply selection circuit according to claim 1, wherein a substrate of the first field effect transistor and a substrate of the second field effect transistor are not connected to the output terminal. 4. A first input terminal is connected to a source of the first field-effect transistor and a gate of the second field-effect transistor, and a second input terminal is connected to a source of the second field-effect transistor and the second field-effect transistor. Connected to the gate of the first field-effect transistor, connected to a voltage source to the first input terminal, connected to a booster circuit to the second input terminal, the output terminal of the first field-effect transistor A power supply selection circuit connected to a drain and a drain of the second field effect transistor. 5. A first input terminal is connected to a source of the first field-effect transistor and a gate of the second field-effect transistor, and a second input terminal is connected to the source of the second field-effect transistor and the second field-effect transistor. The first input terminal is connected to a first booster circuit, the second input terminal is connected to a second booster circuit, and the output terminal is connected to the gate of the first field-effect transistor. A power supply selection circuit connected to a drain of one field effect transistor and a drain of the second field effect transistor. 6. A first input terminal is connected to a source of the first field-effect transistor and a gate of the second field-effect transistor, and a second input terminal is connected to a source of the second field-effect transistor and the source of the second field-effect transistor. Connected to the gate of the first field-effect transistor, connected to a first voltage source to the first input terminal, and connected to a second voltage source also used as a signal input terminal to the second input terminal And an output terminal connected to the drain of the first field-effect transistor and the drain of the second field-effect transistor. 7. A first input terminal is connected to a source of the first field-effect transistor, a gate of the second field-effect transistor, a source of the third field-effect transistor, and a gate of the fourth field-effect transistor, A second input terminal is connected to the gate of the first field-effect transistor and the source of the second field-effect transistor, and a signal inverted to the polarity of the signal applied to the second input terminal is the third signal. A power supply provided to the gate of the field-effect transistor and the source of the fourth field-effect transistor, and having an output terminal connected to the drains of the first, second, third, and fourth field-effect transistors. Selection circuit.