JPH0528417B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a data communication processing device that transmits and receives data to and from an external device through a communication line, and also performs encoding processing of transmitted data and decoding processing of received data.

BACKGROUND ART As such a data communication processing device, there is a device that encodes image data and transmits it to an external device, and also receives encoded image data sent from an external device and decodes it into raw image data. be.

Conventionally, this type of data communication processing device has a bus 2 of a microprocessor 1, as shown in FIG.
A memory 3 that can store one or more pages of raw image data or encoded image data, an encoding/decoding circuit 4 that encodes or decodes image data, and between the memory 3 and the encoding/decoding circuit 4. DMA controllers 5 for DMA transfer are connected respectively,
Encoding/decoding circuit 4 as driver/receiver 6
It had a configuration in which it was connected to the communication line 7 via.

Encoded image data sent from an external device through the communication line 7 is input to the encoding/decoding circuit 4 via the driver/receiver 6, where it is decoded into raw image data and processed under the control of the DMA controller 5. Transferred to memory 3.

In the case of transmitting raw image data stored in the memory 3, the image data is transferred to the encoding/decoding circuit 4 and encoded under the control of the DMA controller 5, and transmitted via the driver/receiver 6 to the communication line. 7.

Problems to be Solved by the Invention However, with such a configuration, increasing the communication speed is not only technically difficult to achieve, but also makes the data communication processing device extremely expensive, making it uneconomical. There was a problem. This problem arises for the following reasons.

First, since data encoding or decoding is performed at the same time as transmission or reception, increasing the speed of the encoding/decoding circuit is essential to increasing communication speed, which is technically difficult to achieve. , and also involves a significant increase in cost.

Second, since encoding generally reduces the amount of data code, and conversely, decoding increases the amount of data code, assuming the transmission and reception communication speed is constant,
If the encoding/decoding circuit is made faster to accommodate the communication speed, the data transfer speed between the memory and the encoding/decoding circuit must be significantly increased, and in order to transfer the data, This is because expensive express buses and other services are required.

The present invention has been made in view of the above-mentioned problems, and is capable of realizing high-speed communication without increasing the speed of the encoding/decoding means and the data transfer means between this means and the storage means. The purpose is to provide a communication processing device.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention newly provides speed conversion means for buffering data transfer speed differences, connects this to a data storage storage means, and connects this to a data storage storage means. Transfer direction control means for controlling the data transfer direction in three directions is interposed between the encoding/decoding means connected to the storage means, the speed converting means, and the communication line, and the speed converting means data transfer between the storage means and the communication line via the encoding/decoding means, data transfer between the storage means and the communication line via the encoding/decoding means, and data transfer from the storage means to the speed conversion means and the communication line. The apparatus is equipped with a configuration that allows data to be transferred to the storage means via the encoding/decoding means.

Effects With the above-described configuration, the present invention can receive and decode data, or encode and transmit data as follows.

In the case of a reception decoding operation, first, the transfer direction control means controls the speed conversion means to enable data transfer between the speed conversion means and the communication line, and transfers the received data from the communication line to the storage means through the speed conversion means. Store it once. Next, the transfer direction control means controls to enable data transfer between the encoding/decoding means and the speed conversion means, and the received data is transferred from the storage means to the encoding/decoding means and decoded. and returns it to the storage means through the speed conversion means.

On the other hand, in the case of an encoded transmission operation, the transfer direction control means first controls the transmission direction control means so that data can be transferred between the encoding/decoding means and the speed conversion means, and transmits the transmission data from the storage means to the encoding/decoding means. It is transferred, encoded, and returned to the storage means via the speed conversion means. Next, the transfer direction control means enables data transfer between the speed conversion means and the communication line, and sends the encoded transmission data from the storage means to the communication line via the speed conversion means.

In this way, since it is possible to decode received data and encode transmitted data regardless of communication speed, it is possible to support high-speed communication without increasing the processing speed of the encoding/decoding means. . In addition, received data is encoded as encoded data, and transmitted data is encoded as encoded data.
Since it is possible to transfer data between the storage means and the communication line without going through a decoding means, the data transfer speed between the storage means and the storage means is much lower than when decoding or encoding is performed at the same time as receiving or transmitting. It is possible to support high-speed communication without increasing the speed.

Therefore, according to the present invention, a data communication processing device capable of high-speed communication can be provided at a relatively low cost.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic block diagram of a data communication processing device according to an embodiment of the present invention. This data communication processing device is connected to an external device 9 via a communication line 8, receives encoded image data from the external device 9, decodes it into raw image data, stores it internally, and also processes the raw image data stored internally. This encodes the image data and transmits it to the external device 9.

To explain the configuration of this device, 10 is a microprocessor (MPU) that performs overall control of this device, and 11 is an MPU bus. This MPU bus 11 includes a memory 12 having a storage capacity capable of storing one page or more of raw image data or encoded image data, an encoding/decoding circuit 13 for encoding or decoding data, and an MPU
A data rate conversion circuit 14 for buffering the data transfer rate difference between the bus 11 and the communication line 8, etc., and a DAM (direct memory access) between the memory 12 and the encoding/decoding circuit 13 or the data rate conversion circuit 14. DMA controller 15 that controls transfer
are connected to each other.

16 is a driver/receiver for the signal line 8, which connects the data rate conversion circuit 14 or the encoding/decoding circuit 13 via the data transfer direction control circuit 17.
connected to. This data transfer direction circuit 17 is
Data transfer direction can be controlled in three directions. That is, between the driver/receiver 16 and the data rate conversion circuit 14, the driver/receiver 1
Data transfer can be controlled to be performed either between the encoder/decoder 6 and the encoder/decoder circuit 13 or between the encoder/decoder circuit 13 and the data rate conversion circuit 14.

Note that there is also a memory for storing the program of the microprocessor 10, but it is omitted in the figure.

The operation of the data communication processing device configured as described above will be described below.

First, a reception/decoding operation and an encoding/transmission operation when the communication speed is low will be explained. In this case, the microprocessor 10 controls the data transfer direction control circuit 1 through the encoding/decoding circuit 13.
7 is controlled so that data transfer is performed between the encoding/decoding circuit 13 and the driver/receiver 16.

In encoded transmit operations, the microprocessor 10
sets the read start address and data amount of the transmission data in the DMA controller 15, and then activates the encoding/decoding circuit 13. The encoding/decoding circuit 13 issues a DMA transfer request when a certain amount of free space is available in the internal buffer, and transmits data (raw image data) under the control of the DMA controller 15.
is transferred from the memory 12 to the encoding/decoding circuit 13. This transmission data is encoded/decoded by the encoder/decoder circuit 1.
3 and transferred to the driver/receiver 16 via the data transfer direction control circuit 17,
It is transmitted to external equipment 9 via communication line 8 .

Note that the direction of data transfer is designated by the microprocessor 10 to the encoding/decoding circuit 13.

In the reception/decoding operation, received data (encoded image data) from the external device 9 is transferred from the data transfer direction control circuit 17 to the encoding/decoding circuit 13, decoded into raw image data, and encoded/decoded. It is stored in the internal buffer of the decoding circuit 13. When a certain amount of data is accumulated, the encoding/decoding circuit 13
A DMA transfer request is issued, and the received data is transferred to the memory 12 under the control of the DMA controller 15. The write start address is set in advance in the DMA controller 10 by the microprocessor 10.

Next, the operation when the communication speed is high will be explained.
In the encoded transmission operation, first, the transmitted data (raw image data) stored in the memory 12 is encoded. That is, microprocessor 1
0 specifies the data transfer direction for the encoding/decoding circuit 13 and the data rate conversion circuit 14, and starts them up. The data transfer direction control circuit 17 includes the data rate conversion circuit 14 and the encoding/transfer direction control circuit 17.
A direction control signal from the decoding circuit 13 controls the transfer direction so that data can be transferred between the data rate conversion circuit 14 and the encoding/decoding circuit 13. Note that the microprocessor 10 determines the readout start address and data amount of the transmission data,
and a write start address are set in the DMA controller 15.

When a certain amount of space becomes available in the internal buffer of the data rate conversion circuit 14, a DMA transfer request is generated.
Memory 1 under the control of the DMA controller 15
2, the transmission data is transferred to the data rate conversion circuit 14. The data rate conversion circuit 14 sequentially transfers the transmission data accumulated in an internal buffer to the encoding/decoding circuit 13 at a transfer rate matching that rate. The transmission data is encoded by the encoding/decoding circuit 13 and stored in an internal buffer of the encoding/decoding circuit 13. When a certain amount of data (encoded transmission data) accumulates in the internal buffer, a DMA transfer request is generated from the encoding/decoding circuit 13, and the data is transferred to the memory 12 under the control of the DMA controller 15.

When the encoding process of the transmission data is completed in this way, the microprocessor 10 specifies the transfer direction to the data rate conversion circuit 14 and starts it up. The data transfer direction control circuit 17 connects the data rate conversion circuit 14 and the driver/receiver 1 according to the direction control signal from the data rate conversion circuit 14.
Control is performed to enable data transfer between the computer and the computer. Note that the reading start address of the encoded transmission data is set in the DMA controller 15 by the microprocessor 10.

The data rate conversion circuit 14 issues a DMA transfer request when a certain amount of space becomes available in the internal buffer.
Transfer of transmission data is received by the DMA controller 15. Then, the transmission data accumulated in the internal buffer is transferred to the driver/receiver 17 in accordance with the data transfer speed of the communication line 8.

In the case of reception, the microprocessor 10 specifies the data transfer direction to the data rate conversion circuit 17 and activates it. The storage start address of received data is also set in the DAM controller 15. The data transfer direction control circuit 17 controls the transfer direction so that data is transferred between the driver/receiver 16 and the data rate conversion circuit 14 in accordance with the direction control signal from the data rate conversion circuit 14.

Received data (encoded image data) from the external device 9 is accumulated in the internal buffer of the data rate conversion circuit 14, and when a certain amount of data is accumulated, a DMA transfer request is issued from the data rate conversion circuit 14, and the data is transferred to the DMA. The data is transferred to the memory 12 under the control of the controller 15.

When the storage of the received data in the memory 12 is completed in this way, the decoding process is performed. The microphone processor 10 sets the read start address, data amount, and write start address of the received data in the DMA controller 15, and also specifies the data transfer direction to the data rate conversion circuit 14 and the encoding/decoding circuit 13, and starts them up. Can be applied. The data transfer direction control circuit 17 includes the data rate conversion circuit 14 and the encoding/decoding circuit 13.
The transfer direction is controlled so that data is transferred between the encoding/decoding circuit 13 and the data rate conversion circuit 14 according to a direction control signal from the encoder/decoder 13 .

In response to a DMA transfer request from the encoding/decoding circuit 13, the received data is transferred to the encoding/decoding circuit 13, decoded, and transferred to the data rate conversion circuit 14 under the control of the DMA controller 15. Accumulated in internal buffer. When a certain amount of decoded received data is accumulated, a DMA transfer request is issued from the data rate conversion circuit 14, and the decoded received data is transferred to the memory 12 under the control of the DMA controller 15.

Although the encoding/transmitting operation and the receiving/decoding operation have been described so far, it is of course possible to transmit/receive raw image data to/from the external device 9. In this case, data is transmitted and received between the memory 12 and the communication line 8 via the data rate conversion circuit 14.

In this embodiment, the encoding/decoding circuit 13 and the data rate conversion circuit 14 are connected to the MPU bus 11.
Although the memory 12 is connected to the memory 12 via a bus, the connection may be made via other buses or separate connection paths.

Furthermore, although this embodiment deals with image data, the present invention can be similarly applied to similar devices that deal with data other than image data.

Effects of the Invention As is clear from the above description, the present invention provides an encoding/decoding means by having a configuration that can perform decoding of received data and encoding of transmitted data regardless of communication speed. Since it is possible to support high-speed communication without significantly increasing the processing speed and the data transfer speed with the storage means, it has the effect of realizing a data communication processing device capable of high-speed communication at a relatively low cost. It is.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a data communication processing device according to an embodiment of the present invention, and FIG. 2 is a schematic block diagram of a conventional data communication processing device. 8...Communication line, 10...Microprocessor (MPU), 11...MPU bus, 12...Memory,
13... Encoding/decoding circuit, 14... Data rate conversion circuit, 15... DMA controller, 16
...Driver/receiver, 17...Data transfer direction control circuit.

Claims (1)

[Claims] 1 A storage means for storing data, an encoding/decoding means for encoding or decoding data connected to the storage means, and a data transfer rate difference connected to the storage means. a speed converting means for buffering, a transfer direction control means for controlling the data transfer direction in three directions, interposed between the encoding/decoding means, the speed converting means and the communication line; data transfer between the storage means and the communication line via the speed conversion means, and data transfer between the storage means and the communication line via the encoding/decoding means. and a data communication processing device that enables data transfer from the storage means to the storage means via the speed conversion means and the encoding/decoding means.