JPS62271159A - Data base equipment for video tex - Google Patents

Abstract

PURPOSE:To send an excellent picture even from an inexpensive personal computer by providing a control circuit having a RAM in a central processing circuit and each line. CONSTITUTION:The central processing circuit 31 and a control circuit 3 having a RAM of a capacity for at least share of one picture for each plural lines are provided. In supplying a retrieval request from a line 6 to the central processing circuit 31, the retrieval request is outputted from the central processing circuit to the personal computer 1 and the data read through the retrieval of a storage device 2 is written in the RAM 35 of a line to which, the retrieval is requested through the personal computer. Thus, the content of the RAM applied with the write is sent to the line 6 sequentially. Even when the personal computer with slow speed is used, the data is easily and quickly sent to plural terminal equipments.

Description

[Detailed description of the invention]

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a database device for videotex using a so-called personal computer. [Summary of the Invention] The present invention relates to a database device for videotex, and by providing a central processing circuit and a control circuit having a RAM for each line, it is possible to send out a good screen even with an inexpensive personal computer. be. [Prior Art] Videotex database devices have conventionally been comprised of systems larger than so-called minicomputers. As a result, the price of the entire system became four-valued, making it difficult for individuals to own it, for example. In response to this, it was considered to construct a database using an inexpensive so-called personal computer. However, the processing speed of such personal computers is slow, making it especially difficult to send data continuously to multiple terminals, and the number of lines that can be connected is limited. That is, in general, the transmission of retrieved data in this type of videotex is performed in units of 16 bits or 8 bits, and if the transmission rate is 4800 hps, the transmission time for 8 bits, for example, is about IJaa. On the other hand, if the number of connected lines is 8, for example, the device must scan all 8 lines in the above-mentioned 1.6 seconds, and if search mode is added to this, the so-called Processing was impossible at the speed of a personal computer. Therefore, a blank space of 1 byte is generated during transmission, making continuous and rapid transmission difficult, and as a result, the number of lines to be connected is limited to a smaller number. (Problems to be Solved by the Invention) As mentioned above, in the conventional technology, when a videotex database device is configured with a so-called personal computer, there are problems such as inability to send data in a good manner. [Means for solving the problem] The present invention includes a storage device (2) to which a plurality of lines (6) are connected and which stores a large number of meat surfaces, and a search/retrieval system for the large number of screens.
A videotex database device provided with a personal computer (1) for controlling reading, comprising a central processing circuit (31) and a RAM (35) with a capacity for at least one screen for each of the plurality of lines. Control circuit (
3) is provided, and the search request from the line (6) is sent to the central processing line II! 3 (31), a search request is output from the central processing circuit to the personal computer (1), and the data read out by searching the storage device 1\(2) is sent to the personal computer through the personal computer. This is a database device for videotex in which the contents of the RAM (35) of the line for which a search request has been made are written, and the contents of the RAM that have been stored are sequentially sent to the line (6). [Operation] According to this, a control circuit having a central processing circuit and a RAM for each line is provided, and data retrieved by a personal computer is written to the -IJ RAM and sent from there to each line. Therefore, even if a slow personal computer is used, data can be easily and quickly sent to multiple terminals. [Example] In FIG. 1, fll is a personal computer (P
C), a hard disk device (2) as an image storage device is connected to this PC (11), and the image (image) of the requested file number is searched and read out according to the search request described later. The data for one screen is sent to the communication control circuit (3)
is supplied to Here, this control circuit (3) is provided with a central processing circuit (CPU) (31), a ROM (32) and a RAM (33) used for the operation of this CPU (31), and furthermore, this CPU (31). ) data bus (34)
line RAM (35a) for the number of lines connected to
(35b)... are connected. Furthermore, this line RA
M has bytes, for example, 64 bytes, which is sufficiently larger than one screen's worth of rLIj image data read from the disk device (2).
(Note that the amount of image data for one screen of communication is approximately 30 bytes). Furthermore, this line RAM (35a) (35b)
”..., each line memory (36a) (36b) has a storage capacity that is sufficiently larger than one packet of image data, for example 256 bytes (the data amount of one packet is approximately 100 bytes)... are connected, and this memory (36a) (36b
)... control circuits (37a) (37b)... for performing DMA reading are connected to the memories (36a) (36b), respectively.
Parallel-to-serial conversion circuit (P/S) (38a) for performing parallel-to-serial conversion and addition of error correction codes, etc., for sending out to the line, respectively.
(38b)" is connected. And this P/S (38a) (38b)...
The output of ... is the transmitter/receiver circuit (modem) (4a
) (4b)..., line connection circuit (5a) (
5b)... is connected to a switching network provided with a plurality of lines (6). In addition, this line (6) is connected to the connection circuit (5a) (5b), modem (4a), respectively.
(4b) Serial-to-parallel conversion circuit (S/P) for performing serial-to-Haralel conversion and error correction through... (39a) (39b)
... is connected to this S/P (39a)
The outputs of (39b)... are connected to the data bus (34). Furthermore, FIG. 2 shows in detail one line (unit control section (30)) of the communication control circuit (3), in which data from the data bus (11) of the PC (1) is transmitted to the first switch ( 4
1) is supplied to the line RAM (35) through one fixed contact, and data from this line RAM (35) is supplied to the CPU (35) through the other fixed contact of the switch (41).
31) is supplied to the data bus (34). Data from this data bus (34) is supplied to the line memory (36) through one fixed contact of the second switch (42), and data from this line memory (36) is supplied to the other switch (42). is supplied to the internal data bus (43) through the fixed contacts of the
) is supplied to P/5 (38). In addition, the switches (41) (42) and the control circuit (37) are controlled by signals from the control bus (44) of the CPU (31), and the switching of the switches and the line memory (36) to the P/S (38) At the same time, the control circuit (37) is supplied with the 1d signal from the data bus (43), and the signal from the control circuit (37) is transferred to the data bus (34). Supplied. Further, the °ζ S/P (39) is controlled by the signal from the control bus (44), and the signal from the modem (4) is supplied to the data bus (34). Further, signals from the control bus (44) are supplied to the data bus (11), and data is mutually communicated between the data buses (11) and (34). The operation of this device is performed, for example, as shown in the flownayat of FIG. First, A in the figure shows the operation of the CPU (31). In this figure, when the operation is started, it is determined in step (1) whether or not there is data input to the port, and if there is no input, this step [1] is repeated. Here, the human power port is supplied with data from the above-mentioned line (6), interrupt signals from the PC (11), control circuit (37), data signals from the data latch, etc., which will be described later. When data is entered into , the first step [
This data is read in step [2], and then the number of the line to which the data corresponds is detected in step [3], and the registers used for the operation are selected according to the detected number. Actions are performed on a line-by-line basis. Furthermore, the data manually generated in step [4] is transferred to the line (6).
It is determined whether the search request is from
], it is determined whether or not it is an interrupt signal from the PC (11), and at step [6], it is determined whether or not it is an interrupt signal from the control circuit (37). In this case, other processing is performed in step [1], and further, in step [8] it is determined whether or not one piece of machine glue has been completed.
If the search request is input from line (6), the operation is terminated. If the operation is not terminated, the process returns to step [1]. Also, when a search request is input from line (6), the request is processed in step [2]. The file number of the l!!3i image is read, the line number requested in step [3] is detected, and the steps start from step [4].

Proceed to [9]. and step

At [9] it is determined whether or not the PC (11gari) is in progress, and if it is not in progress, step [
At step [10], the first switch (41) is switched to the PC (1) side, and at step [11], an image search/read instruction is supplied to the PC+1), and at step [12], the read file number and The line number is sent to the PC (11) and returned to step [8].

If the PC is in operation in [9], the file number and line number are latched to R'AM (33), etc. in step [13], and then the file number and line number are latched to R'AM (33) etc. in step [8].
]. On the other hand, in PCtl), when the operation is started as shown in B in the figure, it is determined in step [31] whether there is an instruction from the CPU (31), and if there is no instruction, this step [31] is repeated. . And the above step [11]
When the instruction from step [12] is supplied, the file number and line number from step [12] are accepted in step [32], and the image file with that number is retrieved in step [33]. Furthermore, the image data searched and read out in step [34] and L indicating the total data amount of this image data.
The value is written to the line RAM (35) through the switch (41). Then, in step [35], the CPU (31)
The final γ interrupt (g is sent, and in step [36]
A confirmation signal from the PU (31) is judged, and if confirmed, the process returns to step [31]. Further, when the end interrupt signal from the PC (1) is supplied to the input port of the CPU (31), the line number is detected in step [3], and the process proceeds from step [5] to step [14]. Then, in step [14], a confirmation signal is sent to the PC (1), and in step [15], the switch (41
) (42) is switched to the CPU (31) side, and in step [16] the L value of the line RAM (35) is read out and written to a register in the RAM (33), for example. Furthermore, in step [17], Baga Nodo number 16 is cented. Here, the image data is divided into packets each corresponding to, for example, one line of the sign, and each packet contains 14-value data indicating the amount of data. Therefore, in step [18], the contents of the above-mentioned L value register are set to L=L-11, and in step [19], the line RAM (
The data of the first packet in 35) is sent to the switch (4
1) Written to line memory (36) through (42). Then, in step [20], the end of writing is determined, and when the writing is completed, the second switch (42) is switched to the data bus (43) side in step [21], and the control circuit A read instruction is supplied to (37) and the process returns to step [8]. Here, the control circuit (37) is composed of, for example, a hardware logic circuit, and when a read instruction is given from the CPU (31), the value of li in the line memory (36) is first read, and then this 11 line memory of several minutes
The data of (36) is read out to P/5 (38), and then the input signal of readout path γ is sent to CPU (31). Furthermore, the control circuit I is sent to the input port of the CPU (31).
When the termination interrupt signal is supplied from jpK (37), the line number is detected in step [3], and the process proceeds from step [6] to step [23]. And step [2
3], a confirmation signal is sent to the control circuit (37), and in step [24] it is determined whether or not the contents of the L value register are 0. If not, the switch (41) is sent in step [25]. (42) is switched to the CPU (31) side, and in step [26] packet No. 1 i=i+l
Then, the process proceeds to step [18] described above. Further, when L=O in step [24], the process proceeds to step [8]. In this way, the image data from the hard disk device (2) is sent to the line (6), but according to the above-mentioned device, a RAM for one screen is provided for each line, and this RAM
Since all image data is transmitted using the CPU, the burden on the personal computer is extremely small, inexpensive equipment can be used, and multiple lines can be easily connected. It can be carried out. Note that existing programs can be used for operating programs such as searching, reading, and writing to RAM for the personal computer. Furthermore, as described above, since the burden on the personal computer is reduced, for example, other processing may be performed when there is no instruction from the CPU. In addition, in the above-described CPU operation, the data latch in step [13] latches a plurality of data in order,
Each time a personal computer completes its operation, the order is determined. Further, interrupts from the personal computer and the control circuit may be executed when other processing is stopped midway through so-called interaction processing. Furthermore, the start end is the start and end of the entire operation of the database device, and the end of step [8] corresponds to the database termination operation, and also includes an initial set immediately after the start and a stop operation immediately before the end. It is something that [Effects of the Invention] According to this invention, the central processing circuit and the RAM for each line are
A control circuit is installed to write the data retrieved by the personal computer into one RAM and then send it to each line, so even if a slow personal computer is used, the data can be sent to multiple terminals. It is now possible to easily and quickly transmit the data.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an example of the present invention, and FIGS. 2 and 3 are diagrams for explaining the same. (1) is a personal computer, (2) is a hard disk device, (3) is a communication control circuit, (6) is a line, (3) is a
1) is a central processing circuit, and (35) is a line RAM. Diagram 1 of the 6th edition of Juju Toxuke 1

Claims (1)

[Scope of Claim] A database device for a videotask, which is provided with a storage device to which a plurality of lines are connected and which stores a large number of screens, and a personal computer that controls searching and reading of the large number of screens, comprising: a central processing unit; circuit, and a RAM with a capacity of at least one screen for each of the above multiple lines.
A control circuit is provided having a control circuit, and when a search request from the line is supplied to the central processing circuit, the central processing circuit outputs the search request to the personal computer, and the storage device is searched and read. The database device for videotex is configured such that the data is written into the RAM of the line on which the search request is made through the personal computer, and then the written contents of the RAM are sequentially sent to the next line.