KR920003345B1 - Image data processing circuit - Google Patents

Abstract

The image data processing circuit processes image data input through number of channels using a direct memory access controller (DMA). The circuit includes a CPU for controlling the communication of facsimiles, a MODEMS (Mo1-Mo4) for modulating and demodulating the FAX signal, a DMA for controlling the memory access, memory units (MEM1,MEM2) for storing FAX image data, a second buffers (BUF21,BUF22) for communicating the output data of the memory units between the DMA and the MODEM, NAND gates (NA1,NA2) for decoding address signals transmitted from the CPU to generate enable signals for the second buffers, latches (LA1-LA4) for enabling the chip select signals (CS1-CS3) of the MODEM using data identification signals (INT0-INT3) of the DMA, and a multiplexer (MUX) for providing address signals to MODEMS.

Description

Image data processing circuit using DMA for multiple facsimile and interface

1 is a conventional circuit diagram.

2 is a circuit diagram according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data processing circuit in a facsimile, and more particularly, to image data processing that can process image data coming from multiple channels as a central processing unit using a director memory access controller (hereinafter referred to as " DMA "). It is about a circuit.

In general, it consisted of 1: 1 communication of terminal to terminal (FAX). Therefore, even without using DMA, even a single CPU could communicate. That is, conventionally, as shown in FIG. 1, data received through one channel of the switch 5 is received by the modem 3 and requested to the DMA in the central processing unit 1, and the data value in the modem 3 using the DMA. To the memory 4. At this time, the central processing unit 1 reads and analyzes the data in the memory 4 and processes it. Accordingly, it is difficult to process data coming from various channels in the related art, and an interrupt controller must be used to process the central processing unit alone, which causes a great deal of complexity and control of many circuit configurations. In addition, there is a problem in that the number of channels is limited to the DMA processing in the CPU.

Accordingly, an object of the present invention is to provide a circuit that can reduce the load on the central processing unit using an external DMA and transmit image data through a channel connecting a plurality of FAX terminals.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a circuit diagram according to the present invention, which communicates by switching a central processing unit (CPU) for controlling several FAX terminals (FAX1-FAXn) to control communication at the same time, and switching the FAX terminals (FAX1-FAXn). A switch (PSTN), a modem (M01-M04) for demodulating and demodulating a FAX signal transmitted and received through the private switch (PSTN), and a director memory for directly controlling memory access by receiving a bus control right from the CPU. An access controller (DMA), first buffers BUF11-BUF13 for buffering data input and output from the CPU, memory devices MEM1 and MEM2 capable of storing FAX image data, and the memory device. In the second buffer BUF21-BUF22 which buffers the output data of MEM1 and MEM2 to the direct memory access controller DMA and the modems M01-M04, and the director memory access controller DMA. Occurrence Receiving the address enable signal AEN and the asynchronous strobe signal ASTM, the address signal Aø of the CPU is decoded through the inverter N2 to enable the second buffers BUF21 to BUF22. NAND gates (NA1, NA2) generating the signal and the data recognition signal (DACKø-DACK3) from the director memory access controller (DMA) is provided to the modem (M01-M04) and the chip selector signal (CSø-CS3) ), The latch circuits LA1-LA4 for latching the interrupt signals INTø-INT3 are cleared, and the supply signal is gated from the data recognition signal DACKø-DACK3 of the director memory access controller DMA. A multiplexer (MUX) for generating a selection signal by inputting to (AN1) and selecting an address signal output from the CPU according to the selection signal and supplying the address signal to the address signals of the modem (M01-M04). do.

ø는

신호로 지적하게끔 처리했다. 모뎀(M01-M04)에서 DMA로 요구하는 것은 래치회로(M01-M04)를 거쳐서 나가게끔 구성되어 있다. DMA가 모뎀(M01-M04)으로부터 요구를 받아들이면 중앙처리장치(CPU)에게 버스 사용권을 요청해 허락을 받고,

신호로 모뎀(M01-M04)쪽에 동작을 하겠음을 알린다. 이때 요청된 래치는 없어지게 된다. DMA가 모뎀(M01-M04)의 데이타를 리드/라이트하게 되면 모뎀(M01-M04)의 인터럽트가 디스에이블되고, 다시 새로운 데이타를 받을 준비를 하게 된다. FAX 통신에 있어서 데이타 처리를 구체적으로 살펴보면, DMA와 모뎀(M01-M04)과의 데이타 처리는 바이트 단위로 하고, 메모리장치(MEM1,MEM2)에 저장된 데이타를 중앙처리장치(CPU)가 분석처리하는 것은 워드(word)단위로 하게된다. 이것은 중앙처리장치(CPU)의 처리속도를 빠르게 해서 실행능력을 높이기 위함이다. 모뎀(M01-M04)으로부터 들어오는 바이트 데이타를 워드로 이루어진 메모리장치(MEM1,MEM2)에 쌓기 위해 제2버퍼(BUF21-BUF22)를 사용했다. 제2버퍼(BUF21-BUF22)는 모뎀(M01-M04)으로부터 들어오는 바이트 데이타들을 ＂하이＂ 또는 ＂로우＂로 나누어서 메모리장치(MEM1,MEM2)에 쌓게 된다.Therefore, a specific embodiment of the present invention will be described in detail with reference to FIG. 2, which is divided into reception and transmission states. First, a case of receiving data from a FAX terminal (FAX1-FAXn), the central processing unit (CPU) allocates the size of each memory device (MEM1, MEM2) for each channel, direct memory access controller (DMA) and modem The reception preparation is completed by putting the M01-M04 in the reception state. When an external FAX terminal (FAX1-FAXn) is connected through the PSTN network, communication starts from this time. The analog signal coming from the FAX terminals FAX1-FAXn is converted to digital at the modems M01-M04. The modems M01-M04 make a processing request to the DMA via the latch circuits LA1-LA4 upon receipt of the data. At this time, the DMA monitors the status of each channel and processes the data on the channel where the request comes in first. The DMA moves the digital data in the modems M01-M04 to the memory devices MEM1, MEM2. After all movement to the memory devices MEM1 and MEM2 is completed, the DMA tells the CPU to process the data entered into the memory devices MEM1 and MEM2. The same applies to the case of sending data to a FAX terminal (FAX1-FAXn). When the central processing unit (CPU) puts the DMA modem (M01-M04) in the transmission state and gives the DMA a command right, the DMA moves data to the modem (M01-M04) from the memory devices (MEM1, MEM2). Let's do it. At this time, the modems M01-M04 convert the digital data into analog data and send it to the FAX terminals FAX1-FAXn through the PSTN network. DMA can also be used as a cascode to handle the needs of more channels. There are two types of communication with the FAX terminals (FAX1-FAXn). One is the image data that you actually want to send and receive, and the other is the protocol data that first sets an appointment to send and receive image data. Both of these data come in through address 0 of the 16 registers controlled by CS? Of modems M01-M04. Since the address of the DMA side can only point to the addresses of the memory devices MEM1 and MEM2, the multiplexer (MUX) was used to designate the registers in the modems M01-M04. When any one of the four channels is active, the inputs in the multiplexer (MUX) are all ø, allowing the 0 register of each modem (M01-M04) to be pointed out.

ø is

It was pointed out as a signal. The request from the modems M01-M04 to DMA is configured to exit through the latch circuits M01-M04. When the DMA accepts a request from the modem (M01-M04), it asks the CPU to get a bus license and gets permission.

Signals the modem (M01-M04) to operate. At this time, the requested latch is lost. When the DMA reads / writes data of the modems M01-M04, the interrupts of the modems M01-M04 are disabled and ready to receive new data again. Looking specifically at the data processing in the FAX communication, the data processing between the DMA and the modems (M01-M04) is in bytes, and the central processing unit (CPU) analyzes the data stored in the memory devices (MEM1, MEM2). Is done in word units. This is to increase the execution speed by increasing the processing speed of the CPU. The second buffer BUF21-BUF22 is used to stack the byte data coming from the modem M01-M04 into the memory devices MEM1 and MEM2 made of words. The second buffer BUF21-BUF22 divides the byte data coming from the modem M01-M04 into " high & low " and stacks them in the memory devices MEM1 and MEM2.

The control of the second buffer BUF21-BUF22 enables the second buffer BUF21-BUF22 with an AEN signal generated when the DMA is operating, and causes an address to be loaded on the data bus of the DMA when an ASTB signal occurs. Therefore, when this ASTB signal is generated, the second buffers BUF21-BUF22 are disabled, and the buffer BUF21 is enabled when Aø = 1 by the address Aø, and the buffer BUF22 is enabled when Aø = ø. Let it open

As described above, the external DMA is used to reduce the load of the central processing unit and to simultaneously use multiple channels.

Claims (1)

In the facsimile image data processing circuit, a central processing unit (CPU) which controls several FAX terminals (FAX1-FAXn) to control communication at the same time, and a private exchanger which switches and communicates with the FAX terminals (FAX1-FAXn). (PSTN), modems (M01-M04) for demodulating and demodulating FAX signals transmitted and received through the private exchange (PSTN), and director memory access for directly controlling memory access by receiving bus control rights from the central processing unit (CPU). A controller (DMA), first buffers BUF11-BUF13 for buffering data input and output from the CPU, memory devices MEM1 and MEM2 capable of storing FAX image data, and the memory device ( A second buffer BUF21-BUF22 which buffers output data of MEM1 and MEM2 to the direct memory access controller DMA and the modems M01-M04, and the director memory access controller DMA. Receives the address enable signal AEN and the asynchronous strobe signal ASTM, and decodes the address signal Aø of the CPU through the inverter N2 to the second buffer BUF21-BUF22. The chip selector signal CSø- of the modems M01-M04 by using the NAND gates NA1 and NA2 for enabling the enable signal and the data recognition signals DACKø-DACK3 of the director memory access controller DMA. The latch circuits LA1-LA4 and the data of the director memory access controller DMA which enable CS3) and clear the output of the latch circuits LA1-LA4 that latch the interrupt signals INTø-INT3 with this signal. The director memory terminal is input to the AND gate AN1 to generate a selection signal, and the CS0 to CS3 is input to the AND gate AN1 to generate a selection signal, and the CPU is generated according to the selection signal. Select the address signal output from An image data processing circuit, characterized by consisting of a multiplexer (MUX) for supplying the address signal of the modem (M01-M04)

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