JPH05283364A - Method of forming plug-in longitudinal wiring - Google Patents

Abstract

PURPOSE:To prevent voids from occurring inside a plug when forming a plug, using a bracket tungsten, in longitudinal wiring process. CONSTITUTION:A connection hole for exposing an impurity diffusion layer 10a is born in the first interlayer insulating film 15, a p<+>-type polysilicon film 16, the second interlayer insulating film 17, and a close contact layer 18, and a WSi2 film 21 is made all over the surface, and it is plugged 20 by bracket tungsten. Since the WSi2 film 21 is excellent in step coverage, it becomes a favorable close contact layer, and voids are prevented from occurring in the plug 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a plug-in vertical wiring for electrically connecting wirings of an ultra-highly integrated semiconductor device, and more particularly, to a three-dimensional conductive layer for high density. Related to the formation of wirings that are arranged in a static manner.

[0002]

2. Description of the Related Art Ultra-high integration of semiconductor devices tends to progress more and more, and there is an increasing demand for a technology for realizing it. This can be seen clearly from the fact that the UV stepper is demanding an exposure technique (eg, KrF excimer laser) having a wavelength shorter than that of UV from g-line to i-line. These exposure techniques determine the so-called minimum dimension of the design rule. It is no exaggeration to say that the development of this exposure technology has promoted the miniaturization of the above-mentioned semiconductor devices.

On the other hand, the miniaturization is limited only by this exposure technique. That is, the minimum size of the exposure technique limits the device size, and thus the structure, and the cell area. Therefore, in order to achieve higher density using the current exposure technology, it is necessary to consider the three-dimensionalization of devices. For example, a trench cell which has once attracted attention in DRAM and a FIN structure which is now attracting attention are the most prominent ones.

By the way, this idea has begun to be applied to multilayer wiring. For example, Proceedings of the 38th Joint Lecture on Applied Physics in 1991, P691, 30p-
The plug-in vertical wiring process shown in W-8 is included. This technology is an active layer laminated device aiming for high density without depending on miniaturization, and the conductive layers for forming electrodes are three-dimensionally arranged, which has been an obstacle to high density of the conventional type area. This is to solve the drawback that the area of the wiring increases, and as shown in FIG. 11, a connection hole is formed in the insulating film 2, the upper wiring 3, and the insulating film 4 which are sequentially formed on the diffusion layer 1 as the lower wiring layer. This is a technique for connecting by opening 6 and embedding the plug 5 in the connection hole 6.

[0005]

However, when using this technique, the problem is what technique is used to form the plug 5. That is, considering the simplicity of the process, the selection W, the CVD technique or the like may be used, but in that case, as shown in FIG. 12, since the plugs 5 start to grow separately from only the conductor, the void 7 is formed. There is.

On the other hand, when using the blanket-W, an adhesion layer is required.

Accordingly, as shown in FIG. 13, when the adhesion layer 8 has a poor coverage, the blanket-type is also the same.
Voids are formed in the W film 9. Especially, in the plug-in vertical wiring, since the aspect ratio of the connection hole is large, it is easily predicted that this will be a problem.

The present invention was made in view of these problems, and aims to obtain a method of forming a plug-in vertical wiring in which a plug conductor can be embedded in a connection hole without generating a void. It is a thing.

[0009]

Therefore, according to the present invention, in order to electrically connect a lower layer wiring including a diffusion layer and at least one or more upper layer wiring formed thereon, the laying direction of the upper layer wiring is set. In the method of forming a plug-in vertical wiring in which a connection hole having a shape penetrating substantially perpendicularly to the hole is formed and the connection hole is filled with a conductor, a step of forming a metal silicide film on the entire surface before forming the plug is provided. Is the solution.

[0010]

According to the present invention, if metal silicide having a good step coverage, for example, WSi ₂ is formed on the entire surface in advance, this serves as an adhesion layer and a heat resistant barrier layer for the lower wiring and the plug material. Blanket plug-W
Even if it is formed by, the adhesion layer is sufficiently maintained. Further, WSi ₂ is formed with good coverage. Therefore, no void is generated even if the W plug is formed by blanket-W CVD.

Further, another function of the present invention is to form the metal silicide even when the structure in which the adhesion layer and the barrier layer are formed only on the diffusion layer and the adhesion layer is not formed on the side wall of the hole is used. In other words, when the blanket-W is formed later, the dependency of the growth lag time on the base is eliminated.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the method of forming the plug-in vertical wiring according to the present invention will be described below with reference to the embodiments shown in the drawings.

(Embodiment 1) FIGS. 1 to 7 are cross-sectional views of a principal part showing a process of forming a plug-in vertical wiring of this embodiment.

First, as shown in FIG. 1, a silicon substrate 1
At a predetermined position of 0, for example, an impurity diffusion layer 10a serving as a lower wiring layer formed of an n ⁺ region into which arsenic (As) is ion-implanted is formed.

Next, the ion (Ar ⁺ ) of argon, which is an inactive substance, is added to Ie16 / at an energy of 10 KeV, for example.
As shown in FIG. 2, ions are implanted with a dose amount of cm ² to obtain 80Å from the surface of the impurity diffusion layer 10a made of single crystal.
Of non-quality silicon layer 1
1 is formed.

Next, for example, a dry oxidation process (heat treatment at an O ₂ flow rate of 10 l / min. For 10 minutes) at 850 ° C. is performed, and as shown in FIG. 3, silicon is formed to a depth of, for example, 50 Å from the surface of the non-quality silicon layer 11. An oxide film 12 is formed, and then a titanium film 13 is formed on the silicon oxide film 12 by a method as shown in FIG.

After that, rapid thermal annealing (RT
A) is performed in an argon (Ar) atmosphere at 650 ° C. for 30 seconds to form the titanium silicide film 14. Then, the unreacted titanium film 13 is selectively wet-etched by immersing the wafer in ammonia-hydrogen peroxide mixture for 10 minutes (FIG. 4). Furthermore, in a nitrogen (N ₂ ) atmosphere, 90
Annealing is performed at 0 ° C. for 30 seconds to form a stable titanium silicide film 14 with low resistance.

Next, as shown in FIG. 5, a first interlayer insulating film (SiO ₂ ) 15 is formed on the substrate by atmospheric pressure CVD, for example, 3 times.
The film is deposited to a film thickness of 000 Å, and then a P ⁺ -polysilicon film 16 as an upper layer wiring 16 is formed by low pressure CVD, for example
Formed to a film thickness of 0 Å, and then again normal pressure CVD
The second interlayer insulating film (SiO ₂ ) 17 by, for example, 3000
Deposit to a film thickness of Å. Thereafter, as shown in the figure, on the second interlayer insulating film (SiO ₂₎ 17, a titanium (Ti) /
Titanium oxynitride (TiON) = 30 nm / 7
The 0 nm adhesion layer 18 is formed by the sputtering method.

Next, a wiring connection hole 19 is formed on the titanium silicide film 14 by dry etching. In this example, the connection hole radius was 0.5 μm.

Next, as shown in FIG. 7, a tungsten silicide (WSi ₂ ) film 21 which is a metal silicide film.
Are formed under the conditions shown below using a dichlorosilane process with good coverage.

○ Gas and its flow rate WF ₆ … 2.5 _SCCM SiH ₂ Cl ₂ … 200 _SCCM ○ Pressure… 40 Pa ○ Temperature… 680 ° C. Then, the wafer is put into a blanket tungsten CVD apparatus and the following two-stage CVD is performed. Connection hole for wiring 1
A plug 20 as shown in FIG.

(First-stage CVD) ○ Gas and its flow rate WF ₆ … 25 _SCCM SiH ₄ … 10 _SCCM ○ Pressure… 1.07 × 10 ⁴ Pa (80 Torr) ○ Temperature… 475 ° C. (second-stage CVD) ○ Gas and its flow rate WF ₆ … 60 _SCCM H ₂ … 360 _SCCM ○ Pressure… 1.07 × 10 ⁴ Pa (80 Torr) ○ Temperature… 475 ° C. In this embodiment, even if blanket tungsten is used, voids are formed in the plug 20. Can be prevented, and the reliability of the wiring can be improved.

(Second Embodiment) FIGS. 9 and 10 show a second embodiment.
FIG. 6 is a main-portion cross-sectional view showing the step of.

This example is similar to Example 1 except that the adhesion layer 18 is not formed, and has the same effect. In this embodiment, WS
The i ₂ film 21 functions as an adhesion layer and a barrier layer.

Although the embodiments have been described above, the present invention is not limited to these, and various design changes associated with the gist of the configuration can be made. For example, although tungsten silicide is used as the metal silicide film in the above embodiment, the present invention is not limited to this.

[0026]

As is apparent from the above description, according to the present invention, it is possible to form a void-free plug even if blanket tungsten is used in the plug-in vertical wiring process. Therefore, there is an effect that a highly reliable next-generation device can be generated.

[Brief description of drawings]

FIG. 1 is a sectional view of an essential part showing a process of a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a main part showing the process of the first embodiment of the present invention.

FIG. 3 is a cross-sectional view of the essential parts showing the process of the first embodiment of the present invention.

FIG. 4 is a cross-sectional view of the essential parts showing the process of the first embodiment of the present invention.

FIG. 5 is a cross-sectional view of a main part showing the process of the first embodiment of the present invention.

FIG. 6 is a cross-sectional view of the essential parts showing the process of the first embodiment of the present invention.

FIG. 7 is a cross-sectional view of a main part showing the process of the first embodiment of the present invention.

FIG. 8 is a cross-sectional view of the essential parts showing the process of the first embodiment of the present invention.

FIG. 9 is a sectional view of a key portion showing a step of a second embodiment of the present invention.

FIG. 10 is a sectional view of a key portion showing a step of a second embodiment of the present invention.

FIG. 11 is a sectional view of a main part of a conventional example.

FIG. 12 is a sectional view of a main part of a conventional example.

FIG. 13 is a sectional view of a main part of a conventional example.

[Explanation of symbols]

10a ... Impurity diffusion layer 14 ... Titanium silicide film 15 ... First interlayer insulating film 16 ... P ⁺ -polysilicon film 17 ... Second interlayer insulating film 18 ... Adhesion layer 19 ... Wiring connection hole 20 ... Plug 21 ... Tungsten silicide film

Claims (1)

[Claims] 1. In order to establish an electrical connection between a lower layer wiring including a diffusion layer and at least one or more upper layer wiring formed thereon, the lower layer wiring has a shape penetrating substantially perpendicularly to the laying direction of the upper layer wiring. A method of forming a plug-in vertical wiring in which a connection hole is formed and a conductor is filled in the connection hole, the method including the step of forming a metal silicide film on the entire surface before forming the plug. Method.