JPH0438877A - Semiconductor device and manufacture method thereof - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device which is flat on the surface and small in its area by burying a source/drain region, a gate insulation film, and a gate electrode or its part at least into a semiconductor substrate, and laying out them so that they may conform to the main side of the substrate. CONSTITUTION:A control electrode 7 of a MOS transistor is formed on the surface of a semiconductor substrate 1 so that it may be buried partially or wholly under the surface, thereby forming a channel section 6, where the MOS transistor performs its transistor action, partially or wholly under the surface of the substrate. The control electrode is selectively deposited partially or wholly based on selective chemical vapor reaction so that the surface of the semiconductor device may be flattened. A source (drain) 5, insulation films 2, and 2' and a wiring layer 8 are installed, but they are not limited to this construction. A metal film selection deposition process based on Al or the like is effective to form a control electrode in a groove and hence attain the evenness of the surface of the semiconductor device, which makes it possible to embody a MOS transistor, which is small in its area and flat on the surface. It is, therefore, possible to obtain a high speed and high reliability MOS transistor.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor integrated circuit devices such as memory photoelectric conversion devices and signal processing devices installed in various electronic devices, and methods for manufacturing the same, and particularly relates to transistor structures thereof. It is.

[Prior Art] In recent years, efforts toward higher integration have led to the development of MOS transistors with gate lengths on the order of submicrons, and the practical use of microfabricated functional elements has been desired.

14 to 16 are schematic cross-sectional views showing the structure of a conventional MOS transistor. Figure 14 shows gate 2
01. Oxide film 202. Source 203 and drain 20
It has the simplest structure among N-MOS transistors with a single drain structure, and the manufacturing process is also simple. However, as miniaturization progresses and the gate length becomes approximately 1.2 μm or less, the operation of the MOS transistor deteriorates due to hot carriers. In order to prevent this, FIG. 15 shows a structure in which lightly doped regions 205 and 206 are provided to relax the electric field between the source and drain.
This is called an opened drain structure.

Furthermore, as an LSI for DRAM, which is the most advanced in miniaturization, the thin transistor cell (TT
C) is proposed. TTC is a semiconductor substrate 211
A trench is provided in the wafer, and a transistor and a capacitor are formed at the same time. That is, a gate oxide film 213 is provided within the trench, and a channel portion 214 is located on the side surface of the gate oxide film 213. Polycrystalline 5i 215 is in the groove at the bottom of the gate 212.
is filled and deposited to form an electrode of a memory capacitor, and its surface is oxidized to form a dielectric film 216 for the capacitor. A buried source 217 is formed on top of the polycrystalline 5i 216. In addition, word line 2 made of polycrystalline Si
18. N4 diffusion layer 21 as drain and bit line
9, and is electrically separated from adjacent cells by a separating cell 220. Insulating film 2211 interlayer insulating film 2
22, there are wiring patterns 223 and 224, respectively.
is formed. Since this TTC has MOS transistors and capacitors formed vertically, it has a small area and is less likely to malfunction due to the influence of the a-line (in addition, it has the advantage of not having any extraneous transistors).

[Problems to be Solved by the Invention] However, the trench type transistor cell described above still has room for improvement in the following points.

1) Even if we look only at the transistor part, the aspect ratio (groove depth/opening diameter) is about 2, so the Si
Defects caused by etching lower the yield, and furthermore, it is difficult to uniformly form a high-quality insulating film in the trenches, resulting in reliability problems.

2) Furthermore, the resistivity of polycrystalline silicon, which is a control electrode material commonly used in TTC, cannot be reduced to less than approximately 1 mΩcm even if impurities are diffused to the maximum extent, which reduces the propagation and delay time that determines the speed of the transistor. I couldn't do that. Silicide instead of polycrystalline silicon (SL
Even if metal alloys are used, the resistivity is approximately 100 to 200 μΩ.
cm, it was not possible to obtain a high-speed, high-yield, and highly reliable transistor.

3) Furthermore, since the control electrode is generally deposited uniformly on the surface of the semiconductor device, the surface of the control electrode reflects the unevenness of the groove itself, which is contrary to planarization. In other words, in order to maintain high reliability of the wiring deposited on the control electrode, the insulating film on the control electrode must be thickened and planarized using a technique called etch-back.

In this method, a thick resist is left only in the recesses, and the insulating film in the resist recesses is simultaneously removed in RF plasma.Since the influence of RF on MOS transistors is extremely large, there is a risk of lowering yield and reliability.

An object of the present invention is to solve these technical problems and provide a semiconductor device having a small area and a flat surface.

[Means for Solving the Problems] In order to achieve such an object, a semiconductor device according to the present invention includes a semiconductor device including a transistor having source and drain regions made of a semiconductor, a gate insulating film, and a gate electrode region. In the device, the source and train regions, the gate insulating film, and the gate electrode region are juxtaposed in a direction along the main surface of the base, and at least a portion thereof is embedded in the base. Features.

A manufacturing method according to the present invention is a method for manufacturing a semiconductor device including a transistor having source and drain regions made of a semiconductor, a gate insulating film, and a gate electrode region. The method is characterized by comprising the steps of: burying a portion of the semiconductor substrate; and arranging the source and drain regions and the gate electrode region in a direction along the main surface of the substrate.

[Function] According to the present invention, since the control electrode is buried from the surface to the bottom of the semiconductor substrate, an MO with a small area and a flat surface can be formed.
An S transistor can be realized, and therefore a high-speed and highly reliable MOS transistor can be obtained.

[Example] The present invention will be described below, but the present invention is not limited to the Examples described below, and any configuration that can achieve the five objects of the present invention may be used.

FIG. 1 is a sectional view illustrating a preferred embodiment of the present invention. In the present invention, a part or all of the control electrode 7 of a MOS transistor is buried from the surface of a semiconductor substrate l, and the transistor operation of the MOS transistor is improved. A part or all of the channel portion 6 is formed below the surface.

Furthermore, the present invention selectively deposits part, all, or all of the control electrode by selective chemical vapor phase reaction to form a flat surface of the semiconductor device.

The example embodiment shown in FIG. 1 includes a source (drain) 5.
Although the insulating films 2, 2' and the wiring layer 8 are shown, as mentioned above, the present invention is not limited to such a structure.

A metal film selective deposition method such as Aρ is effective in forming a control electrode in the groove and achieving flatness of the surface of the semiconductor device.

<1-Description of CVD method> Below, 1-CVD method will be explained with a focus on deposition within the openings, but this can be applied as appropriate according to the technical idea of the present invention, and here, the explanation will be given to the method formed by this method. This will help you understand that the quality of the film is good.

(Film Forming Method) A film forming method suitable for forming the electrode according to the present invention will be described below.

This method is a film forming method suitable for filling the openings with a conductive material in order to form the electrodes having the above-described structure.

A film forming method suitable for the present invention is one in which a deposited film is formed on an electron-donating substrate by a surface reaction using an alkyl aluminum hydride gas and hydrogen gas (
(hereinafter referred to as 1-CVD method).

In particular, a high-quality AQ film can be deposited by using monomethylaluminum hydride (MMAH) or dimethylaluminum hydride (DMAH) as a raw material gas, using H2 gas as a reaction gas, and heating the substrate surface under a mixed gas of these gases. I can do it. Here, in the case of 1-selection deposition, the surface temperature of the substrate is raised to a temperature higher than the decomposition temperature of the alkyl aluminum hydride by direct heating or indirect heating.
It is preferable to maintain the temperature below 50°C, more preferably between 260°C and 440°C.

Methods for heating the substrate to the above temperature range include direct heating and indirect heating, and in particular, if the substrate is maintained at the above temperature by direct heating, a high quality Al2 film can be formed at a high deposition rate. For example, the substrate surface temperature during film formation is set to a more preferable temperature range of 260°C to 440°C.
At this time, a high-quality film can be obtained at a deposition rate higher than that in the case of resistance heating, which is 300 to 5000 people/minute. Examples of such a direct heating method (energy from a heating means is directly transmitted to the substrate to heat the substrate itself) include lamp heating using a halogen lamp, a xenon lamp, or the like. In addition, there is resistance heating as a method of indirect heating, which is carried out using a heating element etc. provided on a substrate support member disposed in a space for forming a deposited film to support a substrate on which a deposited film is to be formed. I can do it.

By applying the CVD method to a substrate in which electron-donating and non-electron-donating surface areas coexist, AQ can be achieved with good selectivity only for electron-donating surface areas.
A single crystal of is formed. This AQ has excellent properties desired as an electrode/wiring material. That is, a reduction in the probability of hillock occurrence and a reduction in the probability of alloy spike occurrence are achieved.

This is because high-quality AQ can be selectively formed on a surface made of a semiconductor or conductor as an electron-donating surface, and because l has excellent crystallinity, it can form a eutectic layer with the underlying silicon, etc. It is thought that the formation of alloy spikes due to the reaction is hardly observed or extremely small. When used as an electrode in a semiconductor device, effects that go beyond the concept of the conventionally considered l-electrode and that were not anticipated by conventional techniques can be obtained.

As mentioned above, it was explained that l deposited on an electron-donating surface, for example, in an opening formed in an insulating film and exposing the surface of a semiconductor substrate, has a single crystal structure, but according to this person's ρ-CVD method, It is possible to selectively deposit the following metal films containing l as a main component, and the film exhibits excellent properties.

For example, in addition to alkyl aluminum hydride gas and hydrogen, SiH<, 5iJa, 5isHs, 5L(CH
s) <, 5iCj24.5iHsCI2*, 5i)
Gas containing SL atoms such as ICε1, TiCJ24,
TiBr4. Gases containing Ti atoms such as Ti(CHs)4, bisacetylacetonatocopper Cu (C-8702), bisdipivaloyl methanite copper Cu (C++H+eO□)
2. Bishexafluoroacetylacetonatocopper Cu (C
Gases containing Cu atoms such as sHFaOa)i are introduced in appropriate combinations to create a mixed gas atmosphere, for example, AN-5j, Al2-Ti, AQ-CuAjl!
Electrodes may be formed by selectively depositing conductive materials such as -5i-Ti and AA-5i-Cu.

In addition, since the Al-CVD method is a film forming method with excellent selectivity and the surface properties of the deposited film are good, a non-selective film forming method is applied to the next deposition step. By forming AQ or a metal film containing AQ as a main component on the selectively deposited ρ film and SiO□ as an insulating film, it is possible to form gold R which is highly versatile and suitable for wiring of semiconductor devices.
membrane can be obtained.

Specifically, such metal films are as follows: 0 selectively deposited AQ, AQ-31, Al2-Ti, A
l2-Cu, Al2-3i-Ti, A(2-Si
-Al2, Al2-Si deposited non-selectively with Cu,
Al2-Ti, Al2-Cu, Al2-5i-Ti, A
For example, a combination with ff-Si-Cu.

As a film forming method for non-selective deposition, go to 〇-C described above.
There are CVD methods, sputtering methods, etc. other than the VD method.

(Film Forming Apparatus) Next, a film forming apparatus suitable for forming the electrode according to the present invention will be described.

FIGS. 2 to 4 schematically show a continuous metal film forming apparatus suitable for applying the film forming method described above.

As shown in FIG. 2, this continuous metal film forming apparatus includes a load lock chamber 311 connected to each other by gate valves 310a to 310f so as to be able to communicate with each other while shutting off outside air, and a CVD reaction chamber as a first film forming chamber. 312, Rf etching chamber 313, sputtering chamber 314 as a second film forming chamber,
Each chamber is configured to be evacuated and depressurized by exhaust systems 316a to 316e, respectively. Here, the load lock chamber 31
Reference numeral 1 denotes a chamber for replacing the substrate atmosphere before the deposition process with an H2 atmosphere after exhausting in order to improve throughput performance. The next CVD reaction chamber 312 is a chamber in which selective deposition is performed on the substrate by the above-mentioned Al-CVD method under normal pressure or reduced pressure, and the substrate surface to be deposited is heated at a temperature of at least 200°C to 40°C.
A substrate holder 31g having a heating resistor 317 that can be heated in a range of 50° C. is provided inside the substrate holder 31g, and a bubbler 31 is installed indoors by a CVD source gas introduction line 319.
A raw material gas such as alkyl aluminum hydride which has been bubbled and vaporized with hydrogen is introduced at 9-1, and hydrogen gas as a reaction gas is introduced from a gas line 319. The next Rf etching chamber 313 is a chamber for cleaning (etching) the surface of the substrate after selective deposition in an Ar atmosphere. Holder 320 and Rf etching electrode line 32
1 and an Ar gas supply line 32.
The zero-order sputtering chamber 314 to which No. 2 is connected is a chamber for non-selectively depositing a metal film on the surface of a substrate by sputtering in an Ar atmosphere, and has an internal temperature of at least 200°C to 200°C.
A substrate holder 323 heated in a range of 50°C and a target electrode 32 to which a sputter target material 324a is attached.
4 is provided, and an Ar gas supply line 325 is provided.
is connected. The last load lock chamber 315 is an adjustment chamber before the substrate is exposed to the outside air after the metal film deposition is completed.
It is configured to replace the atmosphere with N2.

FIG. 3 shows another configuration example of a continuous metal film forming apparatus suitable for applying the above-described film forming method, and the same parts as in FIG. 2 described above are given the same reference numerals. The device shown in FIG. 3 differs from the device shown in FIG. 2 in that it is equipped with a halogen lamp 330 as a direct heating means and can directly heat the surface of the substrate. A claw 331 is provided to hold it in the correct position.

With this configuration, by directly heating the substrate surface, it is possible to further improve the deposition rate as described above.

As shown in FIG. 4, the metal film continuous forming apparatus having the above configuration actually includes the load lock chamber 311, the CVD reaction chamber 312, the Rf etching chamber 313, the sputtering chamber 314, and the transfer chamber 326 as a relay chamber. Load lock chamber 31
It is substantially equivalent to a structure in which 5 are interconnected. In this configuration, the load lock chamber 311 also serves as the load lock chamber 315. As shown in the figure, the transfer chamber 326 is provided with an arm 327 as a transfer means that can rotate forward and backward in the AA force direction and extend and contract in the BB force direction.
This arm 327 allows the substrate to be transferred from the load rotor chamber 311 to the CVD chamber 312, the Rf etching chamber 313, the sputtering chamber 314, and the load lock chamber 315 in order according to the process without exposing it to the outside air, as shown by the arrows in FIG. It can be moved continuously.

(Film Forming Procedure) A film forming procedure for forming electrodes and wiring according to the present invention will be described.

FIG. 6 is a schematic perspective view for explaining a film forming procedure for forming electrodes and wiring according to the present invention.

First, I will explain the outline. A semiconductor substrate with openings formed in an insulating film is prepared, and this substrate is placed in a film forming chamber, its surface is maintained at, for example, 260°C to 450°C, and DMAH gas and hydrogen gas are mixed to form an alkyl aluminum hydride. Al2 is selectively deposited on the exposed portion of the semiconductor within the opening by thermal CVD in a mixed atmosphere. Of course, as mentioned above, by introducing a gas containing Si atoms etc., Al2-3
A metal film mainly composed of Aρ such as i may be selectively deposited.A metal film mainly composed of Aβ or Al2 may be selectively deposited on the l and insulating film selectively deposited by the zero-order sputtering method. to form. Thereafter, electrodes and wiring can be formed by patterning the non-selectively deposited metal film in a desired wiring shape.

Next, a detailed explanation will be given with reference to FIGS. 3 and 6. First, prepare the base. The substrate is prepared, for example, by forming an insulating film with openings of various diameters on a single-crystal Si wafer.

FIG. 6(A) is a schematic diagram showing a part of this base.

Here, 401 is a single crystal silicon substrate as a conductive substrate, and 402 is a thermally oxidized silicon film as an insulating film (layer). 403 and 404 are openings (exposed portions), each having a different diameter. 410 is a groove.

Referring to FIG. 3, the procedure for forming the 12 film which will become the electrode as the first wiring layer on the substrate is as follows.

First, the base body described above is placed in the load lock chamber 311. Hydrogen is introduced into this load lock chamber 311 as described above to create a hydrogen atmosphere. And exhaust system 316b
The inside of the reaction chamber 312 is evacuated to approximately 1 x 10-'' Torr. However, the degree of vacuum inside the reaction chamber 312 is I x 10
−”Aρ can be formed even if it is worse than Torr.

Then, the DMA bubbled from the gas line 319
Supply H gas. H2 is used as the carrier gas for the DMAH line.

The second gas line 319゛ is for H2 as a reaction gas, and H2 flows from this second gas line 319゛.
The reaction chamber 3 is opened by adjusting the opening degree of a slow leak valve (not shown).
12 to a predetermined value. A typical pressure in this case is approximately 1.5 Torr. DM from DMAH line
AH is introduced into the reaction tube. Total pressure approximately 1.5 Torr
, the DMAH partial pressure is approximately 5. OX 10-”Torr
shall be. Thereafter, the halogen lamp 330 is energized to directly heat the wafer. In this way, If is selectively deposited.

After a predetermined deposition time has elapsed, the supply of DMA)I is temporarily stopped. The predetermined deposition time of the Al2 film deposited in this process is the time required until the thickness of the flooded film on the SL (single crystal silicon substrate 1) becomes equal to the film thickness of 5ins (thermal oxidation silicon film 2). It is time and can be determined in advance through experiments.

At this time, the temperature of the substrate surface due to direct heating is approximately 270°C. According to the steps up to this point, the beta film 405 is selectively deposited inside the openings and grooves, as shown in FIG. 6(B).

The above process is referred to as a first film forming process for forming an electrode in a contact hole.

After the first film forming step, the CVD reaction chamber 312 is
6b until a vacuum level of 5×10-” Torr or less is reached. At the same time, the Rf etching chamber 313
is evacuated to below 5 x 10-'Torr. After confirming that the compartment has reached the above vacuum level, close the gate valve 3.
10C is opened, and the substrate is transferred to the CVD reaction chamber 31 by the conveying means.
2 to the Rf etching chamber 313, and close the gate valve 310c. The substrate is transferred to the Rf etching chamber 313, and the Rf etching chamber 313 is evacuated by the exhaust system 316c until a vacuum level of 10-6 Torr or less is reached.

After that, argon is supplied from the Rf etching argon supply line 322, and the Rf etching chamber 313 is
Maintain an argon atmosphere of 1 to 10-” Torr, Rf
Keep the etching substrate holder 320 at about 200°C,
Rf power of 100 W is supplied to the Rf etching electrode 321 for about 60 seconds to cause argon discharge in the Rf etching chamber 313. In this way, the surface of the substrate can be etched with argon ions to remove unnecessary surface layers of the CVD deposited film. In this case, the etching depth is approximately 100 metal degrees equivalent to the oxide. Here, the surface of the CVD deposited film was etched in an Rf etching chamber, but the CVD film on the substrate was transferred in a vacuum.
Since the surface layer of the film does not contain atmospheric oxygen, etc., Rf
You can't beat it even without etching. In that case, Rf
The etching chamber 313 functions as a temperature changing chamber for changing the temperature in a short time when the temperature difference between the CVD reaction chamber 12 and the sputtering chamber 314 is large.

After the Rf etching is completed in the Rf etching chamber 313, the flow of argon is stopped and the argon in the Rf etching chamber 313 is exhausted. Rf etching chamber 31
After the sputtering chamber 314 is evacuated to 5 x 10-' Torr and the sputtering chamber 314 is evacuated to below 5 x 10-' Torr, the gate valve 310d is opened. Thereafter, the substrate is transported from the Rf etching chamber 313 to the sputtering chamber 3 using a conveying means.
14 and close the gate valve 310d.

After transporting the substrate to the sputtering chamber 314, the sputtering chamber 3
14 to 10-1 to 1O as in the Rf etching chamber 313.
-Torr argon atmosphere is created, and the temperature of the substrate holder 323 on which the substrate is placed is set to about 200 to 250°C. Argon is then discharged with a DC power of 5 to 10 kW, and target materials such as A[ and Aρ-Si (Si: 0.5%) are scraped with argon ions.
This process is a non-selective deposition process in which a metal such as Si is deposited on a substrate at a deposition rate of about 10,000 people/minute. This is called a second film forming step for forming wiring to connect to the electrodes.

After forming about 5000 metal films on the substrate, the flow of argon and the application of DC power are stopped.

After the load lock chamber 311 is evacuated to 5×10-” Torr or less, the gate valve 310e is opened and the substrate is moved. After the gate valve 310e is closed, N and gas are flowed into the load lock chamber 311 until atmospheric pressure is reached. Open the gate valve 310f and take the substrate out of the enclosure!

According to the second AJ2 film deposition step described above, an Aβ film 406 can be formed on the 5i02 film 402 as shown in FIG. 6(C).

Then, by patterning this ^i film 406 as shown in FIG. 6(D), wiring in a desired shape can be obtained.

(Experimental Example) The superiority of the Al-CVD method described above and the high quality of the l deposited in the openings will be explained below based on experimental results.

First, the surface of an N-type single crystal silicon wafer as a substrate was thermally oxidized to form 8,000 SiO□ and 0.25 μm×
A plurality of openings with various diameters ranging from 0.25 LLm square to 1100 u x 100 μm square were patterned to expose the underlying Si single crystal. (Samples) A film was formed using the Al-CVD method under the following conditions. DMAH was used as the raw material gas, hydrogen was used as the reaction gas,
Total pressure 1.5 Torr, DMA8 partial pressure 5.0×
Under the common condition of 10-' Torr, film formation was performed by adjusting the amount of power supplied to the halogen lamp and setting the substrate surface temperature in the range of 200° C. to 490° C. by direct heating.

The results are shown in Table 1.

As can be seen from Table 1, the substrate surface temperature due to direct heating is 2.
Above 60° C., Aρ was selectively deposited within the open pores at a high deposition rate of 3000-5000 per minute.

When we investigated the characteristics of the 19 films inside the openings in the range of substrate surface temperature from 260°C to 440°C, we found that there was no carbon content, resistivity was 2.8 to 3.4 μΩcan, reflectance was 90 to 95%, 1
It was found that the hillock density of .mu.- or more was O.about.10, and it had good characteristics with almost no spike occurrence (probability of failure of a 0.15 .mu.l junction).

On the other hand, when the substrate surface temperature is 200°C to 250°C,
Although the film quality was slightly worse than in the case of 260° C. to 440° C., it was a fairly good film from the perspective of the prior art, but the deposition rate was 1000 to 1500 persons/min, which was by no means sufficiently high.

In addition, when the substrate surface temperature is 450°C or higher, the reflectance is 60% or less, and the hillock density of 1 μm or more is 10 to 10'.
cm-”, alloy spike occurrence is 0 to 30%,
The properties of the Aρ membrane within the apertures were degraded.

Next, it will be explained how the method described above can be suitably used for openings such as contact holes and through holes.

That is, it is preferably applied to contact hole/through hole structures made of the materials described below.

A ^ρ film was formed on a substrate (sample) having the structure described below under the same conditions as when forming 1 on sample 1-1 described above.

A silicon oxide film as a second substrate surface material is formed by CVD on the single crystal silicon as the first substrate surface material, and buttering is performed by a photolithography process to partially cover the single crystal silicon surface. I made it vomit.

At this time, the thickness of the thermally oxidized SiO film was 8,000 mm, and the exposed area of single crystal silicon, that is, the size of the opening, was 0.25 μm.
[1,25μI11-100μso×100μm. Sample 1-2 was prepared in this way. (Hereinafter, such a sample will be referred to as "CVD5iO□ (hereinafter abbreviated as SiO□)/single crystal silicon").

Sample 1-3 is a boron-doped oxide film (hereinafter abbreviated as BSG)/single crystal silicon formed by atmospheric pressure CVD, and Sample 1-4 is a phosphorus-doped oxide film (hereinafter abbreviated as PSG)/ Sample 1-5 is a phosphorus- and boron-doped oxide film (hereinafter referred to as BSPG)/single-crystal silicon deposited by atmospheric pressure CVD; Sample 1-6 is a nitride film deposited by plasma CVD (hereinafter referred to as P- Sample 1-7 is a thermal nitride film (hereinafter abbreviated as T-5iN)/single crystal silicon, Sample 1-8 is a nitride film (abbreviated as T-5iN)/single crystal silicon formed by low pressure CVD.
Sample 1-9 is a nitride film (hereinafter referred to as EC
R-3iN)/single crystal silicon.

Furthermore, samples 1-11 to 1-179 (note: sample number 1-1
0.20.30.40.50.60.70.80.90
．． 100, 110.120, 130.140, 1
50, 160.170, are missing numbers). Single crystal silicon (single crystal Si) as the first base surface material,
Polycrystalline silicon (polycrystalline Si), amorphous silicon (amorphous Si), tungsten (W), molybdenum (Mo
), tantalum (Ta), tungsten silicide (W
Si), titanium silicide (TiSi), aluminum (Aρ), aluminum silicon (AJ2-3i
), titanium aluminum (Aρ-Ti), titanium nitride (Ti-N), copper (Cu), aluminum silicon copper (AI2-3i-Cu), aluminum palladium (Aβ-Pd), titanium (Ti), molybdenum silicide (Mo-5t) and tantalum silicide (Ta-3i) were used. The second substrate surface material is T-StO*+SzO, BSG.

PSG, BPSG, P-3iN, T-SiN
, LP-SiN, and ECR-SiN, such as 0 or more, were also able to form good A° C. films comparable to the above-mentioned sample 1-1.

Next, on the substrate on which Aβ was selectively deposited as described above, A° C. was non-selectively deposited and patterned by the sputtering method described above.

As a result, the A℃ film produced by sputtering and the Aρ film selectively deposited inside the openings have good electrical and mechanical durability due to the good surface properties of the l film inside the openings. It was in contact status.

(The following is a blank space) Example 1 FIG. 7 shows an 8MO3 transistor as an example of the present invention. FIG. 7(a) shows an NMOS transistor 3 formed in the area surrounded by the P-well I+field oxide film 2.
The plan view of FIG. 7(b), (c) and (d) is
A-A', B-B' and c in FIG. 7(a), respectively.
It is a sectional view along the -c' line.

Source of this NMOS l-transistor 4. The drains 5 are arranged at separate positions in a plane, and a gate oxide film 6 is arranged adjacent to each of the source 4 and the drain 5 in a vertical direction from the surface of the substrate to the bottom. source 4. adjacent to and from the substrate surface. drain 5
The gate electrode (control electrode) 7 is buried deeper (towards the bottom), and the space between the source 4 and the drain 5 is the region where the transistor operates, called the channel 9. The surface of the transistor is the control electrode. It is almost flat because it is buried.

The surface of this transistor is covered with a glabellar insulating film 2' and a source 4. A metal wiring 8 such as Aβ is drawn out from the drain 5 and the gate electrode through a contact hole for drawing out the electrode. In the process of forming the metal wiring 8, in order to prevent Al2 from being buried in the contact hole, Aβ is applied only in the contact hole, that is, only on the semiconductor substrate.
An effective method is to selectively deposit a material, fill in a contact hole, and then deposit a wiring material over the entire surface of the insulating film and pattern it to form a wiring.

Next, the operation will be explained.

The MOS transistor according to the present invention is an element in which the conductance of a channel portion 9 between a source electrode 4 and a drain electrode 5 is controlled by a gate electrode 7.

When voltage v0 is applied between source electrode 4 and drain electrode 5, voltage ■ is applied to gate electrode 7. When added,■. 〈■
. -When in VT, ■. >Va-Vt, 1 W I++=-(ox・μH(Va-Vd"2
A current flows based on the formula L (Cox: gate capacitance, μ: carrier mobility, W: channel width, L: channel length, 7: threshold voltage).

What is currently required of MO5 transistors is 1) to build the transistor into a small area, and 2) to perform transistor operation at high speed.

The present invention has significantly improved the above two points, and the area of the transistor has been reduced to 80% of the conventional one. Regarding speed, a major factor is the resistance of the gate electrode. In the case of conventionally used polycrystalline Si gates, the resistance is 30 to 80 Ω/co'', and 2 to 5 Ω/cm'' is achieved by polyciding, but in the case of the present invention, the resistance is 30 to 80 Ω/co''. /cm" low resistance was achieved.The reason for this is that the metal electrode is directly embedded, and the
I2 has a single crystal structure, and since it is a buried type, it can be made sufficiently thick.

Embodiment 2 FIG. 8 is a plan view of another embodiment of the NMOS transistor according to the present invention. This embodiment is an example in which the overlapping portion between the gate electrode 7, the source electrode 4, and the drain electrode 5 is made small to reduce the capacitance in order to achieve even higher speed. That is, by changing the arrangement of the gate electrode 7, the capacitance could be reduced compared to the example shown in FIG. 7 while securing the channel.

Embodiment 3 FIG. 9 shows a plan view of still another embodiment 6 In this embodiment, the channel portion 9 was designed to prevent direct contact with the member constituting the gate electrode 7 via the insulating film 6. Polycrystalline Si
The gate electrode material is installed through the wires 10, etc. With this structure, it is possible to prevent the gate electrode member from directly diffusing into the insulating film, and by using polycrystalline Si, which is used in conventional processes, regardless of the work function of the gate electrode member, it is possible to achieve the same process as before. MO with the characteristics of
It was possible to obtain an S transistor, and furthermore, because the direct resistance of the gate electrode was significantly reduced, it was possible to obtain a fine and high-speed MOS transistor.

Embodiment 4 FIG. 10 is a plan view of still another embodiment of the present invention.
In this embodiment, in order to further reduce the parasitic capacitance between the gate electrode 7 and the P well 1 compared to the example shown in FIG.
The oxide film 11 in three directions around the opening in the buried portion of the gate electrode member is made thicker to thicken (reduce) the parasitic capacitance.

Next, a method of manufacturing the embodiment shown in FIG. 10 will be described. 11(a) to 11(g) show cross sections of the embodiment shown in FIG. 10 along line AA'.

First, a P well 102 was formed on an N substrate 101 using a conventional method, and an oxide film 103 having a thickness of 12,000 yen on the surface of the substrate was partially removed. (Figure 1(a)) Next, using 12,000 oxidized 119103 as a mask, C(2x, CBrF5
The substrate was etched by the RIE (reactive ion etching) method using the following gas to form a clear layer 104. The etching depth of the substrate is 3 μm. (FIG. 11(b)) Next, the oxide film 103 is removed, and a thickness of 100 mm is coated over the entire surface of the base.
A thermal oxide film 105 and a SiN film 106 are formed,
The SiN film was partially removed. (FIG. 11(C)) By the conventionally used LOCO3 method, the SiN film 10
A field oxide film 107 was formed only on the removed portions. Formation conditions are Oz: 2j2/min, H2: 4ρ/
The oxidation temperature was 1000°C and the film thickness was 8000°C.

After that, SiNM10B was removed. (Figure 11(d))
Next) After completely removing the oxide film 105 on the substrate in an IF atmosphere, a gate insulating film 10g was formed. The formation temperature was 850°C, and the film thickness was 180°C. As part of the gate electrode of the MOS transistor, polycrystalline 5i109 was deposited on the entire surface of the gate insulating film 108 by thermal decomposition of SiH4, and partially removed in RIE mode in a CCJ2Jg atmosphere. Further, in order to form a source/drain diffusion layer 110 of a MOS transistor, arsenic was ion-implanted at a rate of 5×10 ions/cm. In addition, arsenic is polycrystalline 5
It is also injected into i109 and also plays a role in lowering the resistivity of the polycrystalline SL. Next, in order to electrically activate the source/drain diffusion layer 110, heat treatment was performed at 1000° C. for 15 seconds by RTA (Rapid Thermal Annealing) method. (FIG. 11(e)) Next, place only on the polycrystalline 5i109.
111 was deposited.

The deposition method will be described below. First, the substrate is placed in the reaction chamber of the CVD apparatus, and the reaction chamber is heated to I x 10-'Torr.
It was exhausted to a certain extent. Then, DMAH was supplied from the supply gas line. Note that H2 was used as the carrier gas.

Furthermore, H2 as a reaction gas is supplied from another gas line at 27
It was poured onto a substrate heated to 0°C. Typical pressure in this case is approximately 1.5 Torr and the partial pressure of DMAH is approximately 5 Torr.
X 10-"Torr. According to this method, l is selectively deposited only on the conductive polycrystalline 5ilGe, and is not deposited on the oxide film 108 and the field oxide film 107. Therefore, Aj2111 is a MOS transistor. (FIG. 11(f))
) Next, BPSG was deposited as the glabellar insulating film 112, a contact hole 113 was opened to take out the electrode, and Afll 14 was embedded in the contact hole 113 by the above-mentioned 1-CVD method (FIG. 11(g)). ) In this way, the MOS transistor shown in FIG. 10 was manufactured.

Embodiment 5 FIG. 12 shows yet another embodiment. Figure 12 (
12(a) shows a plan view, and FIG. 12(b) shows an equivalent circuit.

This embodiment is an example in which two NMOS transistors are connected by a common gate electrode 7.

Example 6 FIG. 13 shows yet another example. Figure 13(a)
is a plan view, and (b) is a cross-sectional view. This embodiment is basically different from the embodiment shown in FIGS. 7 to 12 in that channel portions 11 and 12 are formed along the buried gate electrode 7 in a direction perpendicular to the substrate surface. The point is that When a voltage v0 is applied to the gate electrode 7, a current from the source 4 to the drain 5 flows in the direction of the arrow 14 and flows into the highly impurity region (n ”) 13. Further current flows through the channel 12 in the direction of the arrow 15 and into the train electrode 5, along the surface at the same time that the X flow has a current component flowing perpendicularly to the surface. 1st
There is also a component flowing in the direction shown by the arrow 16 in Figure 3 fa).

[Effects of the Invention] As explained above, according to the present invention, since the control electrode is embedded from the surface to the bottom of the semiconductor substrate, it is possible to realize a MOS transistor with a small area and a flat surface, which can be performed at high speed and A highly reliable MOS transistor can be obtained.

[Brief explanation of drawings]

FIG. 1 is a sectional view illustrating a preferred embodiment of the present invention, FIGS. 2 to 5 are views showing an example of a manufacturing apparatus preferable to apply the method of manufacturing a semiconductor device according to the present invention, and FIG. A first method of manufacturing a semiconductor device according to the present invention
A schematic perspective view for explaining the state of wiring layer formation, FIG. 7 is a plan view and a cross-sectional view of an embodiment of the present invention, and FIGS. 8 to 10 are plan views of other embodiments of the present invention, respectively. , FIG. 11 is a schematic sectional view illustrating the manufacturing method of the embodiment shown in FIG. 10, FIG. 12 is a plan view and an equivalent circuit diagram of still another embodiment of the present invention, and FIG. 13 is still another embodiment. A plan view and a sectional view of an embodiment of the present invention, and FIGS. 14 to 16 are sectional views of a conventional MOS transistor, respectively. 2... Field insulating film, 3... MOS transistor, 4... Source, 5... Drain, 6... Gate insulating film, 7... Gate, 8... Wiring, 9... ·channel. Figure 4 Figure 5 O Figure 8 Figure 104 O5 Figure 10 Toe O09 O14 m 7!12 Figure 15 Figure 16

Claims (1)

[Scope of Claims] 1) A semiconductor device including a transistor having source and drain regions made of a semiconductor, a gate insulating film, and a gate electrode region, wherein the source and drain regions, the gate insulating film, and the a gate electrode region;
are arranged in parallel in a direction along the main surface of a base, and at least a part of them is embedded in the base. 2) The semiconductor device according to claim 1, wherein a channel of the transistor is formed in a direction along a plane intersecting a main surface of the base, and carriers move in a direction along the main surface. 3) A semiconductor region is formed under the gate electrode region, and the source and drain regions are arranged across the gate electrode region.
The semiconductor device described in . 4) A method for manufacturing a semiconductor device including a transistor having a source and drain region made of a semiconductor, a gate insulating film, and a gate electrode region, wherein at least a portion of the source and drain region, the gate insulating film, and the gate electrode are made of a semiconductor. 1. A method for manufacturing a semiconductor device, comprising: embedding the source and drain regions in a base; and arranging the source and drain regions and the gate electrode region in a direction along a main surface of the base. 5) The resistivity of the member constituting the gate electrode is 10μ.
5. The method of manufacturing a semiconductor device according to claim 4, wherein a material having a resistance of Ωcm or less is used. 6) When forming the gate electrode region, the method includes the step of depositing Al or a metal containing Al as a main component by a CVD method using an alkyl aluminum hydride and hydrogen. A method for manufacturing a semiconductor device. (Margin below)