JPH01183855A - Mos transistor - Google Patents

Abstract

PURPOSE:To obtain the potential of a semiconductor layer section excellently and effectively by forming a conductive region connected to a channel region and capable of being connected to another fixed potential. CONSTITUTION:A gate electrode 13 is formed onto a semiconductor layer section 12 through a gate oxide film 14 while a source region 15 and a drain region 16 and a channel region 17 between these source region 15 and drain region 16 are shaped into the semiconductor layer section 12. A conductive region 18 being electrically connected to the channel region 17 and capable of being connected to another fixed potential is formed. That is, the conductive region 18 to the channel region 17 is shaped besides the channel region 17 between the source region 15 and the drain region 16. Accordingly, the potential of the semiconductor layer section 12 can be taken through the conductive region 18.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a MOS type transistor, and more particularly to an improved structure of a MOS type transistor in which each component is formed on an insulating substrate surface. be.

[Conventional technology]

FIG. 3 shows a schematic configuration of a conventional MOS type transistor of this type.

That is, in the conventional configuration shown in FIG. 3, reference numeral 1 indicates an insulating substrate, 2 indicates a p-type or n-type semiconductor layer portion formed on the upper surface of this insulating substrate 1, and 3 indicates this semiconductor layer portion 2.
A gate electrode is selectively formed on the upper surface of the gate oxide film 4, and 5 and 8 are gate electrodes formed on the upper surface of the gate oxide film 4.
A source region and a drain region are selectively formed by implanting n-type or p-type impurity ions into the semiconductor layer portion 2 from above until reaching the surface of the insulating substrate 1; is a channel region formed between these source region 5 and drain region 6.

Therefore, as you can see, the conventional MO
In the S-type transistor, as is well known, the current flowing between the source region 5 and the drain region 8 can be controlled by the potential applied to the gate electrode 3.

[Problem to be solved by the invention]

However, in the conventional example, MO
In the case of an S-type transistor, although basic transistor operation is possible as described above, the depth of the source region 5 and drain region 6 reaches the surface of the insulating substrate, so that the semiconductor layer portion 2 is not fixed, and as shown in the graph of drain current versus drain-source voltage characteristics in a MOS type transistor shown in Figure 4, the characteristics of the transistor are disturbed by the King effect. For example, when an inverter is formed using a CMOS configuration, there are disadvantages such as loss of gain characteristics of the inverter.

This invention is aimed at solving these drawbacks of the conventional technology.
The purpose of this is to create a transistor structure that can be constructed on an insulating substrate without impairing its characteristics. This type of MOS transistor,
The object of this invention is to provide a MOS type transistor constructed on an insulating substrate.

[Means to solve the problem]

In order to achieve the above object, a MOS type transistor according to the present invention selectively forms a gate electrode on a semiconductor layer portion formed on an upper surface of an insulating substrate via a gate oxide film, and In a MOS type transistor in which a source region, a drain region, and a channel region between these source and drain regions are selectively formed as desired, the transistor is electrically connected to the channel region, and It is characterized by providing a conductive region that can be connected to another fixed potential.

[For production]

That is, the MOS transistor according to the present invention includes a source region, a drain region, a channel region between the source region and the drain region, and a channel region in a semiconductor layer formed on an insulating substrate. Since a conductive region is provided that is electrically connected to the conductive region and can be connected to another fixed potential, the potential of the semiconductor layer portion can be taken through this conductive region.

〔Example〕

Hereinafter, one embodiment of a MOS transistor according to the present invention will be described in detail with reference to FIGS. 1 and 2.

1 and 2 are a longitudinal cross-sectional view from the front side and a perspective view of the overall appearance, respectively, schematically showing the general structure of a basic MOS type transistor to which this embodiment is applied.

That is, also in the structure of this embodiment shown in FIGS. 1 and 2, reference numeral 11 is an insulating substrate, and 12 is a p-type or n-type semiconductor layer portion formed on the upper surface of this insulating substrate 11. , 13 are formed on the semiconductor layer section 12 via the gate oxide film 14, and have widths and lengths selectively set from at least one side surface to a part of the top surface of the semiconductor layer section 12. The gate electrode is shown.

In addition, 15 and 16 implant n-type or p-type impurity ions into the semiconductor layer portion 12 from above the gate electrode 13 until they reach the surface of the insulating substrate 11, selectively as desired. A channel region 17 is formed between the source region 15 and the drain region 16.

Furthermore, 18 indicates a conductive region which is additionally formed in contact with the other side surface of the semiconductor layer portion 12 and is electrically connected to the channel region 17;
Reference numeral 18 denotes a terminal taken out from this conductive region 18 and connectable to an appropriate fixed potential (not shown).

Therefore, in the MOS type transistor of this embodiment constructed on the insulating substrate as described above, the potential applied to the gate electrode 13 causes the inside of the semiconductor layer portion 12 to be The current flowing between the source region 15 and the drain region 16, which are selectively formed as desired, can be controlled.

In particular, in the case of the structure of this first embodiment,
A conductive region 18 is additionally formed in contact with the other side surface of the semiconductor layer portion 12, and this conductive region 18 is connected to a channel region 17 formed between the source region 15 and the drain region 18. This conductive region 18. Furthermore, the channel region 17 is passed through the terminal 19 taken out from the conductive region 18.
It is possible to take the potential of the semiconductor layer section 12 under the .

Therefore, in this example, the MO3 type transistor structure constructed on the insulating substrate will be explained.

Since the potential of the semiconductor layer section 12 under the channel region 17 can be taken by the conductive region 18, the gain characteristics of the inverter can be changed, for example, when the inverter is formed using a CMOS configuration. This makes it possible to prevent the king effect that causes a decrease in performance.

In the above embodiments, the channel region is formed mainly on the side surface of the semiconductor layer, but the channel region may be formed mainly on the top surface of the semiconductor layer, or it may be formed mainly on the side surface. It may be formed so as to straddle the upper surface portion, and similar actions and effects can be achieved.

〔Effect of the invention〕

As described in detail above, according to the present invention, a gate electrode is selectively formed on a semiconductor layer formed on the upper surface of an insulating substrate via a gate oxide film, and a source region is formed in the semiconductor layer. and a conductive region connected to the channel region and connectable to another fixed potential in an MO3O3 type transistor in which a drain region and a channel region between these source and drain regions are selectively formed as desired. Since the structure is provided with a conductive region, the potential of the semiconductor layer below the channel region can be taken extremely well and effectively by the conductive region, and there is no risk of impairing the electrical characteristics of the device structure. Moreover, it has the advantage of being extremely simple in structure and easy to implement.

[Brief explanation of the drawing]

FIGS. 1 and 2 are a longitudinal cross-sectional view from the front side and a perspective view of the overall appearance, respectively, schematically showing the general configuration of a basic MOS transistor to which an embodiment of the present invention is applied; FIG. 3 is a longitudinal sectional view from the front side schematically showing the general structure of the conventional MOS type transistor, and FIG. 4 is a graph showing drain current versus drain-source voltage characteristics in the MO3 type transistor. 11... Insulating substrate, 12... Semiconductor layer portion, 13
...Gate electrode, 14...Gate oxide film, 15
...Source region, 1B...Drain region, 17
... Channel region, 18 ... Conductive region, 19.
...Same terminal. Agent Masuo Oiwa Figure 1 Figure 2 14; Lee''-) - Yunai Hire
1s; 4 e-plan 1pe Figure 3
Figure 4

Claims (1)

[Claims] A gate electrode is selectively formed on the semiconductor layer portion formed on the upper surface of the insulating substrate via a gate oxide film, and
In a MOS type transistor in which a source region, a drain region, and a channel region between these source and drain regions are selectively formed in the semiconductor layer portion as desired, electrically connected to the channel region. 1. A MOS type transistor, characterized in that it is provided with a conductive region that can be connected to another fixed potential.