JPH05243398A - Formation method of plug-in longitudinal interconnection - Google Patents

Abstract

PURPOSE:To prevent a void from being produced inside a plug when the plug is formed by using blanket tungsten in a longitudinal wiring process. CONSTITUTION:A titanium silicide film 14 is formed on the surface of an impurity diffusion layer 10a as a lower layer to be wired. A close contact layer 18 composed of Ti/TiON is formed on a second interlayer insulating film 17. Thereby, it is possible to prevent a void from being produced inside a plug 20 which is filled into a connecting hole for wiring use and which is composed of blanket tungsten.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a plug-in vertical wiring for electrically connecting the wirings of an ultra-highly integrated semiconductor device to each other, and more particularly to a three-dimensional conductive layer for high density. Related to the formation of wirings that are arranged in a static manner.

[0002]

2. Description of the Related Art Ultra-high integration of semiconductor devices tends to progress more and more, and there is an increasing demand for a technology for realizing them. This can be seen clearly from the fact that the UV stepper is demanding an exposure technique (for example, KrF excimer laser) having a wavelength shorter than that of UV from g-line to i-line. These exposure techniques determine the so-called minimum dimension of the design rule. It is no exaggeration to say that the development of this exposure technology has promoted the miniaturization of the above-mentioned semiconductor devices.

On the other hand, the miniaturization is limited only by this exposure technique. That is, the minimum size of the exposure technique limits the device size, and thus the structure, and the cell area. Therefore, in order to achieve higher density using the current exposure technology, it is necessary to consider the three-dimensionalization of devices. For example, a trench cell, which once attracted attention in DRAM, and a FIN structure, which is now attracting attention, are the most prominent ones.

By the way, this idea has begun to be adopted in multilayer wiring. For example, Proceedings of the 38th Joint Lecture on Applied Physics in 1991, P691, 30p-
The plug-in vertical wiring process shown in W-8 is included. This technology is an active layer laminated device aiming at high density without depending on miniaturization, and the conductive layers for forming electrodes are three-dimensionally arranged, which has been an obstacle to high density of the conventional type area. This is to solve the drawback that the area of the wiring increases, and as shown in FIG. 10, a connection hole is formed in the insulating film 2, the upper wiring 3, and the insulating film 4 which are sequentially formed on the diffusion layer 1 as the lower wiring layer. This is a technique for connecting by opening 6 and embedding the plug 5 in the connection hole 6.

[0005]

However, when using this technique, the problem is what technique is used to form the plug 5. That is, considering the simplicity of the process, the selection W, the CVD technique, or the like may be used, but in that case, as shown in FIG. 11, the plugs 5 start to grow separately from only the conductor, so that the void 7 is formed. There is.

On the other hand, when using the blanket-W, an adhesion layer is required.

Therefore, as shown in FIG. 12, if the adhesion layer 8 has a poor coverage, the blanket-type is also the same.
Voids are formed in the W film 9. Especially, in the plug-in vertical wiring, since the aspect ratio of the connection hole is large, it is easily predicted that a particular problem will occur.

The present invention was made in view of these problems, and aims to obtain a method of forming a plug-in vertical wiring in which a plug conductor can be embedded in a connection hole without generating a void. It is a thing.

[0009]

Therefore, in the present invention, in order to electrically connect the lower wiring layer and at least one upper wiring, a connection penetrating substantially perpendicularly to the laying direction of the upper wiring is provided. In a method of forming a plug-in vertical wiring in which a hole is opened and the connection hole is filled with a wiring conductor, a step of selectively forming a titanium silicide (TiSi ₂ ) layer on the lower wiring layer, and an interlayer insulating film The solution is to have a step of forming an adhesion layer on the top.

[0010]

If TiSi ₂ is formed on the lower wiring layer in advance, this serves as an adhesion layer and a heat-resistant barrier layer for the lower wiring layer plug material. Further, since the adhesion layer is formed on the interlayer insulating film, the adhesion is sufficiently maintained even if the plug is formed by the blanket-W, and the adhesion layer is not formed in the connection hole. The problem of is gone. Therefore, no void is generated.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the method of forming the plug-in vertical wiring according to the present invention will be described below with reference to the embodiments shown in the drawings.

(Embodiment 1) FIGS. 1 to 7 are sectional views of a principal part showing a process of forming a plug-in vertical wiring of this embodiment.

First, as shown in FIG. 1, a silicon substrate 1
At a predetermined position of 0, for example, an impurity diffusion layer 10a as a lower wiring layer formed of an n ⁺ region into which arsenic (As) is ion-implanted is formed.

Next, as shown in FIG. 2, ions (Ar ⁺ ) of argon, which is an inactive substance, are supplied with, for example, energy 10.
Ion implantation is performed at a dose of Ie16 / cm ^{2 with} KeV to obtain 80Å from the surface of the impurity diffusion layer 10a made of single crystal.
Of non-quality silicon layer 1
1 is formed.

Next, for example, a dry oxidation process (heat treatment at an O ₂ flow rate of 10 l / min. For 10 minutes) at 850 ° C. is performed, and as shown in FIG. An oxide film 12 is formed, and then a titanium film 13 is formed on the silicon oxide film 12 by a method as shown in FIG.

After that, rapid thermal annealing (RT
A) is performed in an argon (Ar) atmosphere at 650 ° C. for 30 seconds to form the titanium silicide film 14. Then, the unreacted titanium film 13 is selectively wet-etched by immersing the wafer in ammonia-hydrogen peroxide mixture for 10 minutes (FIG. 4). Furthermore, in a nitrogen (N ₂ ) atmosphere, 90
Annealing is performed at 0 ° C. for 30 seconds to form a stable titanium silicide film 14 with low resistance.

Next, as shown in FIG. 5, a first interlayer insulating film (SiO ₂ ) 15 is formed on the substrate by atmospheric pressure CVD, for example, 3 times.
The film is deposited to a film thickness of 000Å, and subsequently, a P ⁺ -polysilicon film 16 as an upper wiring is formed by a low pressure CVD method, for example, 200
Formed to a film thickness of 0 Å, and then again normal pressure CVD
The second interlayer insulating film (SiO ₂ ) 17 by, for example, 3000
Deposit to a film thickness of Å. Thereafter, as shown in the figure, on the second interlayer insulating film (SiO ₂₎ 17, a titanium (Ti) /
Titanium oxynitride (TiON) = 30 nm / 7
The 0 nm adhesion layer 18 is formed by the sputtering method.

Next, a wiring connection hole 19 is formed on the titanium silicide film 14 by dry etching. In this embodiment, the connection hole radius is 0.5 μm.

After that, the wafer is put into a blanket tungsten CVD apparatus, and a plug 20 as shown in FIG. 7 is formed in the wiring connection hole 19 by the following two-stage CVD.

(First-stage CVD) ○ Gas and its flow rate WF ₆ … 25 _SCCM SiH ₄ … 10 _SCCM ○ Pressure… 1.07 × 10 ⁴ Pa (80 Torr) ○ Temperature… 475 ° C. (second-stage CVD) ○ Gas and its flow rate WF ₆ … 60 _SCCM H ₂ … 360 _SCCM ○ Pressure… 1.07 × 10 ⁴ Pa (80 Torr) ○ Temperature… 475 ° C. In the present embodiment, even if blanket tungsten is used, voids are present in the plug 20. Can be prevented, and the reliability of the wiring can be improved.

(Embodiment 2) FIGS. 8 and 9 are sectional views of the essential part of this embodiment, which is an improved example of the first embodiment.

In this embodiment, as shown in FIG.
The adhesion layer 18 on the second interlayer insulating film 17 is provided with a wiring connection hole 19
Of the blanket tungsten CVD by the same method as in Example 1 above.
To form the plug 20. The above-mentioned overetch is an isotropic etching (for example, gas Cl ₂ = 5).
It can be performed at 0 _SCCM , a pressure of 6.7 Pa, and an output of 0.08 W / cm ² .

In the present embodiment, the adhesion layer 18 is overetched outside the opening edge of the wiring connection hole 19 so that blanket tungsten grows in the shoulder portion of the wiring connection hole 19 and becomes an overhang shape. Can be prevented, and the generation of voids can be further prevented.

Although the embodiments have been described above, the present invention is not limited to these, and various design changes associated with the gist of the configuration can be made.

[0025]

As is apparent from the above description, according to the present invention, it is possible to form a void-free plug even if blanket tungsten is used in the plug-in vertical wiring process. Therefore, there is an effect that a highly reliable next-generation device can be generated.

[Brief description of drawings]

FIG. 1 is a sectional view of an essential part showing a process of a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a main part showing the process of the first embodiment of the present invention.

FIG. 3 is a cross-sectional view of the essential parts showing the process of the first embodiment of the present invention.

FIG. 4 is a sectional view of a key portion showing a step of Embodiment 1 of the present invention.

FIG. 5 is a sectional view of a key portion showing a step of Embodiment 1 of the present invention.

FIG. 6 is a cross-sectional view of a main part showing the process of the first embodiment of the present invention.

FIG. 7 is a cross-sectional view of the essential parts showing the process of the first embodiment of the present invention.

FIG. 8 is a cross-sectional view of the essential parts of Embodiment 2 of the present invention.

FIG. 9 is a sectional view of a main part of a second embodiment of the present invention.

FIG. 10 is a sectional view of a main part of a conventional example.

FIG. 11 is a sectional view of a main part of a conventional example.

FIG. 12 is a sectional view of a main part of a conventional example.

[Explanation of symbols]

10a ... Impurity diffusion layer, 14 ... Titanium silicide film, 1
5 ... First interlayer insulating film, 16 ... P ⁺ -polysilicon film, 1
7 ... 2nd interlayer insulation film, 18 ... Adhesion layer, 19 ... Wiring connection hole, 20 ... Plug.

Claims (1)

[Claims] 1. A connection hole penetrating substantially perpendicularly to a laying direction of the upper layer wiring is formed in order to electrically connect the lower wiring layer and at least one upper layer wiring, and the wiring is formed in the connection hole. In a method of forming a plug-in vertical wiring for filling a conductor for use, titanium silicide (Ti) is selectively formed on the lower wiring layer.
A method of forming a plug-in vertical wiring, comprising a step of forming a Si ₂ ) layer and a step of forming an adhesion layer on the interlayer insulating film.