JPH05274871A - メモリ構造 - Google Patents

メモリ構造

Info

Publication number
JPH05274871A
JPH05274871A JP4318607A JP31860792A JPH05274871A JP H05274871 A JPH05274871 A JP H05274871A JP 4318607 A JP4318607 A JP 4318607A JP 31860792 A JP31860792 A JP 31860792A JP H05274871 A JPH05274871 A JP H05274871A
Authority
JP
Japan
Prior art keywords
memory
array
line
columns
decoder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4318607A
Other languages
English (en)
Japanese (ja)
Inventor
Tran Hiep Van
ブイ．トラン ヒープ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of JPH05274871A publication Critical patent/JPH05274871A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
JP4318607A 1991-11-27 1992-11-27 メモリ構造 Pending JPH05274871A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US79951591A 1991-11-27 1991-11-27
US799515 1991-11-27

Publications (1)

Publication Number Publication Date
JPH05274871A true JPH05274871A (ja) 1993-10-22

Family

ID=25176116

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4318607A Pending JPH05274871A (ja) 1991-11-27 1992-11-27 メモリ構造

Country Status (3)

Country Link
EP (1) EP0544247A3 (enExample)
JP (1) JPH05274871A (enExample)
TW (1) TW231386B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100499844B1 (ko) * 1996-07-11 2006-04-21 텍사스 인스트루먼츠 인코포레이티드 정렬데이타저장장치및본딩패드를구비한ｄｒａｍ구조

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5537346A (en) * 1994-05-20 1996-07-16 Samsung Electronics Co., Ltd. Semiconductor memory device obtaining high bandwidth and signal line layout method thereof
KR0164391B1 (ko) * 1995-06-29 1999-02-18 김광호 고속동작을 위한 회로 배치 구조를 가지는 반도체 메모리 장치
CN102497832B (zh) 2009-09-08 2015-09-09 显著外科技术公司 用于电外科装置、电外科器械的盒组件及其使用方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4656613A (en) * 1984-08-29 1987-04-07 Texas Instruments Incorporated Semiconductor dynamic memory device with decoded active loads
DE69129882T2 (de) * 1990-06-19 1999-03-04 Texas Instruments Inc., Dallas, Tex. Assoziatives DRAM-Redundanzschema mit variabler Satzgrösse

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100499844B1 (ko) * 1996-07-11 2006-04-21 텍사스 인스트루먼츠 인코포레이티드 정렬데이타저장장치및본딩패드를구비한ｄｒａｍ구조

Also Published As

Publication number Publication date
EP0544247A2 (en) 1993-06-02
TW231386B (enExample) 1994-10-01
EP0544247A3 (en) 1993-10-20

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