JPH05274248A - Direct memory access device - Google Patents

Abstract

PURPOSE:To save the trouble of the temporary stoppage of DMA transfer, the reset of a processing content and the restarting of DMA in the case of transferring DMA while switching the processing content in accordance with data. CONSTITUTION:A data monitoring block 203 is provided for DMA 201. The data monitoring block 203 discriminates whether information read out from a memory by a data reading block 202 is data or information showing the processing content. In the case of data, the piece of data is outputted to a data write-in block 205 after processing by a data processing block 204. In the case of information showing the processing content, the processing procedure on a program memory 206 is started by setting the piece of information to be a command so as to program-control the data processing block 204. Thus, since the processing content in DMA 201 can be switched in accordance with data, troubles of the temporary stoppage of DMA operation, the reset of the processing content and the restarting of DMA 201 are removed, and since program control is executed, comparatively advanced processing is possible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a direct memory access device (DMA) which directly accesses a memory and transfers the obtained data to a transfer destination device.

[0002]

2. Description of the Related Art Conventionally, DMA has been used in a data processing device such as a computer. FIG. 3 shows the configuration of a general data processing device.

The data processing apparatus shown in this figure comprises a memory 101, an I / O 102, a CPU 103 and a DMA 10.
5 is connected by a bus 104. Memory 1
When the data stored in 01 is to be transferred to the transfer destination device by writing to the I / O 102, the CP
U 103 issues a DMA transfer command to DMA 105. The DMA 105 directly accesses the memory 101 in response to this instruction and transfers the data on the memory 101 to the I / O 10
Write to 2. Therefore, the DMA 105 is the memory 101
Data transfer to / from I / O 102 and a plurality of memories 10
When 1 is used, it controls the transfer of data between the memories 101, and assists the CPU 103 to reduce the load and improve the processing speed.

[0004]

As described above, in the conventional method, the processing speed is increased by the DMA transfer and the CPU 10
The load reduction of 3 was realized. However, since the CPU 103 was executing the other processing, the clock frequency for determining the operating speed of the CPU 103 had to be increased in order to improve the processing speed. But the CPU
If the clock frequency of 103 is increased, the memory 101 cannot follow this.

A particular problem arises when the data in the memory 101 has to be subjected to a predetermined process in DMA transfer. That is, the transfer destination device is the memory 1
This is a case where the data on 01 cannot be received as it is and it is necessary to perform a predetermined process. In this case, the CPU 103 reads the data in the memory 101, performs a predetermined process, and then writes the data in the memory 101 again. Thereafter, the CPU 103 sends DM to the DMA 105.
A transfer command is given, and DMA transfer by the DMA 105 is performed. Therefore, in such a case, the speed of the memory 101 greatly affects the overall processing speed.

In order to solve such a problem, the applicant of the present application has previously proposed a configuration in which a DMA has a data processing function (Japanese Patent Application No. 4-45397). In this proposal, by providing the DMA with a data processing function, the need for data processing in the CPU 103 is eliminated, so that the processing result is not written in the memory 101. However, even in this case, there is a problem that the DMA operation must be temporarily stopped and restarted in order to switch the content of the data processing in the DMA for each data.

The present invention has been made to solve the above problems, and D
An object of the present invention is to eliminate the trouble of temporarily stopping the operation of the DMA and restarting after setting the processing content when changing the processing content in the MA.

[0008]

In order to achieve such an object, the DMA of the present invention is a block for directly reading information from a memory in response to a command from a processor and an information related to data of the read information. A block to which a predetermined process is applied, a block to write the processed data to the transfer destination device, and the information to be read, and if the read information is the information related to the data, it is provided to the above process. If the information is related to the processing content, a block for program-controlling the processing by using the information as a command is provided.

Further, the data processing apparatus of the present invention includes a memory in which data is stored together with information relating to processing contents, a processor for issuing a command to transfer the data in the memory to a transfer destination device, and the command. According to the present invention, which directly reads data from the memory and transfers it to the transfer destination device.
And are provided.

[0010]

In the DMA of the present invention, the DMA from the memory
The information read in is composed of data and commands. If it is data, the monitoring block provides this data for a predetermined process, and if it is a command, the process is program-controlled accordingly. Therefore, in the present invention, when the processing contents are switched according to the data, the trouble of temporarily stopping the DMA operation and restarting after resetting the processing contents becomes unnecessary,
Further, since the processing is program-controlled, it is possible to perform comparatively advanced processing.

Furthermore, the same operation can be obtained in the data processing device of the present invention.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a DMA according to an embodiment of the present invention.
2 shows the structure of information handled in this embodiment.

First, the DMA 201 shown in FIG. 1 includes a data reading block 202 and a data monitoring block 20.
3, a data processing block 204, a data writing block 205, and a program memory 206. The DMA 201 can be used, for example, in the data processing device shown in FIG.

The data reading block 202 reads the information stored in the memory 101 and supplies it to the data monitoring block 203 and the data processing block 204.
If the information read by the data reading block 202 is information relating to data, the data monitoring block 203 provides this for processing in the data processing block 204, and if it is information indicating the processing content, Program memory 206 using information as commands
Start the processing procedure (program) stored in
Program contents of the data processing block 204 are controlled. The data write block 205 I / Os the data processed in the data processing block 204.
Write to 102 and transfer to the transfer destination device.

The information 301 shown in FIG. 2 is composed of information 302 and data 303 indicating the processing contents of the data. Also, these information 302 and data 3
The first bit 304 of 03 is information 302 indicating the processing method.
Is a bit indicating whether or not
The former is "1" and the latter is "0". The data monitoring block 203 monitors the leading bit 304 to identify whether the information read by the data reading block 202 is the information 302 indicating the processing method or the data 303.

As described above, according to this embodiment, when it is necessary to switch the processing contents according to the data to be DMA-transferred, the DMA operation is temporarily stopped, the processing method is reset, and the DMA 201 is restarted. No need for labor. Therefore, the CPU 103 DMs a series of data 303 having different processing contents by issuing only one DMA transfer command.
A transfer is possible, and the processing speed is improved.

Further, according to this embodiment, the processing procedure on the program memory 206 is started by using the information 302 as a command for the processing content. Therefore, for example, the processing to be performed can be made relatively sophisticated as compared with Japanese Patent Application No. 4-67108, which was previously proposed by the applicant of the present application.

[0019]

As described above, according to the present invention,
Since the information read from the memory into the DMA is monitored and the processing content is switched according to the monitoring result and the processing is program-controlled, the DMA operation is temporarily stopped.
The trouble of resetting the processing contents and restarting the DMA is unnecessary, and the processing speed is improved. Further, the processing content can be made relatively sophisticated.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a DMA according to an embodiment of the present invention.

FIG. 2 is a diagram showing a structure of information handled in the present embodiment.

FIG. 3 is a block diagram showing a general configuration of a data processing device.

[Explanation of symbols]

 101 memory 102 I / O 103 CPU 201 DMA 202 data reading block 203 data monitoring block 204 data processing block 205 data writing block 206 program memory 301 information 302 processing method information 303 data 304 information 302 and the first bit of data 303

Front page continuation (72) Inventor Shoji Ishikawa 5-1-1, Shimorenjaku, Mitaka-shi, Tokyo Within Japan Radio Co., Ltd. (72) Inventor Yuuki Sudo 5-1-1, Shimorenjaku, Mitaka-shi, Tokyo Within Japan Radio Co., Ltd.

Claims (2)

[Claims] 1. A block for directly reading information from a memory in response to a command from a processor, a block for subjecting information relating to data in the read information to a predetermined process, and the processed data to a transfer destination device. The block to be written and the information to be read are monitored, and if the read information is information related to the data, the processing is provided, and if it is information related to the processing content, the processing is programmed using this as a command. A direct memory access device comprising: a control block. 2. A memory in which data is stored together with information relating to processing contents, a processor which issues a command to transfer the data in the memory to a transfer destination device, and information is directly read and transferred from the memory in response to the command. The direct memory access device according to claim 1, which transfers the data to a destination device, and a data processing device.