JPH05267540A - Packaging structure for semiconductor device - Google Patents
Packaging structure for semiconductor deviceInfo
- Publication number
- JPH05267540A JPH05267540A JP9578892A JP9578892A JPH05267540A JP H05267540 A JPH05267540 A JP H05267540A JP 9578892 A JP9578892 A JP 9578892A JP 9578892 A JP9578892 A JP 9578892A JP H05267540 A JPH05267540 A JP H05267540A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- substrate
- semiconductor device
- semiconductor package
- connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/328—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体素子の実装構造
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element mounting structure.
【0002】[0002]
【従来の技術】従来の実装構造は図3に示すように半導
体パッケージ7の端面に、内部半導体素子の信号線に個
々に導通した接続ランド6aと内部半導体素子の電源線
に個々に導通した接続ランド6bとを備えている。2. Description of the Related Art In the conventional mounting structure, as shown in FIG. 3, a connection land 6a is individually connected to a signal line of an internal semiconductor element and a connection is individually connected to a power line of an internal semiconductor element on an end surface of a semiconductor package 7. The land 6b is provided.
【0003】一方、実装基板1の端面に、接続ランド6
a,6bに相互接続される接続ランド2a,2bを備え
ている。On the other hand, the connection land 6 is provided on the end surface of the mounting substrate 1.
It has connection lands 2a and 2b interconnected to a and 6b.
【0004】そして、半導体パッケージ7と実装基板1
との接続ランド6a,2a,6b,2bを溶着接続部3
により接続していた。Then, the semiconductor package 7 and the mounting substrate 1
The connection lands 6a, 2a, 6b, 2b for connection with
Was connected by.
【0005】[0005]
【発明が解決しようとする課題】この従来の実装方法で
は、半導体素子の電源線を他の信号線と同様に半導体パ
ッケージから接続ランドとして個々に設けなければなら
ず、半導体素子の処理信号速度の増加とともに増える電
源端子の増加に対して、接続ランドの個数を増加させる
ことでしか対応できないという問題点があった。In this conventional mounting method, the power supply line of the semiconductor element must be individually provided as a connection land from the semiconductor package like other signal lines, and the processing signal speed of the semiconductor element can be reduced. There has been a problem that the increase in the number of power supply terminals, which increases with the increase, can be dealt with only by increasing the number of connection lands.
【0006】また、溶着接続部により半導体パッケージ
が実装基板と密着せず、半導体パッケージの放熱を実装
基板を介して行うことができないという問題点があっ
た。Further, there is a problem that the semiconductor package does not adhere to the mounting substrate due to the welded connection portion, and the heat dissipation of the semiconductor package cannot be performed through the mounting substrate.
【0007】本発明の目的は、接続ランドの個数を増加
させることなく、電源端子の増加に対処し、かつ放熱効
率を向上させた半導体素子の実装構造を提供することに
ある。An object of the present invention is to provide a mounting structure of a semiconductor device which copes with an increase in power supply terminals and improves heat dissipation efficiency without increasing the number of connection lands.
【0008】[0008]
【課題を解決するための手段】前記目的を達成するた
め、本発明に係る半導体素子の実装構造は、半導体パッ
ケージと、実装基板とを組合せてなる半導体素子の実装
構造であって、半導体パッケージは、内部半導体素子の
信号線に個々に導通した接続ランドと、内部半導体素子
の電源線に共通して接続した電源パターンとを端面に有
するものであり、実装基板は、前記電源パターンに相互
接続される電源パターンを端面に有し、前記接続ランド
に相互接続される接続ランドを端面より後退させて凹部
内に有するものである。In order to achieve the above object, a semiconductor element mounting structure according to the present invention is a semiconductor element mounting structure in which a semiconductor package and a mounting board are combined. A connection land that is electrically connected to the signal line of the internal semiconductor element and a power supply pattern that is commonly connected to the power supply line of the internal semiconductor element, and the mounting board is interconnected to the power supply pattern. And a connection land interconnected with the connection land is recessed from the end surface.
【0009】[0009]
【作用】半導体パッケージの内部半導体素子の電源線を
共通に接続してパターン化して実装基板との間の接続を
行い、かつ実装基板と半導体パッケージとを密着させ
る。Function: The power supply lines of the internal semiconductor elements of the semiconductor package are commonly connected and patterned to make a connection with the mounting board, and the mounting board and the semiconductor package are brought into close contact with each other.
【0010】[0010]
【実施例】以下、本発明の一実施例を図により説明す
る。図1は、本発明の一実施例を示す断面図、図2は、
本発明の一実施例に用いる実装基板を示す平面図であ
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing an embodiment of the present invention, and FIG.
It is a top view which shows the mounting substrate used for one Example of this invention.
【0011】図において、本実施例に係る半導体素子の
実装構造は、半導体パッケージ7と実装基板1とを組合
せたものである。In the figure, the semiconductor element mounting structure according to this embodiment is a combination of a semiconductor package 7 and a mounting substrate 1.
【0012】半導体パッケージ7は、内部半導体素子の
信号線に個々に導通した接続ランド6と、内部半導体素
子の電源線に共通して接続した電源パターン5とを端面
に有するものである。The semiconductor package 7 has, on its end face, connection lands 6 that are individually conducted to the signal lines of the internal semiconductor elements and power supply patterns 5 that are commonly connected to the power supply lines of the internal semiconductor elements.
【0013】実装基板1は、前記電源パターン5に相互
接続される電源パターン4を端面に有し、前記接続ラン
ド6に相互接続される接続ランド2を端面より後退させ
て凹部(以下、絶縁空間という)8内に有するものであ
る。The mounting board 1 has a power supply pattern 4 interconnected with the power supply pattern 5 on an end surface thereof, and the connection land 2 interconnected with the connection land 6 is set back from the end surface to form a recess (hereinafter referred to as an insulating space). It has in 8).
【0014】半導体パッケージ7の接続ランド6を実装
基板1の接続ランド2に溶着接続部3を介して接続し、
同時に、パッケージ7の電源パターン5を基板1の電源
パターン4に溶着接続部9を介して接続する。The connection land 6 of the semiconductor package 7 is connected to the connection land 2 of the mounting board 1 through the welding connection portion 3,
At the same time, the power supply pattern 5 of the package 7 is connected to the power supply pattern 4 of the substrate 1 via the welding connection portion 9.
【0015】[0015]
【発明の効果】以上説明したように本発明は、半導体素
子の電源線をパッケージ上に電源パターンとして設け、
また溶着接続部分を基板の凹部内に収容し、前記パッケ
ージ電源パターンと実装基板上の基板電源パターンとの
接続を可能にしたので、前記半導体パッケージの電源端
子を増加させることがなく、電源インピーダンスを低く
抑えることができる。As described above, according to the present invention, the power line of the semiconductor element is provided on the package as a power pattern.
Further, since the welded connection portion is housed in the concave portion of the substrate to enable connection between the package power source pattern and the substrate power source pattern on the mounting substrate, the power source impedance of the semiconductor package is not increased and the power source impedance is increased. It can be kept low.
【0016】また、半導体パッケージと実装基板が溶着
接続部を介して密着されるため、前記半導体素子の放熱
性を向上できるという効果を有する。Further, since the semiconductor package and the mounting substrate are adhered to each other via the welded connection portion, there is an effect that the heat dissipation of the semiconductor element can be improved.
【図1】本発明の一実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.
【図2】図1に示した実装基板の平面図である。FIG. 2 is a plan view of the mounting board shown in FIG.
【図3】従来例を示す断面図である。FIG. 3 is a cross-sectional view showing a conventional example.
1 実装基板 2 接続ランド 3 溶着接続部 4 電源パターン 5 電源パターン 6 接続ランド 7 半導体パッケージ 8 凹部 9 溶着接続部 1 Mounting Substrate 2 Connection Land 3 Weld Connection 4 Power Pattern 5 Power Pattern 6 Connection Land 7 Semiconductor Package 8 Recess 9 Weld Connection
Claims (1)
せてなる半導体素子の実装構造であって、 半導体パッケージは、内部半導体素子の信号線に個々に
導通した接続ランドと、内部半導体素子の電源線に共通
して接続した電源パターンとを端面に有するものであ
り、 実装基板は、前記電源パターンに相互接続される電源パ
ターンを端面に有し、前記接続ランドに相互接続される
接続ランドを端面より後退させて凹部内に有するもので
あることを特徴とする半導体素子の実装構造。1. A semiconductor element mounting structure comprising a combination of a semiconductor package and a mounting substrate, wherein the semiconductor package has a connection land electrically connected to a signal line of the internal semiconductor element and a power supply line of the internal semiconductor element. The mounting board has a power supply pattern interconnected with the power supply pattern on the end surface and a connection land interconnected with the connection land from the end surface. A mounting structure for a semiconductor device, characterized in that the mounting structure is provided so as to be retracted and have the recess.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9578892A JPH05267540A (en) | 1992-03-23 | 1992-03-23 | Packaging structure for semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9578892A JPH05267540A (en) | 1992-03-23 | 1992-03-23 | Packaging structure for semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05267540A true JPH05267540A (en) | 1993-10-15 |
Family
ID=14147200
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9578892A Pending JPH05267540A (en) | 1992-03-23 | 1992-03-23 | Packaging structure for semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05267540A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6707685B2 (en) | 2001-04-26 | 2004-03-16 | Kyocera Corporation | Multi-layer wiring board |
JP2013069800A (en) * | 2011-09-21 | 2013-04-18 | Nec Corp | Structure and method for mounting semiconductor device |
-
1992
- 1992-03-23 JP JP9578892A patent/JPH05267540A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6707685B2 (en) | 2001-04-26 | 2004-03-16 | Kyocera Corporation | Multi-layer wiring board |
JP2013069800A (en) * | 2011-09-21 | 2013-04-18 | Nec Corp | Structure and method for mounting semiconductor device |
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