JPH05166993A - Semiconductor chip carrier - Google Patents

Abstract

PURPOSE:To enable the part of a lead soldered to wirings laid on a board to be visually inspected to lessen a soldering operation time by a method wherein a slit or a through-hole is bored in a part of the lead to provide an opening. CONSTITUTION:An electrode located on the surface of a semiconductor chip is connected to a metallized part 2 with a wire, and a lead 3 is electrically connected to the electrode of the semiconductor chip through the intermediary of the metallized part 2. In this case, a slit 3a is provided on a part of the lead 3. Solder 6 is fed to the outer periphery of the lead 3 to connect the lead 3 with a conductor pattern 5a of an outer board 4, where a flow of solder 6 can be visually confirmed with ease through the slit 3a provided to the lead 3. By this setup, a soldering operation can be lessened in time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip carrier, and more particularly to improvement of a lead structure of a semiconductor chip carrier for mounting a semiconductor chip and connecting to a wiring of another substrate.

[0002]

2. Description of the Related Art FIG. 4 is a perspective view of a conventional semiconductor chip carrier, FIG. 5 is a plan view of the semiconductor chip carrier when it is mounted, and FIG. 6 is a sectional view taken along the line AA 'in FIG. Show. In each figure, 1 is a plate-shaped insulator, 2 is a metallized portion provided on a part of the front surface and the back surface of the insulator 1,
Reference numeral 3 denotes a plate-shaped lead attached to the metallized portion 2, and these members constitute a semiconductor chip carrier. Further, 4 is an external substrate to which the semiconductor chip carrier is connected, 5 is a conductor pattern provided on the surface of the external substrate 4, 6 is solder for connecting the lead 3 and the conductor pattern 5, and 7 is a semiconductor chip carrier. Fins to which the external board 4 and the external board 4 are attached, and 8 are solders for connecting the fin 7 to the semiconductor chip carrier and the external board 4.

Next, a mounting method will be described. The semiconductor chip (not shown) attached to the metallized portion 2 has electrodes (not shown) on the surface of the chip and the metallized portion 2
Are connected by a wire such as gold or aluminum, and the lead 3 is electrically connected to the electrode of the semiconductor chip through the metallized portion 2 on the surface. Then, as shown in FIG. 6, the semiconductor chip carrier and the external substrate 4 are mounted on the fins 7 by the solder 8, and then the solder 6 is supplied to the outer peripheral edge portion of the leads 3 of the semiconductor chip carrier as shown in FIG. It is connected to the conductor pattern 5 on the substrate 4. As a result, the semiconductor chip is connected to the conductor pattern 5 on the external substrate 4,
A predetermined operation is performed by supplying power and a signal.

[0004]

Since the conventional semiconductor chip carrier is constructed as described above, when the leads of the carrier are connected to the conductor pattern on the external board by soldering, the contact between the external board and the lead is made. It was not possible to visually confirm whether or not the solder was sufficiently poured into the surface and the connection was surely made. For this reason, a large amount of solder was required as well as heat-up for a long time to sufficiently pour the solder. Further, the area in which the solder spreads becomes large, which necessitates a wide conductor pattern on the external substrate, which results in a long assembling work time and the device cannot be downsized.

The present invention has been made to solve the above-mentioned problems, and it is possible to visually confirm the flow of solder into the contact surface between the lead and the external board, and therefore the external board can be quickly fed. An object of the present invention is to obtain a semiconductor chip carrier that can be soldered and can be downsized.

[0006]

In a semiconductor chip carrier according to the present invention, an opening is provided by notching a part of a lead part or forming a through hole, and the lead part and wiring on another substrate. It is intended to confirm the soldering state with.

[0007]

In the present invention, since the lead portion is partially notched or formed with a through hole, the state of the solder flowing in can be visually confirmed through this opening.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor chip carrier according to an embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, FIG.
The same reference numerals denote the same or corresponding portions, and 3a is a slit provided in the lead 3.

Next, a mounting method will be described. First, the electrodes on the surface of the semiconductor chip (not shown) attached to the metallized portion 2 of the semiconductor chip carrier and the metallized portion 2 are connected by a wire such as gold or aluminum in the same manner as in the conventional case, and the leads 3 are connected to the metallized portion 2. Electrically connected to the electrode of the semiconductor chip via. Further, the leads 3 and the metallized portions (not shown) on the back surface of the semiconductor chip carrier are connected to the fins using solder.

Next, as shown in FIG. 2, when the solder 6 is supplied to the outer peripheral edge of the lead 3 to connect the lead 3 and the conductor pattern 5a of the external substrate 4, the lead 3 has a slit 3a.
Is provided, it is possible to easily visually confirm how the solder 6 flows at this time through the slit 3a.
The working time of soldering can be shortened, and at the time of soldering, the solder 6 quickly flows into the exposed external substrate 4 through the slits 3a, so that the leads 3 and the conductor patterns 5a are formed.
The solder is promptly supplied to the contact surface of. Further, since the flow-in state of the solder can be visually confirmed, the amount of solder used for soldering may be the minimum amount necessary for connecting the lead 3 and the conductor pattern 5a, and the solder attached to other parts than the soldering portion. Since the amount of the conductive pattern 5a is reduced, the width of the conductor pattern 5a can be reduced. Further, even if the amount of the solder 6 used is a little large, excess solder does not spread around the lead 3 and is collected and absorbed in the slit 3a.

As described above, according to this embodiment, since the slit 3a is formed in the lead 3, when the lead 3 and the conductor pattern 5a of the external substrate 4 are soldered, the state of the solder flowing at that time is determined by the slit 3a. It can be visually confirmed from the above, the working time can be shortened, and the amount of solder used can be reduced. Further, since the solder 6 quickly infiltrates into the contact surface between the lead 3 and the conductor pattern 5a through the slit 3a, the speed of the soldering operation itself can be increased, and the amount of solder spreading around the soldering portion is reduced, so that the conductor pattern is reduced. The width of 5a can be reduced, and the device can be downsized.

FIG. 3 shows another embodiment of the present invention. In this example, the lead 3 is formed with a plurality of through holes 3b instead of slits, and the solder is supplied through the through holes 3b during soldering. Then, the same effect as that of the above-described embodiment is obtained.

In the above embodiment, a plurality of slits having the same width are provided, but the width and shape of the slits are not limited to this, and various modifications are possible. Needless to say, the shape of the through hole is not limited to the circular shape, and various modifications are possible.

[0014]

As described above, according to the semiconductor chip carrier of the present invention, a part of the lead portion is notched,
Alternatively, since the through hole is formed and the opening is provided, it is possible to visually confirm the soldering state of the lead portion and the wiring on another board, and it is possible to shorten the soldering work time, and Can be minimized, and therefore the conductor pattern of the other substrate connected to the lead can be made small,
There is an effect that the device can be downsized.

Further, there is an effect that the opening speed at the time of soldering improves the infiltration speed, and the soldering speed itself can be increased.

[Brief description of drawings]

FIG. 1 is a perspective view of a semiconductor chip carrier according to an embodiment of the present invention.

FIG. 2 is a plan view of the semiconductor chip carrier when mounted.

FIG. 3 is a perspective view showing another embodiment of the semiconductor chip carrier.

FIG. 4 is a perspective view of a conventional semiconductor chip carrier.

FIG. 5 is a plan view of a conventional semiconductor chip carrier when mounted.

FIG. 6 is a sectional view of a conventional semiconductor chip carrier.

[Explanation of symbols]

 1 Insulator 2 Metallized part 3 Lead 3a Slit 3b Hole 4 External board 5 Conductor pattern 5a Conductor pattern 6 Solder 7 Fin 8 Solder

Claims (1)

[Claims] 1. A semiconductor comprising: an insulating substrate on which a semiconductor chip is mounted; and a lead portion for electrically connecting the chip mounted on the substrate to a wiring formed on another substrate by soldering. In the chip carrier, the lead portion is provided with an opening by notching a part of the lead portion or forming a through hole, and the soldering state at the time of performing the soldering can be visually confirmed. Semiconductor chip carrier.