JPH05267454A - Method of generating data on hard macro pattern - Google Patents

Abstract

PURPOSE:To shorten the time of automatic layout processing by enabling the generation of the hard macro pattern matching with specified technology from the data on the hard macro pattern which has the terminal position not positioned on the grid based on specified technology. CONSTITUTION:A wiring pattern La for connecting the positions Ta and Ts of both terminals is made, setting the position Ts of a temporary terminal at the position of the grid geared to the technology of a chip 19, outside of a hard macro pattern 20, to the position Ta of each terminal (old terminal) of the hard macro pattern 20 being made by another technology not dependent on the technology of a chip 19 to be mounted. Moreover, a wiring pattern Ln for connecting both terminals Ts and Tn is made, setting the position Tn of another terminal at the position Ts of the temporary terminal similarly. And, in addition to these wiring patterns La and Ln, other pattern data are made, and these data are made the pattern data P of a new hard mask 30 geared to the technology of the chip 19.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hard macro pattern data generation method. In recent years, when a hard macro is mounted in a gate array, an embedded LSI has appeared in which a hard macro portion is physically dedicated and mounted without using a transistor for a logic cell. In such an LSI,
It takes a lot of man-hours to align the pattern data of the hard macros of different technologies with a specific technology and perform the layout processing. Therefore, an efficient layout process of hard macros with different technologies is desired for short-term development and short-term delivery of LSI.

[0002]

2. Description of the Related Art Conventionally, in a gate array due to high integration and compounding of LSI, RAM, ROM, PL
Compiled macros such as A, FIFO, multiplier, barrel shifter, and ALU, and hard macros such as CPU peripherals, CPU cores, and analog circuits (hereafter, compiled macros are also included in hard macros) are combined with logic circuits. It has come to be mounted on one chip. In addition, when a hard macro is mounted in a gate array, an embedded LSI has appeared in which the hard macro portion is physically dedicated without using a transistor for a logic cell to increase the degree of integration.

[0003]

By the way, in automatic layout processing, the grid pitch, which is the basic unit of the coordinate system for processing, differs for each technology due to the difference in manufacturing process. Therefore, when a hard macro created for one technology is mounted on another technology as it is, the grid pitches are different from each other. As a result, as shown in FIG.
Peripheral circuit (logic cell) consisting of 0 and logic cell 2
When 1 is connected, the terminal position Ta of the hard macro 20 does not ride on the grid of the terminal position of the peripheral circuit 21 due to the difference in the grid pitch GP.

Therefore, conventionally, it was necessary to manually change the terminal positions to create another pattern, which was very troublesome and required a great deal of time. RAM, R
Bits, words, and columns can be freely selected in a compiled macro such as OM, and a hard macro can be created by compiling when necessary, but it is not possible to create a hard macro in advance, and the compiled macro can be used after all. I had to fix it in my work.

Further, when a hard macro created for another technology is manually mounted on the embedded LSI 19 shown in FIG. 6, a further problem occurs. That is, the transistors for the logic cell 21 are often laid all over the area other than the hard macro 20 region. In this case, the position of the power supply wiring 22 supplied to the logic cell 21 is fixed on the assumption that the hard macro 20 is not mounted. As a result, a process of removing the power supply wiring 22 in the area where the hard macro 20 is arranged is performed, and there is a problem that the power supply wiring 22 is cut in the middle. Moreover, in the same manner as described above, the power supply terminal position Tb of the hard macro 20 for supplying to the hard macro 20 and the LSI
It didn't fit well with the power position on 19.

The present invention has been made in order to solve the above problems, and its purpose is to form a hard macro pattern created by another technology having terminal positions not located on a grid based on a specific technology. It is an object of the present invention to provide a hard macro pattern data generation method capable of generating a hard macro pattern in which data is matched by the specific technology and contributing to reduction in automatic layout processing time.

[0007]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides a position outside the hard macro pattern created by another technology that does not depend on the technology of the chip to be mounted on the terminal position of the hard macro pattern. On the other hand, a temporary terminal position is set at a grid position suitable for the technology of the chip, and a wiring pattern for connecting both terminal positions is formed. A new terminal position is set at a grid position suitable for the technology of the chip to be mounted with respect to the temporary terminal position, and a wiring pattern for connecting the temporary terminal position and the new terminal position is formed. Then, each wiring pattern is added to the hard macro pattern to create new pattern data, and the new pattern data added is created to create new hard macro pattern data suitable for the technology of the mounted chip. To do.

[0008]

Therefore, according to the present invention, the pattern data of this new hard macro can be used and matched with the technology of the chip to be mounted, so that automatic layout processing can be performed. As a result, the time required for the process of the entire automatic layout is shortened, the man-hours for development are reduced, and short-term product development becomes possible.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment embodying the present invention will now be described with reference to FIGS.
It will be described with reference to FIG. FIG. 1 is a block diagram of a hard macro pattern data generation device. The hard macro layout device 10 is connected to a storage device 11 that stores hard macro pattern data, and the hard macro that is stored in the storage device 11 does not depend on the technology. The pattern data of is input. The hard macro layout device 10 is connected to the rule input device 12, and inputs the information of the technology rule including the wiring rule set by the rule input device 12 such as the wiring width, the grid pitch, the adjacency condition, and the restriction information. Also, the rotation information input device 1
Reference numeral 3 is for inputting rotation and mirror inversion information, which is used when rotating or mirror reversing when a hard macro is mounted on an LSI, to the hard macro layout device 10 by the number of hard macros.

Then, the hard macro layout device 10
Is the rule input device 12 and inputs the hard macro pattern data input from the storage device 11 based on the information of the technology rule such as the wiring width, grid pitch, adjacency condition and other wiring rules and the restriction information from the rule input device 12. The hard macro pattern data suitable for the technology specified by the device 12 is created. Then, the created pattern data is stored in the storage device 14. Further, the hard macro layout device 10 makes a library of the created pattern data for automatic layout and stores it in the storage device 15.

Next, the operation of the hard macro pattern data generating device is shown in FIG.
The processing operation of 0 will be described. It should be noted that, for convenience of explanation, when the LSI is mounted on the embedded LSI 19 shown in FIG. 4, the new hardware shown in FIG. 3 for matching the pattern data of the hard macro 20 created by another technology at the position shown in FIG. A case where the pattern data of the pattern P of the macro 30 is generated will be described.

Now, information on the technology rule of the LSI 19 shown in FIG. 4 is inputted from the rule input device 12. Further, the pattern data of the hard macro 20 created by another technology that does not depend on the technology of the LSI 19 is input from the storage device 11. Then, when the hard macro 20 needs to be rotated or inverted when mounted on an LSI, the pattern data of the hard macro 20 is rotated or inverted based on the rotation from the rotation information input device 13 and the mirror inversion information. ..

Next, with respect to each terminal (old terminal) position Ta of the hard macro 20, outside the pattern of the hard macro 20, a temporary terminal position (hereinafter, temporary terminal position) is set at a grid G position based on the technology of the LSI 19. Say)
Determine each Ts. Subsequently, the wiring La is provided between the old terminal position Ta and the temporary terminal position Ts with the given wiring width.
To do. Since the wiring La needs to be wired so as to satisfy the given adjacency condition, the wiring La is cranked. In this case, each temporary terminal position Ts is determined to be a position that satisfies the wiring width and adjacency conditions and secures a region necessary for crank wiring processing. Moreover, in order to minimize the pattern size of the generated hard macro 30, the crank position of each wiring La is determined by the positional relationship between all the old and temporary terminal positions Ta and Ts, the wiring width, and the adjacency condition. .. At this time, the power supply wiring Le described later is also taken into consideration for the determination.

When the wiring La between the old terminal position Ta and the temporary terminal position Ts is determined, a pair of power supply rings R1 and R2 are provided.
Generate. The pair of power supply rings R1 and R2 are located outside each of the temporary terminal positions Ts and arranged so as to surround the pattern of the hard macro 20. This arrangement position is determined by the adjacency condition of the temporary terminal position Ts and the wiring La.

Then, the pair of power supply rings R1 and R2 and the power supply terminal position Tb of the hard macro 20 are connected to each other in a straight line at a given wiring width at intervals satisfying the adjacency condition. At this time, when the power supply wiring Le intersects and is short-circuited at the crank portion of the wiring La connected between the old terminal position Ta and the temporary terminal position Ts, the wiring layer of the crank portion of the wiring La is changed. .. That is, the contact holes H are formed at both ends of the crank portion, and the processing is performed so that the contact holes H are connected to each other.

Next, the hard macro layout device 10 determines the new terminal position Tn based on the temporary terminal position Ts. That is, a new terminal position Tn with respect to each temporary terminal position Ts is located at a position outside the pair of power supply rings R1 and R2, and at a position connected from each temporary terminal position Ts by a straight line orthogonal to the power supply rings R1 and R2. To decide. When the new terminal position Tn is determined, the new terminal position Tn and the temporary terminal position Ts are connected to form the wiring Ln. At this time, when the wiring Ln connected between the temporary terminal position Ts and the new terminal position Tn crosses the power supply rings R1 and R2 and is short-circuited, the wiring layer of the wiring Ln is changed.

When the new terminal position Tn and the wiring Ln are determined in this way, the hard macro layout apparatus 10 causes the terminals Ta, Ts and Tn and the positions thereof, the positions of the wirings La and Ln and the wiring thereof. Layer, power ring R1,
Pattern data of a new hard macro 30 in which information such as the position and layer of R2 is part of the hard macro 20 is created. That is, a pattern obtained by adding the patterns of the new terminal position Tn, the power supply rings R1 and R2, and the wirings La and Ln to the pattern of the original hard macro 20 is output as the pattern data of the hard macro 30 according to the technology of the LSI 19. The pattern data of the hard macro 30 that matches the technology of the LSI 19 is stored in the storage device 1.
In addition to being stored and held in the memory 4, the pattern data of the hard macro for automatic layout includes the data of the official new terminal position and the wiring prohibition area, and the library is stored in the storage device 15.

When the hard macro pattern P thus created is mounted on the technology of the embedded LSI 19, since the new terminal position Tn of the mounted hard macro 20 matches the grid pitch GP of the LSI 19. The connection with other logic cells 21 is easily and automatically performed.

Moreover, as shown in FIG. 4, the power supply wirings 22 supplied to the logic cells 21 are cut off by the laid-out hard macros 30, but the cut power supply wirings 22 are formed in the hard macros 30, respectively. By connecting to the power supply rings R1 and R2, there is no need to perform a new layout process of power supply wiring due to disconnection.

As described in detail above, according to this embodiment,
When the hard macro 20 created by another technology is mounted on the embedded LSI 19, the pattern of the wirings La and Lb matched with the technology of the LSI 19 is added to the pattern of the hard macro 20 from the hard macro 20. Data of a new pattern P of the hard macro 30 to which the pattern of the power supply wiring Le connecting the patterns of the power supply rings R1 and R2 and the power supply terminal position Tb of the hard macro 20 is added is created. Therefore, if this new hard macro pattern data is used, it is compatible with the embedded LSI technology, and automatic layout processing is possible. As a result, the automatic layout becomes possible, and the time (TAT) required for the entire automatic layout process is shortened, so that the development man-hours are reduced and the short-term product development becomes possible. Moreover, since automatic layout is possible, there is no manual input error as in the past.

The present invention is not limited to the above-mentioned embodiment, but in the above-mentioned embodiment, the embedded LSI 1 is used.
Although the pattern data of the hard macro 30 for 9 has been described, it may be applied to a standard cell type LSI. In this case, if the power supply rings R1 and R2 are unnecessary, the pattern of the power supply rings R1 and R2 is not formed.

Although the temporary terminal position Ts is provided and the new terminal position Tn is provided for the temporary terminal position Ts, the temporary terminal position Ts may be the new terminal position Tn. in this case,
There is no wiring between the temporary terminal position Ts and the new terminal position Tn.

Further, although the pattern P of the hard macro 30 is rectangular in the above-mentioned embodiment, it is not limited to this, and if the new terminal position Tn is on the grid G of the technology, another pattern is obtained. The shape may be changed according to the connection with the macro.

[0024]

As described in detail above, according to the present invention, pattern data of a hard macro created by another technology having a terminal position not located on the grid based on the specific technology is stored in the specific technology. A matched hard macro pattern can be generated, and there is an excellent effect that the automatic layout processing time can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram of a hard macro pattern data generation device showing an embodiment of the present invention.

FIG. 2 is a flowchart showing a processing operation of a hard macro layout device.

FIG. 3 is a pattern diagram of a hard macro created by a hard macro layout device.

FIG. 4 is a diagram showing a state in which a hard macro formed by a hard macro layout device is mounted on an embedded LSI.

FIG. 5 is a diagram showing hard macros placed on grids of different technologies.

FIG. 6 is a diagram showing hard macros created by different technologies in an embedded LSI.

[Explanation of symbols]

 19 LSI 20 Hard Macro 30 New Hard Macro Ta Terminal Position Ts Temporary Terminal Position G Grid La, Ln, Ln Wiring P Pattern

Claims (4)

[Claims] 1. The above-mentioned relative to the terminal position (Ta) of the hard macro pattern (20) outside the hard macro pattern (20) created by another technology that does not depend on the technology of the mounted chip (19). Chip (1
9) The temporary terminal position (Ts) is set to the grid position (G) that matches the technology of 9), and both terminal positions (Ta, T
s) is formed into a wiring pattern (La), and a new terminal position (T) is formed at a grid position (G) corresponding to the technology of the chip (19) with respect to the temporary terminal position (Ts).
n) is set, the temporary terminal position (Ts) and the new terminal position (Ts)
n) is formed, a wiring pattern (Ln) is formed, new wiring pattern data is created by adding the wiring patterns (La, Ln) to the hard macro pattern (20), and the new pattern is added. A method of generating pattern data of a hard macro, characterized in that pattern data (P) of a new hard macro (30) suitable for the technology of the chip (19) to be mounted is used. 2. A pair of power ring patterns (R1, R2) are formed outside a hard macro pattern (20) created by another technology, and the power ring pattern (R1, R2) and the hard macro pattern are formed. (2
0) A new pattern formed by forming a power supply wiring pattern (Le) for connecting to the power supply terminal position (Tb) and further adding the power supply ring pattern (R1, R2) and the power supply wiring pattern (Le). 2. The hard macro pattern data generation method according to claim 1, wherein the data is pattern data (P) of a new hard macro (30) suitable for the technology of the chip. 3. The pattern data generating method according to claim 2, wherein the power supply ring pattern (R1, R2) is formed outside the temporary terminal position (Ts). 4. The pattern data generation method according to claim 1, wherein the pattern data of the new hard macro (30) includes data of the wiring prohibited area.