JP2000314954A - Formation of layout of pattern for lsi, formation of pattern for lsi and formation of mask data for lsi - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to surely execute the proximity effect correction capable of forming a circuit pattern to enable operation while subjecting an LSI(large-scale integrated circuit) to desired fining. SOLUTION: This method for formation of a layout consists in first setting a design rule, basic process conditions, etc., (SB1). Next circuit patterns are formed in accordance with the set design rule (SB2) and thereafter, whether the formed circuit patterns satisfy the design rule or not is certified (SB3). OPC (proximity effect correction) pattern forming specifications are then set (SB5) and the OPC patterns are formed from the respective circuit patterns in accordance with the OPC pattern forming specifications (SB6). Whether the formed OPC patterns satisfy an OPC pattern arrangement rule or not is certified (SB7). Whether an OPC effect may be obtained or not is certified (SB10). If the OPC pattern arrangement making it infeasible to obtain the OPC effect is decided to exist (SB11), the design rule is so corrected as not to generate the OPC pattern arrangement making it infeasible to obtain the OPC effect (SB12).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI pattern layout creating method which can surely perform proximity effect correction,
The present invention relates to a method of creating mask data and a method of forming an LSI pattern using the same.

[0002]

2. Description of the Related Art In recent years, the size of large-scale integrated circuit devices (hereinafter, referred to as LSIs) using semiconductors has been reduced, and
In the lithography process, which is one of the LSI manufacturing processes, the optical proximity effect (optical Proximity effect)
The difference between the dimension (mask dimension) of a design pattern formed on a reticle or the like and the dimension (working dimension) of a transfer pattern formed by transferring the design pattern on a resist has become more significant. As a result, if the dimensions of the design pattern are made to correspond to the mask dimensions as they are, there arises a problem that the processing dimensions do not match the desired design dimensions. This problem has been particularly pronounced in transistors that determine whether or not LSIs operate normally.

[0003] Furthermore, there is a generational change that requires discontinuous dimensional changes in LSI. For example, if the process technology is 0.
In order to change from the 25 μm generation to the 0.18 μm generation, the size represented by the gate length of the transistor is reduced by about 70
Vary by percentage reduction. At this time, not only the gate length but also the cell area for realizing the same circuit is 70
It is also expected that the area of percent squared, or about 50 percent by area ratio, will be reduced. This reduction is achieved by introducing new exposure tools with shorter wavelength exposure light sources or by improving the processing process.

However, in recent years, it has become impossible to satisfy this reduction rate only by introducing a new apparatus or improving a processing process. This is because the size variation of the processing dimensions with respect to the mask dimensions has increased, and the dimensions of the design rules such as the gate protrusion dimensions and contact margins set to guarantee circuit operation can satisfy the 70% reduction rate of the previous generation. Because it is gone.

FIG. 20A shows a design pattern 100A and a processed pattern (transfer pattern) 100B of a general transistor (FET). As shown in FIG. 20A, the design pattern 100A includes a gate pattern 101 serving as a gate layer and an activation layer pattern 102 serving as an activation layer. In the gate pattern 111 of the processing pattern 100B, both end portions 111a of the gate pattern 111 disappear because the gate width is smaller than the design size. As described above, the transistor does not operate normally in a state where the overlap between the activation layer pattern 112 and the gate pattern 111 has disappeared.

In order to prevent this, as shown in a design pattern 100C in FIG. 20B, protrusions 101a projecting from the activation layer pattern 102 in the gate width direction are provided at both ends of the gate pattern 101. The disappearance dimension at both ends of the gate pattern 101 increases as the dimension of a line pattern called a gate length 101b decreases. For this reason, the protrusion dimension 10
1c is not reduced in proportion to the gate length 101b. Therefore, when the gate length 101b is reduced, in order to guarantee the operation of the transistor, the gate pattern 10
One protrusion size 101c must be increased. As a result, it is increasingly difficult for the design rule relating to the protrusion dimension 101c to satisfy the 70% reduction ratio of the previous generation.

[0007] In spite of such a current situation, a design rule is determined based on a dimensional variation of a processing dimension with respect to a mask dimension, and is defined, for example, by a 70% reduction ratio of the previous generation. Therefore, even for a pattern that cannot completely satisfy the design rule, such as the protrusion dimension 101c of the gate pattern 101, the design rule with a 70% reduction ratio is preferentially adopted in order to reduce the circuit pattern area. .

After that, a cell library is created from the circuit pattern designed according to the design rules. Create LSI chip data from the created cell library,
Determine final process conditions for manufacturing. Based on the final process conditions, the amount of variation of the processing dimension caused by the proximity effect with respect to the mask dimension is evaluated, and data in which the mask layout is corrected so that the processing dimension does not vary with the design dimension is created. At this time, the processing dimensions for each mask dimension are evaluated using an empirical model for processing dimension evaluation taking various conditions into consideration so that the processing dimensions can be evaluated under the process conditions already determined.

For example, in a circuit pattern, a portion where the processing size is smaller than the mask size has a larger mask pattern size than the design size, and a portion where the processing size is larger than the mask size has a larger size than the design size. Correct so that the mask pattern dimension becomes thin. Proximity effect correction (OpticalPro
It is called an ximity correction (OPC) pattern.

[0010]

However, in the above-described conventional mask data creation method for LSI, the OPC pattern is created for the first time in the mask pattern data creation stage after all the circuit patterns are determined. There is a problem that it cannot be created.

For example, as shown in FIG. 20A, when the end of the gate pattern 101 disappears, the protruding portion 101a of the gate pattern 101 is adjusted so that the value of the processing size matches the circuit pattern size. In some cases, the space between the protruding portion 101a and the pattern around it is already the minimum size determined from the resolution limit. In such a case, it is impossible to change the protrusion dimension 101c of the gate pattern 101.

Further, the conventional mask data creating method has various problems as described below.

(1) A design rule that does not consider proximity effect correction in advance has a problem that a pattern dimension becomes unnecessarily large.

As described above, the proximity effect correction for the gate pattern includes a method other than extending the protruding portion. For example, when the space between the gates is set relatively large, a hammerhead pattern may be added to the protruding portion of the gate pattern that is not located on the activation layer of the transistor. This hammer head pattern does not extend the protruding portion but widens only the end of the protruding portion in the gate length direction, thereby preventing the processing dimension of the gate pattern end from shrinking in the gate width direction. As described above, the proximity effect correction can be realized not only by compensating the variation in the processing dimension from the mask dimension, but also by suppressing the variation. For this reason,
Simply estimating the dimensional variation without evaluating the dimensional variation due to the OPC pattern and determining a design rule based on the dimensional variation would result in the determination that a dimension larger than necessary is necessary.

(2) In general, circuit patterns are created based on basic pattern arrangement rules. The process conditions are determined so that variations in the processing dimensions of the created pattern and variations from the mask dimensions are reduced. On the other hand, since the arrangement rule of the OPC pattern is different from the pattern arrangement rule used when determining the process condition, there is a problem that the used process condition is not always optimal for the OPC pattern arrangement rule.

For example, when a circuit pattern is designed so that the space between the patterns becomes a minimum value, it is assumed that the processing size of the space becomes larger than the design value. In this case, since the size of the space in the OPC pattern is made smaller than the size of the circuit pattern, the minimum space between the OPC patterns becomes smaller than the minimum value of the space between the patterns when the process conditions are first set. ing. Therefore, if the process conditions do not change at all, the processing pattern by the OPC pattern should match the circuit pattern size well. However, in practice, the process conditions fluctuate at the time of manufacturing, so that the processing dimensions vary due to the fluctuations. This is because, in general, when the processing size is reduced, the optimum process condition for suppressing the size variation due to the change in the process condition changes. In an extreme case, in order to suppress the dimensional variation, it is necessary to change even a basic exposure method such as a super-resolution or a phase shift mask.

(3) Although the final process conditions of the LSI are not determined until immediately before manufacturing, there is a problem that the details of the OPC pattern cannot be determined until the details of the process conditions are determined.

When developing an LSI, the circuit pattern design of the cell library is started more than six months before the manufacture of the LSI. However, since the process conditions are determined immediately before the manufacture, the details of the OPC pattern must be determined. Can't decide early. For this reason, it is difficult to design the circuit pattern of the cell library in consideration of the final OPC pattern in order to solve the problem (1).

(4) The OPC pattern is created using only the difference between the design dimension of the circuit pattern and the processing dimension under predetermined process conditions. It is assumed that a circuit pattern uses a design rule defined by a reduction rate of 70% of the previous generation. However, in some LSIs, it is desirable that the reduction ratios are not the same.

For example, in the case of LSIs having the same function, the chip area may be realized at a reduction rate of 50% of the previous generation. Furthermore, in an actual circuit pattern, it is not required that the processing dimensions match the design dimensions at all locations. Some parts of the circuit need to match the design dimensions with high accuracy in order to operate,
In some parts, some dimensional changes are allowed. Therefore, designing all the processing dimensions at a reduction rate of 70% of the previous generation imposes unnecessarily difficult conditions on the manufacture of the LSI, and makes it difficult to realize a desired LSI.

[0021] The present invention solves the above-mentioned conventional problems and provides an LS
It is an object of the present invention to surely perform proximity effect correction for forming a circuit pattern that can operate while achieving desired miniaturization of I.

[0022]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a method of creating a layout of an LSI pattern or a method of creating mask data for an LSI. The proximity effect correction pattern can be created. In addition, a design rule for enabling the proximity effect correction pattern is set at the time of designing a circuit pattern.

More specifically, the method for creating an LSI pattern layout according to the present invention employs an LSI pattern layout including a plurality of circuit patterns.
A circuit pattern design step of designing a plurality of circuit patterns in an SI pattern, an initial arrangement step of initial arrangement of the designed circuit patterns, and a circuit pattern arranged adjacent to or crossing each other among the initially arranged circuit patterns A proximity effect correction pattern creating step of creating a proximity effect correction pattern from circuit patterns arranged adjacent or intersecting with each other, and determining whether the proximity effect correction is effective. A correction effect determination step, a design rule change step of changing a design rule that defines a circuit pattern so that the proximity effect correction is enabled when determined to be invalid, and an initial arrangement based on the changed design rule. And a circuit pattern rearrangement step of rearranging the selected circuit pattern.

According to the LSI pattern layout creating method of the present invention, after the proximity effect correction pattern is created, the design rule for defining the circuit pattern is changed so that the proximity effect correction becomes effective. ,
A situation in which proximity effect correction cannot be performed on a mask pattern to which a design pattern is transferred can be avoided.

In the LSI pattern layout creating method according to the present invention, the proximity effect correction pattern creating step includes a step of setting a correction pattern creation specification for creating the proximity effect correction pattern. It is preferable to include a step of changing the correction pattern creation specification so that the proximity effect correction becomes effective when it is determined that the effect correction is invalid.

In the method for creating a layout of an LSI pattern according to the present invention, the circuit pattern rearrangement step includes a step of creating a plurality of relocation patterns and selecting a relocation pattern having a small circuit area from the plurality of created relocation patterns. It is preferable to include

An LSI pattern layout creating method according to the present invention further comprises a design rule creating step of creating a design rule for performing a layout so that proximity effect correction is effective, and includes an initial arrangement step or a circuit pattern rearrangement. Preferably, the step includes a step of arranging a plurality of circuit patterns based on a design rule.

In this case, the design rule creation step includes:
It is preferable to include a step of setting a plurality of design rules and selecting a design rule that can reduce a circuit area among the set design rules.

In this case, the method for creating a layout of an LSI pattern according to the present invention comprises the steps of: setting a correction pattern creation specification for creating a proximity effect correction pattern; The method further includes a step of creating a correction pattern arrangement rule, and a step of determining a design rule by creating a proximity effect correction pattern based on the correction pattern creation specification and the correction pattern arrangement rule. Is preferred.

In this case, the method for producing a layout of an LSI pattern according to the present invention comprises the steps of: determining whether proximity effect correction is effective for a circuit pattern arranged based on a design rule; If it is determined that
Preferably, the method further comprises the step of correcting the correction pattern creation specification or the correction pattern arrangement rule so that the proximity effect correction is effective.

In the method for preparing an LSI pattern layout according to the present invention, the correction effect judging step performs a process simulation including at least one of a lithography step and an etching step, so that a predicted value of a processing dimension satisfies a predetermined value. It is preferable to determine whether or not this is the case.

In this case, in the lithography step in the process simulation, it is preferable to determine whether or not the predicted value of the processing dimension when the exposure amount or the focus position changes beyond the process allowance satisfies a predetermined value. .

In this case, it is preferable that the judgment of the process simulation includes a step of judging the dimension of the transistor in the gate length direction.

In this case, it is preferable that the judgment of the process simulation includes a step of judging a protrusion dimension of the gate of the transistor from the active layer in the gate width direction.

A first method for forming an LSI pattern according to the present invention performs a circuit pattern designing step of designing a plurality of circuit patterns in an LSI pattern including a plurality of circuit patterns, and performs an initial arrangement of the designed circuit patterns. The initial placement step, and performing the proximity effect correction on the circuit patterns arranged adjacent or intersecting with each other among the circuit patterns initially arranged, so that the proximity effect correction pattern is obtained from the circuit patterns arranged adjacent or intersecting with each other. Proximity effect correction pattern creating step of creating a pattern, a correction effect determining step of determining whether the proximity effect correction is valid under predetermined process conditions, and when it is determined that the proximity effect correction is invalid, the proximity effect correction is valid Rule change process to change the design rule that defines the circuit pattern A circuit pattern rearrangement step of rearranging an initially arranged circuit pattern, a mask manufacturing step of manufacturing a mask using the proximity effect correction pattern, and a semiconductor under predetermined process conditions using the manufactured mask. A pattern forming step of forming a plurality of circuit patterns on the substrate.

According to the first method for forming an LSI pattern, a circuit pattern (work pattern) is formed on, for example, a resist film by using a mask manufactured by using the LSI pattern layout creating method of the present invention. A circuit pattern of a circuit that operates reliably can be obtained.

The first method of forming an LSI pattern includes a step of evaluating an expected value of a processing yield when a manufactured mask is used under predetermined process conditions after a mask manufacturing step. It is preferable that the method further includes a step of resetting predetermined process conditions so that the expected value reaches the target value when the value does not reach the target value, and then repeating the circuit pattern designing step again.

The first method of producing mask data for an LSI according to the present invention is a method for producing a plurality of circuit patterns included in an LSI, comprising: a first correction pattern group which does not change the pattern shape in accordance with a change in process conditions; A step of classifying a correction pattern group into a second correction pattern group for changing a pattern shape in accordance with a change in condition; and a step of cell-level proximity from the first correction pattern group when designing a plurality of circuit patterns. A cell level correction pattern data generating step of generating effect correction pattern data; and a chip level correction of generating chip level proximity effect correction pattern data from a second correction pattern group when generating chip data from a plurality of circuit patterns. Pattern data creating step.

According to the first method of creating mask data for LSI, a plurality of circuit patterns included in the LSI are subjected to a first correction pattern group whose pattern shape is not changed in accordance with a change in process conditions; Therefore, the first correction pattern group can be registered as a library even if the first correction pattern group has been subjected to proximity effect correction in advance. Further, since the first correction pattern group greatly affects the area of the cell, the proximity effect correction pattern at the cell level can be determined at the cell designing stage by using the proximity effect correction pattern at the cell level. It is possible to reliably evaluate the cell area of the proximity effect correction pattern that is created in a targeted manner. Furthermore, since the proximity effect correction at the cell level can be performed on a cell-by-cell basis, the specification for creating the proximity effect correction pattern can also be determined on a cell-by-cell or block-by-cell basis.

In the first method of generating mask data for LSI, the step of generating cell level correction pattern data includes the step of determining whether the proximity effect correction in the generated cell level proximity effect correction pattern data is valid. When it is determined that the proximity effect correction is invalid, the proximity effect correction pattern data at the cell level or the circuit pattern corresponding to the proximity effect correction pattern data is corrected so that the proximity effect correction becomes effective. It is preferable to include a step of re-determining the validity and a step of registering the cell-level proximity effect correction pattern data in the cell library when the validity is determined.

According to a second method of generating mask data for LSI according to the present invention, a plurality of circuit patterns included in an LSI are formed by a first correction pattern group that does not change the pattern shape in accordance with a change in process conditions; A step of classifying the first correction pattern group into a second correction pattern group that changes a pattern shape in accordance with a change in condition;
Setting a cell-level correction pattern creation specification for creating a cell-level proximity effect correction pattern, designing a plurality of circuit patterns, and creating a cell-level correction pattern creation specification for the first correction pattern group. Determining the validity of the proximity effect correction in the cell-level proximity effect correction pattern created by the method, and, if the proximity effect correction is determined to be invalid, the proximity effect correction is enabled, After correcting the determined circuit pattern, re-determining the validity of the proximity effect correction, and, when the proximity effect correction is determined to be valid, the circuit pattern belonging to the first correction pattern group is stored in a cell library. And registering the circuit pattern belonging to the second correction pattern group in the cell library, and registering the circuit pattern in the cell library. Generating chip-level pattern data from a road pattern; setting chip-level correction pattern generation specifications for generating a chip-level proximity effect correction pattern for a second correction pattern group; A step of creating cell-level proximity effect correction pattern data from circuit patterns belonging to the first correction pattern group based on the level correction pattern creation specification; and a step of creating a second correction pattern group based on the chip level correction pattern creation specification. And generating chip-level proximity effect correction pattern data from a circuit pattern belonging to

According to the second method of preparing mask data for LSI, a plurality of circuit patterns included in the LSI are subjected to a first correction pattern group whose pattern shape is not changed in accordance with a change in process conditions; When the proximity effect correction pattern for which the cell level correction pattern creation specification is set is determined to be valid, the proximity effect correction pattern determined to be valid is classified into a second correction pattern group whose pattern shape is changed according to Is registered in the cell library. Then, in a step of creating mask data, cell-level proximity effect correction pattern data and chip-level proximity effect correction pattern data are created from the cell library. Therefore, it is not necessary to create the proximity effect correction pattern data having an extremely large data amount even at the time of creating the mask data, so that a large amount of data can be easily managed.

According to a third method of preparing mask data for LSI according to the present invention, a plurality of circuit patterns included in an LSI are processed by a first correction pattern group that does not change the pattern shape in accordance with a change in process conditions; A step of classifying the first correction pattern group into a second correction pattern group that changes a pattern shape in accordance with a change in condition;
Setting a cell-level correction pattern creation specification for creating a cell-level proximity effect correction pattern, designing a plurality of circuit patterns, and creating a cell-level correction pattern creation specification for the first correction pattern group. Determining the validity of the proximity effect correction in the cell-level proximity effect correction pattern created by the method, and, if the proximity effect correction is determined to be invalid, the proximity effect correction is enabled, After revising the determined circuit pattern or the cell-level correction pattern creation specification of the circuit pattern, re-determining the validity of the proximity effect correction. If the proximity effect correction is determined to be valid, the first The circuit patterns belonging to the correction pattern group and the cell level correction pattern creation specification corresponding to the circuit patterns are registered in the cell library. In both cases, a step of registering a circuit pattern belonging to the second correction pattern group in the cell library, a step of creating chip-level pattern data from the circuit pattern registered in the cell library, Generating the cell-level proximity effect correction pattern data from the circuit patterns belonging to the first correction pattern group, and generating the cell-level proximity effect correction pattern data from the circuit patterns belonging to the second correction pattern group based on predetermined chip-level correction pattern generation specifications. Generating chip-level proximity effect correction pattern data.

In the first to third methods of creating mask data for LSI, the step of determining the validity of proximity effect correction is performed when there are a plurality of circuit pattern layouts for which proximity effect correction has been determined to be valid. It is preferable to include a step of selecting a layout having a circuit area of a predetermined value or less from a plurality of layouts.

In this case, it is preferable that the proximity effect correction pattern data at the cell level include a serif pattern, a hammerhead pattern, or an insection pattern.

According to a fourth method of producing mask data for LSI according to the present invention, a first correction pattern group in which, among a plurality of circuit patterns included in an LSI, circuit patterns are determined by a pattern arrangement over a plurality of layers; A correction pattern group classification step of classifying the circuit pattern into a second correction pattern group determined by a pattern arrangement in one layer;
When designing a plurality of circuit patterns, an inter-layer correction pattern data generating step of generating an inter-layer proximity effect correction pattern data from a first correction pattern group; And an intra-layer correction pattern data generating step of generating intra-layer proximity effect correction pattern data from the second correction pattern group.

According to the fourth method of creating mask data for LSI, a plurality of circuit patterns included in an LSI are divided into a first correction pattern group determined by a pattern arrangement of a plurality of layers of circuit patterns, and one circuit pattern. The first correction pattern group can be registered as a library even if the first correction pattern group has been subjected to the proximity effect correction in advance, since it is classified into the second correction pattern group determined by the pattern arrangement in the layer. . Further, since the first correction pattern group greatly affects the area of the cell, the proximity effect correction pattern at the cell level can be determined at the cell designing stage by using the proximity effect correction pattern at the cell level. It is possible to reliably evaluate the cell area of the proximity effect correction pattern that is created in a targeted manner. Furthermore, since the proximity effect correction at the cell level can be performed on a cell-by-cell basis, the specification for creating the proximity effect correction pattern can also be determined on a cell-by-cell or block-by-cell basis.

In the fourth method of creating mask data for LSI, the step of creating interlayer correction pattern data includes:
Determining whether the proximity effect correction in the created proximity effect correction pattern data of the interlayer is valid; and, if it is determined that the proximity effect correction is invalid, the proximity effect of the interlayer so that the proximity effect is corrected. After correcting the correction pattern data or the circuit pattern corresponding to the proximity effect correction pattern data, re-determining the validity of the proximity effect correction; and, if determined to be valid, the proximity effect correction pattern of the interlayer. Registering the data in the cell library.

According to a fifth method for producing LSI mask data according to the present invention, a first correction pattern group in which, among a plurality of circuit patterns included in an LSI, a circuit pattern is determined by a pattern arrangement over a plurality of layers; A step of classifying the circuit pattern into a second correction pattern group determined by a pattern arrangement in one layer; and an interface for creating an inter-layer proximity effect correction pattern with respect to the first correction pattern group. A step of setting a layer correction pattern creation specification, a step of designing a plurality of circuit patterns, and a step of designing an interlayer correction pattern creation specification for the first correction pattern group. A step of determining whether the proximity effect correction is effective; and, when the proximity effect correction is determined to be invalid, the proximity effect correction. Correcting the circuit pattern determined to be invalid so as to be valid, and then re-determining the validity of the proximity effect correction; and, if the proximity effect correction is determined to be valid, the first correction pattern Registering the circuit patterns belonging to the group in the cell library and registering the circuit patterns belonging to the second correction pattern group in the cell library; and generating chip-level pattern data from the circuit patterns registered in the cell library. A step of setting an intra-layer correction pattern creation specification for creating an intra-layer proximity effect correction pattern for the second correction pattern group; A step of creating proximity effect correction pattern data of an interlayer from circuit patterns belonging to a correction pattern group; Based on Ntorareiya correction pattern creation specifications, and a step of creating a proximity effect correction pattern data of the intra-layer from the circuit pattern belonging to the second correction pattern group.

According to the fifth method of creating mask data for LSI, a plurality of circuit patterns included in the LSI are divided into a first correction pattern group determined by a pattern arrangement of a plurality of circuit patterns and one circuit pattern. And a second correction pattern group determined by the pattern arrangement in the layer of the layer, and when the proximity effect correction pattern in which the inter-layer correction pattern is set is determined to be valid, the proximity effect correction pattern determined to be valid Is registered in the cell library. Then, in the step of creating mask data, the proximity effect correction pattern data of the interlayer and the proximity effect correction pattern data of the intra layer are created from the cell library. Therefore, it is not necessary to create the proximity effect correction pattern data having an extremely large data amount even at the time of creating the mask data, so that a large amount of data can be easily managed.

According to a sixth LSI mask data generating method according to the present invention, a first correction pattern group in which, among a plurality of circuit patterns included in an LSI, a circuit pattern is determined by a pattern arrangement over a plurality of layers; A step of classifying the circuit pattern into a second correction pattern group determined by a pattern arrangement in one layer; and an interface for creating an inter-layer proximity effect correction pattern with respect to the first correction pattern group. A step of setting a layer correction pattern creation specification, a step of designing a plurality of circuit patterns, and a step of designing an interlayer correction pattern creation specification for the first correction pattern group. A step of determining whether the proximity effect correction is effective; and, when the proximity effect correction is determined to be invalid, the proximity effect correction. After correcting the circuit pattern determined to be invalid or the specification of creating an interlayer correction pattern of the circuit pattern so as to be valid, a step of determining again the validity of the proximity effect correction, and determining that the proximity effect correction is valid. If it is determined, the circuit pattern belonging to the first correction pattern group and the specification for creating an interlayer correction pattern corresponding to the circuit pattern are registered in the cell library, and the circuit pattern belonging to the second correction pattern group is registered in the cell library. , A step of generating chip-level pattern data from the circuit patterns registered in the cell library, and a step of converting the circuit patterns belonging to the first correction pattern group to an Generating proximity effect correction pattern data of the Based on the pattern creating specifications, and a step of creating a proximity effect correction pattern data of the intra-layer from the circuit pattern belonging to the second correction pattern group.

In the fourth to sixth LSI mask data creation methods, the step of determining the validity of the proximity effect correction is performed when there are a plurality of circuit pattern layouts for which the proximity effect correction is determined to be valid. It is preferable to include a step of selecting a layout having a circuit area of a predetermined value or less from a plurality of layouts.

In this case, it is preferable that the specification for creating an interlayer correction pattern is determined by an arrangement rule that defines one layer including the gate of the transistor and another layer including the active region.

Also, in this case, the specification for creating an interlayer correction pattern is such that the first wiring layer and the layer including the contact for electrically connecting the second wiring layer different from the first wiring layer are included. Preferably, it is determined by a prescribed arrangement rule.

In this case, the step of determining the effectiveness of the proximity effect correction includes performing a process simulation including at least one of a lithography step and an etching step, so that the predicted value of the processing dimension satisfies a predetermined value. It is preferable to determine whether or not this is the case.

In the lithography step in the process simulation in this case, it is preferable to determine whether or not the predicted value of the processing dimension when the exposure amount or the focus position changes beyond the process allowance satisfies a predetermined value.

In this case, it is preferable that the judgment of the process simulation includes a step of judging the dimension of the transistor in the gate length direction.

In this case, it is preferable that the judgment of the process simulation includes a step of judging a protrusion of the gate of the transistor from the active layer in the gate width direction.

In the second to seventh LSI pattern forming methods according to the present invention, a mask is manufactured by using any of the first to sixth LSI mask data forming methods according to the present invention.
Forming a plurality of circuit patterns on the semiconductor substrate using the manufactured mask;

[0060]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment according to the present invention will be described with reference to the drawings.

In the first embodiment, when manufacturing an LSI, a design rule including a condition for generating an OPC pattern in which a proximity effect correction (OPC) effect is effective is determined, and the determined design rule is used. A circuit pattern is designed and mask pattern data is created.

Further, an OPC pattern is created from a circuit pattern according to a design rule in which the OPC effect is effective, and an optimum basic process condition is determined based on the created OPC pattern. The OPC in this specification
The effect means that the created OPC pattern can realize a processing pattern in which a circuit transferred to a region having substantially the same occupied area (circuit area) as the original circuit pattern can operate normally. Say.

FIG. 1 shows an LS according to the first embodiment of the present invention.
5 shows a creation flow of a method for creating I mask data. As shown in FIG. 1, first, in step SA1, a design rule for designing a circuit pattern of a circuit to be included in an LSI, basic process conditions, a creation specification for creating an OPC pattern from a circuit pattern, and an OPC pattern placement rule are respectively determined. I do. Here, the basic process conditions are, for example, in the case of a lithography step, various conditions such as a wavelength of an exposure light source, a degree of interference of exposure light, a focus position, an exposure amount, and a numerical aperture of a lens. Including selection. For example, whether to use an annular exposure method, whether to use a phase shift mask, and the like. The design rule is a rule that must be observed when designing a circuit pattern in order to obtain a circuit that actually operates. The OPC pattern arrangement rule is a rule to be satisfied by the OPC pattern so that the transfer pattern exposed on the wafer becomes a processable pattern. Therefore, this rule is a design rule in the OPC pattern, and includes a rule that defines a basic pattern arrangement such as a minimum line width and a minimum space of the OPC pattern. As a result, the design rule that guarantees the processing pattern is applied to the OPC pattern serving as the mask pattern,
A design rule can be set for the circuit pattern on the assumption that an OPC pattern is created. As a result, it is possible to select the optimum condition even after the OPC pattern is determined for the basic process condition.

Next, in step SA2, a circuit pattern is created for each cell which is a basic circuit constituting the LSI.

Next, in step SA3, it is verified whether the circuit pattern created in step SA2 satisfies the design rule. If the circuit pattern does not satisfy the design rule, the process proceeds to step SA4, where the portion of the circuit pattern that does not satisfy the design rule is corrected, and the process is repeated from step SA2. If the verified circuit pattern satisfies the design rule, the process proceeds to step SA5.

Next, in step SA5, the basic cells constituting the LSI chip pattern are stored by registering the circuit pattern created for each cell in the cell library.

Next, in step SA6, circuit pattern data necessary for the LSI is extracted from the cell library, and LSI chip data is created using the extracted circuit pattern data.

Next, in step SA7, final process conditions for manufacturing LSI chip data are determined. At this time, if it is necessary to change the OPC pattern placement rule due to the final process condition, the OP
Change the C pattern arrangement rule. This is for the following reason. That is, when developing an LSI, it generally takes one year or more from the determination of a design rule to the creation of a necessary cell library, whereas the period required to create LSI chip data from the cell library is longer. Is at most a few months. For this reason, despite the fact that the optimal process conditions have been determined for the design rules, at the time when the cell library is completed and the LSI chip data is created, the introduction of new resist materials and new equipment will first The determined process conditions may not always be optimal. For this reason, in order to further improve the productivity, it is desirable to finally determine the process conditions at the stage of creating the LSI chip data.

Next, in step SA8, a necessary OPC pattern is created from the LSI chip data based on the OPC pattern creation specification. Specifically, the amount of change in the processing dimension caused by the optical proximity effect with respect to the mask dimension is evaluated under the final process conditions, and data in which the mask layout is corrected so that the processing dimension does not change with respect to the design dimension is created.

Next, in step SA9, it is verified whether or not the OPC pattern created in step SA8 satisfies the OPC pattern arrangement rule. If the OPC pattern placement rule is not satisfied, the process proceeds to step SA1.
Proceeding to 0, the portion of the OPC pattern that does not satisfy the OPC pattern arrangement rule is corrected, and the process is repeated from step SA8. If the verified OPC pattern satisfies the OPC pattern arrangement rule, the next step SA1
Proceed to 1 to create mask pattern data using the OPC pattern.

A mask or reticle is manufactured using the mask pattern data created as described above, and a circuit capable of operating on a resist film or the like formed on a semiconductor substrate, for example, using the manufactured mask or reticle. The pattern can be transferred.

As described above, in the development of the conventional LSI, since the design rule is determined in the upstream process and the OPC pattern is determined in the downstream process, a circuit pattern or an arrangement in which an OPC pattern cannot be created occurs. In that case, it was virtually impossible to change the design rules. However, according to the present embodiment, since the design rule can be changed so that the OPC pattern is effective when the design rule is determined, the circuit pattern and the mask data based on the changed design rule reliably exhibit the OPC effect. it can.

Hereinafter, the details of the processing in step SA1 shown in FIG. 1 will be described with reference to the drawings.

FIG. 2 shows an example of a procedure for determining a basic process condition and a design rule applied to a cell library in a method for creating an LSI pattern layout according to the present embodiment. As shown in FIG. 2, first, in step SB1, initial settings of design rules, basic process conditions, and OPC pattern arrangement rules determined by the basic process conditions are performed. These initial values are given to be some typical samples of the cell library created in step SA6 shown in FIG.

Next, in step SB2, a circuit pattern is created based on the set design rules.

Next, in step SB3, it is verified whether or not the created circuit pattern satisfies the design rule. If the circuit pattern does not satisfy the design rule, the process proceeds to Step SB4, and Step SB4
In the above, the portion not satisfying the design rule of the circuit pattern is corrected, and the process is repeated from step SB2.

Next, in step SB5, an OPC pattern creation specification which defines the specification for creating a required OPC pattern from the circuit pattern is set. The OPC pattern creation specification may be rule-based or model-based (= simulation-based), and a known method may be used. That is, if the circuit patterns are the same, the same OP
Any method that can create a C pattern may be used. Note that the rule base is a method of defining an OPC pattern creation rule for each pattern category in a circuit pattern, and creating an OPC pattern according to the defined creation rule. The model base is a method of calculating the dimensions of a mask pattern using a model formula for simulating the processing dimensions so that the processing patterns match the circuit patterns.

Next, in step SB6, an OPC pattern is created from each circuit pattern based on the set OPC pattern creation specification.

Here, specific examples of the circuit pattern and the OPC pattern will be described with reference to the drawings.

FIG. 3 shows an example of a circuit pattern.
As shown in FIG. 3, the circuit pattern showing the transistor circuit has a rectangular activation layer pattern 11 having a cutout on one side of a long side. On the activation layer pattern 11, a first gate pattern 12 that crosses a long side of the activation layer pattern 11 and straddles a region that does not include the cutout portion.
And a second gate pattern 13 and a third gate pattern 14 that are respectively parallel to the first gate pattern 12 and straddle the cutouts of the activation layer pattern 11. Wiring pattern 15 extending in parallel with the long side having the notch in
Is arranged.

The third gate pattern 14 includes a transistor portion 14a functioning as a gate electrode of the transistor.
And a gate wiring portion 14b having a bent portion that bends over a peripheral region (isolation region) of the activation layer pattern 11.

FIG. 4 shows an example of an OPC pattern created based on the circuit pattern shown in FIG. here,
As shown in FIG. 4, the OPC pattern creation specifications include, for example, the hammer head pattern 12 at the end of the first gate pattern 12, the second gate pattern 13, and the third gate pattern 14 on the wiring pattern 15 side.
h, 13h, and 14h are added, and the width (gate length) of the portion located on the activation layer pattern 11 is changed in accordance with the distance between adjacent gate patterns.

Next, in step SB7, it is verified whether or not the OPC pattern created in step SB6 shown in FIG. 2 satisfies the OPC pattern arrangement rule set in step SB1. The verification target area 17 shown in FIG.
An example is shown in which the interval between patterns is smaller than the minimum space width in the OPC pattern arrangement rule. As described above, when the OPC pattern arrangement rule is not satisfied, the process proceeds to step SB8 shown in FIG. 2, and the OPC pattern creation specification is modified so that the verification target area 17 satisfies the OPC pattern arrangement rule in step SB8. Thereafter, the process is repeated from step SB8. In order to eliminate the violation of the rule of the verification target area 17 shown in FIG. 4, each of the OPC patterns 12 to 14 according to the distance between the adjacent patterns such as the hammer head patterns 12h to 14h.
It is necessary to add a specification to change the shape of the. FIG. 5 shows an OPC pattern in which an OPC pattern is re-created based on the OPC pattern creation specification whose specification has been changed. As shown in the verification target region 17 in FIG. 5, the end of the second gate pattern 13 on the wiring pattern 15 side is obtained by erasing the hammer head pattern 13h, and instead, the end is replaced by the first and third gates. The patterns 12 and 14 are extended so as to be aligned with the ends of the hammer head patterns 12h and 14h.

Next, after the placement verification of the OPC pattern is completed, in SB9 shown in FIG. 2, it is determined whether or not the dimension of the processed pattern obtained from the OPC pattern, that is, the finished dimension (critical dimension) matches the circuit pattern. Is verified. This is a step of confirming whether an effective OPC pattern can be created. Here, it is difficult to verify whether or not the dimensions of the circuit pattern match the dimensions of the processing pattern using an actual circuit. Therefore, a simulation method that is excellent in the reproducibility of the actual circuit is used. However, CD verification does not need to be performed for all portions of one circuit pattern, but is performed for a portion, such as a gate length in a gate pattern, in which a processing dimension must match a design dimension with high accuracy. . If it is determined that the CD verification does not match, the process proceeds to step SB8,
The OPC pattern creation specification is modified so that the mismatched part in the OPC pattern is eliminated, and the process returns to step SB5.
Repeat from

Next, in step SB10, it is verified whether or not the OPC effect appears for the OPC pattern for which the CD verification has been completed. Here, it is verified whether or not the processed pattern dimension satisfies the condition for normally operating the circuit, not whether or not the processed pattern dimension exactly matches the design pattern dimension. The verification method verifies, for example, a processing pattern of a protruding portion of a gate of a circuit pattern by a simulation method having excellent reproducibility as in step SB9. As a specific example, regardless of whether the end of the gate pattern satisfies the dimensions on the circuit pattern, the protruding portion of the gate pattern disappears in the overlapping region between the activation layer pattern and the gate pattern in the processing pattern. Then, it is checked whether or not the activation layer pattern is exposed from the overlap region. Furthermore, even in the case where the processing pattern of the protruding portion of the gate pattern is longer than a predetermined dimension, it is necessary that the protruding portion that is longer does not short-circuit with another pattern and hinder the operation of the circuit. No problem. However,
In the verification of the OPC effect, when a failure occurs, the circuit does not operate. Therefore, in consideration of the variation of the process conditions in the manufacturing process, not only the predetermined process conditions but also the process conditions include a margin for each process. It is necessary to verify that no malfunction occurs.

FIG. 6 shows an example of a simulation result of a processing pattern in the verification of the OPC effect in step SB10. As shown in FIG. 6, the activation layer pattern 1
The corners of each corner and the notch in 1A are rounded, and the protruding part of the second gate pattern 13A on the side of the wiring pattern 15A has almost disappeared. From this simulation result, as shown in the first verification target region 17A, the source region and the drain region in the active layer pattern 11A of the transistor are substantially short-circuited because the gate width of the second gate pattern 13A is reduced. And normal operation cannot be obtained. Further, as shown in the second verification target area 18A, the shape of the bent portion of the third gate pattern 14A becomes dull, and the gate length locally increases near the side of the activation layer pattern 11A. A predetermined operation cannot be obtained. However, here, an example in which the process conditions have a margin is not shown. In practice, a process pattern is simulated after giving a predetermined margin to the process conditions.

As shown in FIG. 6, when it is determined that the OPC effect cannot be obtained, that is, when the normal operation of the circuit cannot be expected, the process proceeds to step SB11 shown in FIG.
In step SB11, it is determined whether or not there is a circuit pattern in which the OPC effect cannot be obtained.

If it is determined in step SB11 that there is no pattern arrangement in which the OPC effect cannot be obtained, the process is repeated from step SB8 again, and the OPC pattern creation specification is corrected so as to obtain the OPC effect.
On the other hand, when it is determined in step SB11 that there is a circuit pattern arrangement in which the OPC effect cannot be obtained, the process proceeds to step SB12, and the design rule is corrected so that the circuit pattern arrangement in which the OPC effect cannot be obtained does not occur.
Thereafter, the process is repeated from step SB4.

FIG. 7 shows the result of correcting the pattern arrangement in which the OPC effect cannot be obtained in step SB4. Here, as a modification example of the design rule, a rule of providing a predetermined interval between the gate pattern and the activation layer pattern is added. Accordingly, a portion of the third gate pattern 14B extending in the gate wiring portion 14b in parallel with the long side of the activation layer pattern 11B has an interval larger than the initial value between the long side of the activation layer pattern 11B. Provided. Similarly, the activation layer pattern 11B
In the end of the notch between the first gate pattern 12 and the second gate pattern 13 in the above, an interval larger than the initial value is provided between the end of the notch and the side surface of the second gate pattern 13. In FIG. 7, the contours of the third gate pattern 14 and the activation layer pattern 11 before correction are indicated by broken lines.

FIG. 8 is an OPC pattern obtained based on the circuit pattern shown in FIG. 7, and FIG. 9 is an OPC pattern shown in FIG.
9 shows a processing pattern indicating a simulation result obtained based on the C pattern. As shown in FIG. 9, the protruding portion at the end of the second gate pattern 13A on the wiring pattern 15A side is extended to such an extent that a predetermined gate length is secured. Further, the gate length of the transistor portion 14a in the third gate pattern 14C is substantially constant.
In this manner, by changing the design rule by verifying the OPC effect, it is possible to create a circuit pattern that can reliably obtain the OPC effect without generating rework steps.

Next, in step SB13 shown in FIG. 2, the circuit area (cell area) of the circuit pattern that can obtain the OPC effect and the yield of the normal operation of the circuit in the processed pattern obtained from the OPC pattern of the circuit pattern are obtained. Evaluate the expected value. As a method for evaluating the expected value of the yield, for example, a method for evaluating the normal operation probability of a transistor in a cell as described in JP-A-10-284608 or JP-A-11-121345 may be used. . This is because the operation probability of normal operation of the transistor can be regarded as an expected value of the yield of the circuit pattern. More specifically, a processing dimension that enables normal operation of the transistor is represented as a response surface function using a process condition or a dimension of a mask pattern representing the transistor as a variable. Further, the method is a method of calculating a probability that a transistor has a working dimension in which a transistor can operate normally in a manufacturing process by substituting a fluctuation distribution of a process condition predicted in the manufacturing process into the response phase function. In general, the reduction in the circuit pattern area and the expected value of the yield at which the circuit can operate normally have a conflicting relationship.

If it is determined in step SB13 that the circuit pattern area is larger than the design value, the flow advances to step SB14 to change the design rule and the corresponding OPC pattern arrangement rule so that a smaller circuit pattern can be obtained. Then, the processing is repeated from step SB1. Also, in step SB13, when it is determined that the expected value of the yield of the normal operation is lower than the target value,
Proceeding to step SB14, the basic process conditions are improved, the design rules and the related OPC pattern placement rules are changed to be enlarged, and the process is repeated from step SB1.

On the other hand, if both the circuit pattern area and the expected value of the yield satisfy the target values, step SB1
Proceed to No. 5, design rules, basic process conditions, OPC
The pattern arrangement rule, OPC pattern creation specification, and circuit pattern data are finally determined.

As described above, according to the present embodiment, by creating a plurality of circuits (cells) as typical samples to be registered as a cell library, the circuit area targeted by the current generation cell library can be reduced. It is possible to determine the basic process conditions and the design rules that ensure the expected value of the normal operation for the created circuit. Needless to say, as the number of samples increases, more optimal design rules, OPC pattern arrangement rules, and OPC pattern creation specifications can be determined.

Hereinafter, effects of the present embodiment will be listed.

(A) In order to determine a design rule that satisfies the condition for obtaining the OPC effect and to design a circuit pattern based on the determined design rule, a necessary OPC is necessary at the stage of creating mask pattern data in the final step. You can never create a pattern.

(B) For circuit patterns belonging to a plurality of typical categories, the final design rules are determined by reflecting the conditions of the design rules for which the OPC effect is effective in the design rules used for circuit pattern design. Therefore, a highly versatile design rule can be constructed.

(C) When determining design rules, O
In order to obtain a predetermined cell area as a condition for obtaining the PC effect, the predetermined cell area is set to be equal to that of the previous generation LSI.
If you set it to be half the area of the circuit included in
Design rules are not unnecessarily large.

(D) Since the design rule is reduced not based on the size of the processing pattern based on each circuit pattern defined by the design rule but on the basis of the reduction of the circuit area, it is difficult to realize more than necessary. The situation of designing a pattern is avoided.

(E) The basic process conditions are
Since the PC pattern is assumed and the settings are reset so as to improve the productivity as shown in step SB14, the basic process conditions are not inappropriate for the final process conditions.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. In the present embodiment, as in the first embodiment, the necessary OP
A design rule including a condition for creating a C pattern is determined, and a circuit pattern is designed and mask pattern data is created based on the determined design rule. In particular, in the present embodiment, since the OPC effect can be individually verified at the time of designing each cell (basic circuit), the cell area can be made smaller for each cell.

FIGS. 10 and 11 show a processing flow of an LSI mask data creating method according to the second embodiment of the present invention.

First, in step SC1 shown in FIG. 10, a design rule, a basic process condition, and an OPC pattern arrangement rule are determined. Among them, the design rule and the basic process conditions are set in step SA1 shown in FIG.
Is determined in the same manner as described above. On the other hand, the OPC pattern placement rules classify the OPC patterns into a first category that does not need to be sensitively changed according to a change in process conditions, and a second category that needs to be changed sensitively.

Here, specific examples of the first and second categories will be described with reference to FIGS. 12 (a) and 12 (b). FIG. 12A shows a first pattern 21A including a wiring portion 21a and a protruding portion 21b which protrudes relatively largely from one side portion of the wiring portion 21a, a wiring portion 22a, and a first pattern 21A from one side portion of the wiring portion 22a. A second pattern 22A including a relatively small protruding portion 22b and the second wiring portion 21a, 22
a are parallel and spaced apart. In this case, for example, the OPC pattern for changing the processing size of the wiring width in each of the wiring portions 21a and 22a needs to be changed sensitively to the change of the process condition, and is therefore classified into the second category. Although not shown, as another example, the processing dimension of the gate length in the gate pattern is a pattern that must exactly match the design dimension, and is classified into the second category.

On the other hand, as shown in FIG. 12B, the hammer head pattern 21c provided at the end of the protrusion 21b in the first OPC pattern 21B created based on the first pattern 21A, and the wiring Portion 21a and Projection 21
The insection pattern 21d, which has been deleted so that the connection with b, is narrowed, does not need to be changed sensitively to changes in process conditions, and is classified into the first category. Similarly, the second OP created based on the second pattern 22A
The serif patterns 22c provided at both corners of the end of the protrusion 22b in the C pattern 22B are also classified into the first category. Here, the hammer head pattern 21c and the serif pattern 22c prevent the end of the original pattern from disappearing, and the in-section pattern 21d prevents the corner of the connection portion between the patterns from being rounded.

In general, an OPC pattern that is important in determining a circuit pattern area (cell area), that is, an OPC pattern that exhibits an OPC effect with a reduced cell area, is
It belongs to the first category. Therefore, the OPC pattern belonging to the first category is referred to as a cell-level OPC pattern because the proximity effect correction can be performed even at the stage of designing a cell library in which the final process condition is not determined. On the other hand, for the second category in which the OPC pattern cannot be created unless the final process conditions are determined, the proximity effect correction is performed after the LSI chip data is completed and after the final process conditions are determined. Let's call them patterns.

Next, in step SC2 shown in FIG. 10, a circuit pattern is created for each cell without depending on the category based on the design rule determined in step SC1.

Next, in step SC3, it is verified whether the created circuit pattern satisfies the design rule. If the circuit pattern does not satisfy the design rule, the process proceeds to step SC4, and the process proceeds to step SC4.
In step 2, the portion of the circuit pattern that does not satisfy the design rule is corrected, and the process is repeated from step SC2.
If the circuit pattern data satisfies the design rule, the process proceeds to step SC5.

Next, in step SC5, a cell-level OPC pattern is created from the circuit patterns belonging to the first category among the created circuit patterns. The rule-based method is preferably used for creating the cell-level OPC pattern. That is, a rule for creating a cell-level OPC pattern is created for each circuit pattern, and a cell-level OPC pattern is created according to the created rules. Here, the OPC for obtaining the OPC effect
To create a pattern, instead of designing an OPC pattern to match the processing dimensions with the circuit pattern dimensions, create an optimal OPC pattern so that a processing pattern that allows the circuit pattern to operate normally in its area can be realized. There is a need to. For this reason, as for the processing dimensions of a portion that does not cause a defect in the circuit operation, an OPC pattern that improves the expected value of the circuit operation yield may be created even if the circuit pattern dimension is ignored. Therefore, in order to realize this, a method called a rule base that can define a rule that can create an OPC pattern for each circuit pattern is suitable as a model for creating an OPC pattern. This is because the model base realizes the processing dimensions appearing in the circuit pattern as they are.

Next, in step SC6, it is verified whether or not the created cell-level OPC pattern satisfies the OPC pattern arrangement rule. Cell level OPC
If the pattern does not satisfy the OPC pattern arrangement rule, the process proceeds to step SC7, in which the portion of the cell level OPC pattern that does not satisfy the OPC pattern arrangement rule is corrected, and the process is repeated from step SC5.

Next, in step SC8, it is verified whether or not the OPC effect is obtained for the cell-level OPC pattern satisfying the OPC pattern arrangement rule. The verification method is the same as step SB10 of the first embodiment, and is performed by a simulation method that is excellent in the reproducibility of an actual circuit. As a specific example, whether or not the protruding portion of the gate pattern disappears in the overlapping region between the activated layer pattern and the gate pattern in the processed pattern regardless of whether the end of the gate pattern satisfies the dimensions on the circuit pattern. To check whether the activation layer pattern is exposed from the overlap region. However, OPC
As described above, since the circuit does not operate if a failure occurs as described above, it is necessary to consider not only the predetermined process conditions but also the process conditions in consideration of the variation in the process conditions in the manufacturing process. It is necessary to verify that no problem occurs, including the margin.

If it is determined in step SC8 that the OPC effect cannot be obtained, that is, the circuit cannot be expected to operate normally, the process proceeds to step SC9, where the circuit pattern cannot obtain the OPC effect in step SC9. Check whether there is a pattern arrangement.

If it is determined in step SC9 that there is no pattern arrangement in which the OPC effect cannot be obtained, the process is repeated from step SC7 again, and a cell level OPC pattern is created again so as to obtain the OPC effect.
On the other hand, if it is determined in step SC9 that there is a circuit pattern arrangement in which the OPC effect cannot be obtained, the process proceeds to step SC4, and the circuit pattern is corrected so that the circuit pattern arrangement in which the OPC effect cannot be obtained does not occur. Thereafter, the process is repeated from step SC2.

Next, in step SC10, it is determined whether or not the cell area of each circuit pattern is smaller than a target value. If the cell area is larger than the target value, the process proceeds to step SC4, and the circuit pattern is corrected so as to reduce the cell area. On the other hand, if the cell area is equal to or smaller than the target value, the process proceeds to step SC11 shown in FIG.

Next, in step SC11 shown in FIG. 11, the cell level OPC pattern created for each cell is registered as a mask pattern cell library of each circuit pattern. Further, the circuit patterns belonging to the second category are registered as they are in the cell library. Thus, a set of basic circuits constituting the LSI chip pattern is accumulated.

Next, in step SC12, circuit pattern data necessary for the LSI is extracted from the cell library, and LSI chip data is created using the extracted circuit pattern data.

Next, in step SC13, the LSI
Determine final process conditions for manufacturing chip data.

Next, in step SC14, based on the final process conditions, the amount of change in the processing dimension caused by the proximity effect with respect to the mask dimension is evaluated in more detail. As a result, a chip-level OPC pattern is created for a cell belonging to the second category, for example, a portion where the processing dimension of the gate length in the gate pattern must exactly match the design dimension. OPC at this time
As a pattern creation method, a rule base or a model base can be used.

Next, in step SC15, CD verification is performed to determine whether or not the dimensions of the processing pattern created from the chip-level OPC pattern match the dimensions of the circuit pattern. Also in this case, the finished dimensions are verified using a simulation method capable of sufficiently reproducing an actual circuit.
Also in this step, it is not necessary to verify all the parts of one circuit pattern, and the CD verification is also performed on the parts whose processing dimensions need to match the design dimensions with high accuracy. If it is determined that the CD verification does not match, the process proceeds to step SC16, in which the chip level OPC pattern is corrected so as to eliminate the mismatching portion in the OPC pattern, and the process is repeated from step SC14 again. When the model base is used in step SC14, the CD verification need not be performed.

Next, in SC17, mask pattern data is created using the created cell-level and chip-level OPC patterns. A mask or reticle is manufactured from the mask pattern data, and an operable circuit pattern can be transferred to a resist film or the like formed on a semiconductor substrate using the manufactured mask or reticle.

(Modification of Second Embodiment) Hereinafter, a modification of the second embodiment of the present invention will be described with reference to the drawings.

FIGS. 13 and 14 show a processing flow of an LSI mask data creating method according to a modification of the second embodiment of the present invention. In the second embodiment,
As shown in step SC11, the cell level OPC pattern is directly registered in the cell library. In this modification, when a cell-level OPC pattern is created based on a rule base, a step of creating a cell-level OPC pattern includes a step of setting the creation specification, and a step of creating a cell-level OPC pattern based on the creation specification. The case where the operation is performed separately will be described. Thus, instead of the cell level OPC pattern, a circuit pattern and a cell level OPC pattern creation specification for the circuit pattern can be separately registered in the cell library.

In FIG. 13, the difference from the second embodiment is that the creation of the cell level OPC pattern in step SC5 shown in FIG. 10 is different from the second embodiment in that the cell level OPC pattern for each circuit cell shown in step SD5A is used in this modification.
The point is that the process is separated into two processes of setting a pattern creation specification and creating a cell level OPC pattern shown in step SD5B.

In FIG. 14, the difference from the second embodiment is that, in step SD11 for creating a cell library, the object to be registered in the cell library is not an OPC pattern, but each circuit pattern and its corresponding cell level OPC pattern. The point is that each combination with the creation specification is registered.

A further significant difference is that step SD1
In 4, a cell-level OPC pattern is created according to the created cell-level OPC pattern creation specification.
Chip-level O based on rule-based or model-based
The point is that the chip level OPC pattern is simultaneously created according to the PC pattern creation specification.

Thus, the cell-level and chip-level OPC comprising a large amount of complicated pattern data
There is no need to process the pattern until immediately before creating the mask data, and the process of handling a large amount of data can be unified.

The cells registered in the cell library are:
Since it is necessary to represent not only the mask data of the mask production but also the circuit configuration, it is desirable that a circuit pattern representing a processing pattern, not an OPC pattern, be registered. Also, when changing the registered circuit pattern, it is more convenient to register the circuit pattern instead of the OPC pattern.

As described above, according to the second embodiment and its modifications, the circuit patterns are classified into the first category that strongly affects the cell area and the second category that is not strongly affected by the circuit pattern. A cell level OPC pattern belonging to one category can be determined at the cell design stage. For this reason, the circuit pattern can be designed while considering the OPC effect and reducing the cell area, so that it is possible to eliminate a pattern arrangement in which the OPC effect cannot be obtained at the stage of designing each circuit pattern. Thereby, when the target cell area is achieved, the circuit pattern that is difficult to realize and the circuit pattern including the useless margin are not mixed, so that the cell area is reliably reduced to the target value while The expected value of the yield at which the LSI operates normally can also be improved.

(Third Embodiment) Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

This embodiment differs from the second embodiment in that
A cell whose circuit pattern is upstream of an OPC pattern defined by a plurality of layers, such as a transistor, including a first layer including an activation layer pattern and a second layer including a gate pattern extending over the activation layer pattern An OPC pattern created in the design process and defined only in a single layer, such as a gate pattern, is created in a downstream mask data processing process.

A circuit (cell) includes a plurality of components. In designing a circuit pattern for determining the arrangement of the plurality of components, a circuit which greatly affects the cell area among various circuits is usually used. Is defined not by a single layer but by a pattern contained in a plurality of layers. The OPC pattern defined by the plurality of layers can change the arrangement of circuit components for each layer.
By considering the C pattern in the cell design stage, it is possible to arrange circuit components with a smaller cell area.

FIGS. 15 and 16 show a processing flow of an LSI mask data creating method according to the third embodiment of the present invention.

First, in step SE1 shown in FIG. 15, similarly to step SC1 according to the second embodiment, a design rule, a basic process condition, and an OPC pattern arrangement rule are determined. Further, as a feature of the present embodiment, an OPC pattern defined by a plurality of layers, that is, an inter-layer OPC pattern, which is important in determining a cell area, is classified as a first category, and an OPC pattern defined by a single layer is classified. Patterns, ie, intra-layer patterns, are classified as a second category.

Next, steps SE2, SE3 and SE4
After creating each circuit pattern and verifying the design rules, in step SE5, an interlayer OPC pattern is created for each cell.

Here, the inter-layer OPC pattern will be described with reference to the drawings.

FIG. 17A shows a plan configuration of a transistor circuit for explaining a circuit pattern according to the present embodiment, and FIG. 17B shows an interlayer OPC of FIG.
3 shows a plan configuration of a transistor circuit for explaining a pattern. As shown in FIG. 17A, a first circuit pattern 31A including a rectangular activation layer pattern 31a and a gate layer pattern 31b straddling a central portion of a long side of the activation layer pattern 31a, and a rectangular activation layer pattern 31a. And a second circuit pattern 32A composed of an active layer pattern 32a and a gate layer pattern 32b straddling the center of the long side of the active layer pattern 32a. Activation layer pattern 3
The long sides of 1a and 32a are spaced apart by about 0.3 μm,
Opposing ends of the gate layer patterns 31b and 32b are arranged so as not to overlap with each other.

As described above, for example, the first circuit pattern 31A has an overlapping portion where the activation layer pattern 31a and the gate layer pattern 31b overlap. Therefore, when the activation layer pattern 31a is formed on the semiconductor substrate, a channel region is generated in the overlapping portion to function as a transistor circuit. For this reason, there is an arrangement rule between the activation layer pattern 31a and the gate layer pattern 31b. Therefore, changes in the positional relationship between the activation layer pattern 31a and the gate layer pattern 31b affect each other. The same applies to the second circuit pattern 32A.

The first OPC pattern 31B and the second OPC pattern 32B shown in FIG.
It corresponds to the first circuit pattern 31A and the second circuit pattern 32A shown in FIG. As shown in FIG. 17B, here, each gate layer pattern 31b, 32
13 shows an example in which hammer head patterns having different shapes are added to both end portions of FIG. Specifically, at one end of each of the gate layer patterns 31b and 32b on the side facing each other, the distance between the active layer patterns 31a and 32a is 0.2 μm, which is smaller than that of the circuit pattern. The shape of the hammer head pattern is made smaller than the other end.

Although not shown, an OPC pattern based on a contact pattern for connecting wires included in different layers is also formed from a wiring OPC pattern formed from the wiring pattern and a contact pattern. The contact OPC pattern is defined by a plurality of layers.

Next, steps SE6 and SE shown in FIG.
8 and SE10, created interlayer OPC
It is verified whether the pattern satisfies the OPC pattern arrangement rule, whether the OPC effect can be obtained, and whether the cell area satisfies a predetermined value. The verification method may be performed by the method described in the second embodiment. If the verification result is not satisfactory, the inter-layer OPC pattern is corrected in step SE7, or the circuit pattern is corrected for each layer and the rearrangement of circuit components is performed in step SE4 so as to obtain the OPC effect. Do.

Next, in step SE11 shown in FIG. 16, an inter-layer OPC pattern created for each cell is registered as a mask pattern cell library of each circuit pattern. Further, the circuit patterns belonging to the second category are registered as they are in the cell library. As a result, a set of basic circuits constituting the LSI chip pattern is accumulated.

Next, in step SE12, circuit pattern data necessary for the LSI is extracted from the cell library, and LSI chip data is created using the extracted circuit pattern data.
Determine final process conditions for manufacturing I-chip data.

Next, in step SE14, the amount of change in the processing dimension caused by the proximity effect with respect to the mask dimension is evaluated in more detail based on the final process conditions. Thereby, the intra layer OP belonging to the second category
Create a C pattern. At this time, the OPC pattern creation method may be either rule-based or model-based.

Next, in step SE15, a CD indicating whether or not the dimension of the processed pattern created from the intra-layer OPC pattern matches the dimension of the circuit pattern
Perform verification. Also in this case, the finished dimensions are verified using a simulation method capable of sufficiently reproducing an actual circuit. Also in the present embodiment, it is not necessary to verify all the parts of one circuit pattern, and it is performed on a part where the processing dimensions need to match the design dimensions with high accuracy.
If it is determined that the CD verification does not match, step SE1
Proceeding to 6, the intra-layer OPC pattern is corrected so that the mismatched portion in the OPC pattern is eliminated, and the process is repeated from step SE14 again. Step SE
14 using the model base, this CD
The verification need not be performed.

Next, in SE17, mask pattern data is created using the created OPC patterns of the inter-layer and intra-layer. A mask or reticle is manufactured from the mask pattern data, and an operable circuit pattern can be transferred to a resist film or the like formed on a semiconductor substrate using the manufactured mask or reticle.

In this embodiment, in step SE14, the intra-layer OPC belonging to the second category
Although the pattern is created after the LSI chip data is created in step SE12, a circuit that is a cell-level OPC pattern of the first category in the second embodiment among the intra-layer OPC patterns is also included. Therefore, a circuit in which such a cell-level OPC pattern is generated may be designed in step SE2.

(Modification of Third Embodiment) A modification of the third embodiment of the present invention will be described below with reference to the drawings.

FIGS. 18 and 19 show a processing flow of an LSI mask data creating method according to a modification of the third embodiment of the present invention. In the third embodiment,
As shown in step SE11, the interlayer OPC pattern is directly registered in the cell library. In the present modification, when an interlayer OPC pattern is created by a rule base, a step of creating an interlayer OPC pattern includes a step of setting the creation specification, and a step of creating an interlayer OPC pattern based on the creation specification. The case where the operation is performed separately will be described. As a result, instead of the inter-layer OPC pattern, a circuit pattern and an inter-layer OPC pattern creation specification for the circuit pattern can be separately registered in the cell library.

In FIG. 18, the difference from the third embodiment is that the generation of the interlayer OPC pattern in step SE5 shown in FIG. 15 is different from that of the third embodiment in that This is a point separated into two processes of setting the creation specification and creating the interlayer OPC pattern in step SF5B.

In FIG. 19, the difference from the third embodiment is that, in step SF11 for creating a cell library, the object to be registered in the cell library is not an OPC pattern, but each circuit pattern and its corresponding interlayer OPC pattern. The point is that each combination with the creation specification is registered.

A further significant difference is that step SF1
4, an inter-layer OPC pattern is created according to the created inter-layer OPC pattern creation specification, and an intra-layer OPC pattern is created according to a rule-based or model-based intra-layer OPC pattern creation specification.
The point is that the C pattern is created simultaneously.

In this way, the O and O of the inter-layer and the intra-layer composed of a large amount of complicated pattern data
There is no need to process the PC pattern until immediately before creating the mask data, and the process of handling a large amount of data can be unified.

The cells registered in the cell library are:
Since it is necessary to represent not only the mask data of the mask production but also the circuit configuration, it is desirable that a circuit pattern representing a processing pattern, not an OPC pattern, be registered. Also, when changing the registered circuit pattern, it is more convenient to register the circuit pattern instead of the OPC pattern.

As described above, according to the third embodiment and its modifications, the circuit patterns are classified into the first category that strongly affects the cell area and the second category that is not strongly affected by the circuit pattern. An inter-layer OPC pattern belonging to one category can be determined at the cell design stage.
For this reason, the circuit pattern can be designed while considering the OPC effect and reducing the cell area, so that it is possible to eliminate a pattern arrangement in which the OPC effect cannot be obtained at the stage of designing each circuit pattern. Thereby, when the target cell area is achieved, the circuit pattern that is difficult to realize and the circuit pattern including the useless margin are not mixed, so that the cell area is reliably reduced to the target value while The expected value of the yield at which the LSI can operate normally can also be improved.

Step SE4 and step SF4
In the above, the rearrangement processing of circuit components may be performed using a tool called a compactor. When a compactor is used, it is not necessary to repeat verification and correction as in the present embodiment. Further, if the OPC effect of the inter-layer OPC pattern is added to the rearrangement function of the compactor in a ruled manner, the cell pattern can be automatically synthesized.

[0156]

According to the LSI pattern layout creating method according to the present invention, after the proximity effect correction pattern is created, the design rule for defining the circuit pattern is changed so that the proximity effect correction becomes effective. Proximity effect correction can be reliably performed by using a design pattern created by a design rule in which the proximity effect correction is valid and a mask pattern created by the design pattern.

According to the method for producing LSI mask data according to the present invention, a circuit pattern which greatly affects the area of a cell is a cell-level proximity effect correction pattern or an inter-layer proximity effect correction pattern. The proximity effect correction pattern can be determined at the design stage. For this reason, the cell area of the proximity effect correction pattern finally created can be reliably evaluated.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a method for creating LSI mask data according to a first embodiment of the present invention.

FIG. 2 is a flowchart illustrating an LSI pattern layout creation method according to the first embodiment of the present invention.

FIG. 3 is a plan view showing an example of a circuit pattern in an LSI pattern layout creation method according to the first embodiment of the present invention.

FIG. 4 is a plan view showing an LSI pattern layout creation method according to the first embodiment of the present invention, and showing an example of an OPC pattern created from the circuit pattern shown in FIG. 3;

FIG. 5 is a plan view showing a method for creating a layout of an LSI pattern according to the first embodiment of the present invention, and showing another example of an OPC pattern created from the circuit pattern shown in FIG. 3;

FIG. 6 is a plan view showing an LSI pattern layout creation method according to the first embodiment of the present invention, showing an example of a processed pattern obtained from the OPC pattern shown in FIG. 5;

FIG. 7 is a plan view showing a method for creating a layout of an LSI pattern according to the first embodiment of the present invention, in which the circuit pattern shown in FIG. 3 is modified;

8 is a plan view showing an LSI pattern layout creation method according to the first embodiment of the present invention, and showing an example of an OPC pattern created from the circuit pattern shown in FIG. 7;

FIG. 9 is a plan view showing an LSI pattern layout creation method according to the first embodiment of the present invention, showing an example of a processed pattern obtained from the OPC pattern shown in FIG. 8;

FIG. 10 is a flowchart illustrating a method of creating mask data for LSI according to a second embodiment of the present invention.

FIG. 11 is a flowchart illustrating a method of generating LSI mask data according to a second embodiment of the present invention.

FIGS. 12A and 12B show patterns for explaining categories in an LSI mask data creating method according to a second embodiment of the present invention, and FIG. 12A shows a pattern belonging to the second category; FIG. 4 is a plan view showing a chip-level circuit pattern, and FIG. 4B is a plan view showing a cell-level circuit pattern belonging to a first category.

FIG. 13 is a diagram showing an example of L according to a modification of the second embodiment of the present invention.
9 is a flowchart illustrating a method for creating SI mask data.

FIG. 14 illustrates L according to a modification of the second embodiment of the present invention.
9 is a flowchart illustrating a method for creating SI mask data.

FIG. 15 is a flowchart illustrating a method of generating LSI mask data according to a third embodiment of the present invention.

FIG. 16 is a flowchart illustrating a method of generating mask data for LSI according to a third embodiment of the present invention.

FIGS. 17A and 17B show patterns for explaining categories in an LSI mask data creating method according to the third embodiment of the present invention, and FIG. 17A belongs to the first category; It is a top view which shows the circuit pattern of an interlayer, (b) is a top view which shows an example of the OPC pattern created from (a).

FIG. 18 is a diagram illustrating an L according to a modification of the third embodiment of the present invention.
9 is a flowchart illustrating a method for creating SI mask data.

FIG. 19 is a diagram showing an L according to a modification of the third embodiment of the present invention.
9 is a flowchart illustrating a method for creating SI mask data.

FIGS. 20 (a) and (b) are plan views showing a conventional design pattern and a processing pattern of a transistor in a conventional method of creating mask data for LSI.

[Explanation of symbols]

 Reference Signs List 11 activation layer pattern 11A activation layer pattern 11B activation layer pattern 11C activation layer pattern 12 first gate pattern 12A first gate pattern 12h hammer head pattern 13 second gate pattern 13A second gate pattern 13h hammer Head pattern 14 Third gate pattern 14A Third gate pattern 14B Third gate pattern 14C Third gate pattern 14a Transistor part 14b Gate wiring part 14h Hammerhead pattern 15 Wiring pattern 15A Wiring pattern 17 Verification target area 17A First Verification target area 18A second verification target area 21A first pattern 21B first OPC pattern 21a wiring portion 21b protrusion 21c hammerhead pattern 21d insection pattern 2 A second pattern 22B second OPC pattern 22a wiring part 22b projecting part 22c serif pattern 31A first circuit pattern 31B first OPC pattern 31a activation layer pattern 31b gate layer pattern 32A second circuit pattern 32B second OPC pattern 32a Activation layer pattern 32b Gate layer pattern

Claims (36)

[Claims] 1. A circuit pattern design step of designing a plurality of circuit patterns in an LSI pattern including a plurality of circuit patterns, an initial placement step of performing initial placement of the designed circuit patterns, A proximity effect correction pattern creating step of creating a proximity effect correction pattern from the circuit patterns arranged adjacent or intersecting by performing the proximity effect correction on the circuit patterns arranged adjacent or intersecting with each other; A correction effect determining step of determining whether or not the proximity effect correction is valid; and a design rule for changing a design rule defining the circuit pattern so that the proximity effect correction becomes valid when it is determined that the proximity effect correction is invalid. The process of changing and re-arranging the initially placed circuit pattern based on the changed design rules Layout generation method of LSI patterns, characterized in that it comprises a pattern relocation process. 2. The method according to claim 2, wherein:
Setting a correction pattern creation specification for creating the proximity effect correction pattern, wherein the correction effect determination step includes changing the correction pattern creation specification to the proximity effect when the proximity effect correction is determined to be invalid. 2. The method according to claim 1, further comprising the step of changing the correction so that the correction becomes effective. 3. The circuit pattern rearranging step includes a step of generating a plurality of rearrangement patterns and selecting a rearrangement pattern having a small circuit area from the plurality of generated rearrangement patterns. 2. The method for creating an LSI pattern layout according to item 1. 4. A design rule creating step for creating a design rule for performing a layout so that the proximity effect correction is effective, wherein the initial arrangement step or the circuit pattern rearrangement step includes:
2. The method according to claim 1, further comprising the step of arranging the plurality of circuit patterns based on the design rule. 5. The design rule creating step includes a step of setting a plurality of the design rules and selecting a design rule capable of reducing a circuit area among the set design rules. 5. The method for creating an LSI pattern layout according to item 4. 6. A step of setting a correction pattern creation specification for creating the proximity effect correction pattern, and a step of creating a correction pattern arrangement rule so that the proximity effect correction in the proximity effect correction pattern is effective. 5. The LSI according to claim 4, further comprising: determining the design rule by creating the proximity effect correction pattern based on the correction pattern creation specification and the correction pattern arrangement rule. How to create a layout for a pattern. 7. A step of determining whether or not the proximity effect correction is valid for a circuit pattern arranged based on the design rule; and determining that the proximity effect correction is invalid when it is determined to be invalid. 7. The method of claim 6, further comprising: modifying the correction pattern creation specification or the correction pattern arrangement rule so as to be effective. 8. The correction effect determining step includes performing a process simulation including at least one of a lithography step and an etching step to determine whether a predicted value of a processing dimension satisfies a predetermined value. 2. The method for creating an LSI pattern layout according to claim 1, wherein: 9. A lithography step in the process simulation, wherein a determination is made as to whether or not a predicted value of a processing dimension when the exposure amount or the focus position changes beyond the process allowance satisfies the predetermined value. 9. The layout creating method for an LSI pattern according to claim 8, wherein: 10. The LSI according to claim 8, wherein the determination of the process simulation includes a step of determining a dimension of the transistor in a gate length direction.
How to create a layout for a pattern. 11. The layout of an LSI pattern according to claim 8, wherein the determination of the process simulation includes a step of determining a protrusion dimension of a gate of the transistor from an active layer in a gate width direction. How to make. 12. A circuit pattern designing step of designing the plurality of circuit patterns in an LSI pattern including a plurality of circuit patterns, an initial arrangement step of performing initial arrangement of the designed circuit patterns, A proximity effect correction pattern creating step of creating a proximity effect correction pattern from circuit patterns arranged adjacent or intersecting by performing proximity effect correction on circuit patterns arranged adjacent or intersecting with each other; A correction effect determining step of determining whether or not the proximity effect correction is valid under the following process conditions; and a design rule for defining the circuit pattern so that the proximity effect correction is valid when it is determined that the proximity effect correction is invalid. The process of changing the design rules, and the circuit initially placed based on the changed design rules A circuit pattern rearrangement step of rearranging turns, a mask manufacturing step of manufacturing a mask using the proximity effect correction pattern, and a semiconductor device under the predetermined process condition using the manufactured mask. A pattern forming step of forming a plurality of circuit patterns.
Of forming pattern for use. 13. A step of evaluating an expected value of a processing yield when the manufactured mask is used under the predetermined process conditions after the mask manufacturing step; and a case where the expected value does not reach a target value. 2. The method according to claim 1, further comprising a step of resetting the predetermined process condition so that the expected value reaches a target value, and then repeating the circuit pattern designing step again.
3. The method for forming an LSI pattern according to item 2. 14. A plurality of circuit patterns included in an LSI, a first correction pattern group that does not change a pattern shape according to a change in process conditions, and a second correction pattern group that changes a pattern shape according to a change in process conditions. A correction pattern group classification step of classifying the plurality of circuit patterns into a plurality of correction pattern groups;
A cell-level correction pattern data generation step of generating cell-level proximity effect correction pattern data from the correction pattern group; and, when generating chip data from the plurality of circuit patterns, a chip-level correction pattern data from the second correction pattern group. A mask level correction pattern data generating step of generating proximity effect correction pattern data. 15. The cell-level correction pattern data creating step includes: determining whether proximity effect correction in the created cell-level proximity effect correction pattern data is valid; and determining if the proximity effect correction is invalid, Correcting the cell-level proximity effect correction pattern data or the circuit pattern corresponding to the proximity effect correction pattern data so that the proximity effect correction becomes effective, and then determining the validity of the proximity effect correction again. The method of claim 14, further comprising: registering the proximity effect correction pattern data at the cell level in a cell library when it is determined that the pattern is valid. 16. A first correction pattern group that does not change a pattern shape according to a change in process conditions, and a second correction pattern group that does not change a pattern shape according to a change in process conditions. Classifying into a correction pattern group; setting a cell-level correction pattern creation specification for creating a cell-level proximity effect correction pattern for the first correction pattern group; Designing; and determining whether or not the proximity effect correction is effective in the cell-level proximity effect correction pattern created by the cell level correction pattern creation specification for the first correction pattern group; When the proximity effect correction is determined to be invalid, the circuit pattern determined to be invalid is set so that the proximity effect correction is valid. After performing the correction, re-determining the validity of the proximity effect correction; and, when the proximity effect correction is determined to be valid, registering a circuit pattern belonging to the first correction pattern group in a cell library. Registering a circuit pattern belonging to the second correction pattern group in the cell library; generating chip-level pattern data from the circuit pattern registered in the cell library; Setting a chip level correction pattern creation specification for creating a chip level proximity effect correction pattern for the group; and a circuit belonging to the first correction pattern group based on the cell level correction pattern creation specification Creating cell-level proximity effect correction pattern data from the pattern; Based on the emission creating specifications, the second method of creating LSI mask data, characterized by comprising the step of creating a proximity effect correction pattern data of the chip-level from the circuit patterns belonging to the correction pattern group. 17. A first correction pattern group that does not change a pattern shape according to a change in process conditions, and a second correction pattern group that changes a pattern shape according to a change in process conditions. Classifying into a correction pattern group; setting a cell-level correction pattern creation specification for creating a cell-level proximity effect correction pattern for the first correction pattern group; Designing; and determining whether or not the proximity effect correction is effective in the cell-level proximity effect correction pattern created by the cell level correction pattern creation specification for the first correction pattern group; When it is determined that the proximity effect correction is invalid, the circuit pattern or the circuit determined to be invalid is set so that the proximity effect correction becomes valid. A step of re-determining the validity of the proximity effect correction after correcting the cell level correction pattern creation specification of the circuit pattern; and a step of determining the first correction pattern group when the proximity effect correction is determined to be valid. Registering a circuit pattern belonging to and a cell level correction pattern creation specification corresponding to the circuit pattern in a cell library, and registering a circuit pattern belonging to the second correction pattern group in the cell library; and Generating chip-level pattern data from the registered circuit patterns; and, based on the cell-level correction pattern generation specification, converting cell-level proximity effect correction pattern data from the circuit patterns belonging to the first correction pattern group. Based on the process of creating and the specified chip level correction pattern creation specification,
A step of generating chip-level proximity effect correction pattern data from circuit patterns belonging to the second correction pattern group. 18. The step of determining the validity of the proximity effect correction includes, when there are a plurality of layouts of the circuit pattern for which the proximity effect correction is determined to be valid, a circuit area of the plurality of layouts is equal to or smaller than a predetermined value. 18. The method according to claim 15, further comprising a step of selecting a layout. 19. The method of claim 14, wherein the cell-level proximity effect correction pattern data includes a serif pattern, a hammerhead pattern, or an insection pattern. 20. Among a plurality of circuit patterns included in an LSI, a first correction pattern group in which a circuit pattern is determined by a pattern arrangement over a plurality of layers, and a circuit pattern is determined by a pattern arrangement in one layer. A correction pattern group classification step of classifying the plurality of circuit patterns into a second correction pattern group;
An inter-layer correction pattern data generating step of generating an inter-layer proximity effect correction pattern data from the correction pattern group; and, when generating chip data from the plurality of circuit patterns, an intra-layer correction of the intra layer from the second correction pattern group. An intra-layer correction pattern data generating step of generating proximity effect correction pattern data. 21. The inter-layer correction pattern data creating step includes: determining whether proximity effect correction in the created proximity effect correction pattern data of the interlayer is valid; and determining if the proximity effect correction is invalid, Correcting the proximity effect correction pattern data of the interlayer or a circuit pattern corresponding to the proximity effect correction pattern data so that the proximity effect correction becomes effective, and then determining the validity of the proximity effect correction again. 21. The method of claim 20, further comprising the step of: registering the proximity effect correction pattern data of the interlayer in a cell library when it is determined to be valid. 22. Among a plurality of circuit patterns included in an LSI, a first correction pattern group in which circuit patterns are determined by a pattern arrangement over a plurality of layers, and a circuit pattern is determined by a pattern arrangement in one layer. Classifying into a second correction pattern group; setting an interlayer correction pattern creation specification for creating an interlayer proximity effect correction pattern for the first correction pattern group; Designing the circuit pattern, and determining whether or not the proximity effect correction pattern is effective in the proximity effect correction pattern of the interlayer, which is created based on the interlayer correction pattern creation specification for the first correction pattern group. When the proximity effect correction is determined to be invalid, such that the proximity effect correction becomes effective, Determining the validity of the proximity effect correction again after performing the correction of the fixed circuit pattern; and, when the proximity effect correction is determined to be valid, changing the circuit pattern belonging to the first correction pattern group. A step of registering a circuit pattern belonging to the second correction pattern group in the cell library while registering the cell pattern in the cell library; and a step of creating chip-level pattern data from the circuit pattern registered in the cell library. Setting an intra-layer correction pattern creation specification for creating an intra-layer proximity effect correction pattern for the second correction pattern group; and setting the first layer based on the inter-layer correction pattern creation specification. Generate proximity effect correction pattern data of an interlayer from circuit patterns belonging to a correction pattern group And the extent, on the basis of the intra-layer correction pattern creating specifications,
A step of generating intra-layer proximity effect correction pattern data from circuit patterns belonging to the second correction pattern group. 23. Among a plurality of circuit patterns included in an LSI, a first correction pattern group in which a circuit pattern is determined by a pattern arrangement over a plurality of layers, and a circuit pattern is determined by a pattern arrangement in one layer. Classifying into a second correction pattern group; setting an interlayer correction pattern creation specification for creating an interlayer proximity effect correction pattern for the first correction pattern group; Designing the circuit pattern, and determining whether or not the proximity effect correction pattern is effective in the proximity effect correction pattern of the interlayer, which is created based on the interlayer correction pattern creation specification for the first correction pattern group. When the proximity effect correction is determined to be invalid, such that the proximity effect correction becomes effective, After correcting the specified circuit pattern or the specification for creating an interlayer correction pattern of the circuit pattern, after re-determining the validity of the proximity effect correction, when the proximity effect correction is determined to be valid, Registering a circuit pattern belonging to a first correction pattern group and an interlayer correction pattern creation specification corresponding to the circuit pattern in a cell library, and registering a circuit pattern belonging to the second correction pattern group in the cell library; Generating chip-level pattern data from the circuit patterns registered in the cell library; and, based on the interlayer correction pattern generation specification, converting the circuit patterns belonging to the first correction pattern group into an interlayer. A step of creating proximity effect correction pattern data, and a predetermined intra-lay Based on the correction pattern creation specification, the second method of creating LSI mask data from the circuit patterns belonging to the correction pattern group characterized by comprising the step of creating a proximity effect correction pattern data of the intra-layer. 24. The step of judging the validity of the proximity effect correction is such that when there are a plurality of layouts of the circuit pattern for which the proximity effect correction is determined to be effective, the circuit area becomes smaller than a predetermined value from the plurality of layouts. 24. The method according to claim 21, further comprising a step of selecting a layout. 25. The specification according to claim 22, wherein the specification for creating an interlayer correction pattern is determined by an arrangement rule defining one layer including a gate of a transistor and another layer including an active region. The method of creating mask data for LSI according to any one of the above. 26. The inter-layer correction pattern creation specification, wherein an arrangement defining a first wiring layer and a layer including a contact for electrically connecting a second wiring layer different from the first wiring layer. 25. The method according to claim 22, wherein the method is determined by a rule. 27. The step of judging the effectiveness of the proximity effect correction includes performing a process simulation including at least one of a lithography step and an etching step to determine whether a predicted value of a processing dimension satisfies a predetermined value. 20. The method according to claim 15, wherein
25. The method for creating mask data for LSI according to any one of 21 to 24. 28. The lithography step in the process simulation, wherein a determination is made as to whether or not a predicted value of a processing dimension when the exposure amount or the focus position changes beyond the process allowance satisfies the predetermined value. 28. The method of generating mask data for LSI according to claim 27. 29. The L according to claim 27, wherein the determination of the process simulation includes a step of determining a dimension of the transistor in a gate length direction.
How to create SI mask data. 30. The layout of an LSI pattern according to claim 27, wherein the judgment of the process simulation includes a step of judging a protrusion of a gate of the transistor from an active layer in a gate width direction. How to make. 31. A plurality of circuit patterns included in an LSI, a first correction pattern group that does not change a pattern shape according to a change in process conditions, and a second correction pattern group that changes a pattern shape according to a change in process conditions. A step of classifying the plurality of circuit patterns into a group of correction patterns;
Generating a cell-level proximity effect correction pattern from the correction pattern group; and generating chip-level proximity effect correction pattern data from the second correction pattern group when generating chip data from the plurality of circuit patterns. A mask manufacturing step of manufacturing a mask using the created proximity effect correction pattern data; and a pattern forming step of forming the plurality of circuit patterns on a semiconductor substrate using the manufactured mask. A method for forming an LSI pattern, comprising: 32. A first correction pattern group that does not change a pattern shape according to a change in process conditions, and a second correction pattern group that changes a pattern shape according to a change in process conditions. Classifying into a correction pattern group; setting a cell-level correction pattern creation specification for creating a cell-level proximity effect correction pattern for the first correction pattern group; Designing; and determining whether or not the proximity effect correction is effective in the cell-level proximity effect correction pattern created by the cell level correction pattern creation specification for the first correction pattern group; When the proximity effect correction is determined to be invalid, the circuit pattern determined to be invalid is set so that the proximity effect correction is valid. After performing the correction, re-determining the validity of the proximity effect correction; and, when the proximity effect correction is determined to be valid, registering a circuit pattern belonging to the first correction pattern group in a cell library. Registering a circuit pattern belonging to the second correction pattern group in the cell library; generating chip-level pattern data from the circuit pattern registered in the cell library; Setting a chip level correction pattern creation specification for creating a chip level proximity effect correction pattern for the group; and a circuit belonging to the first correction pattern group based on the cell level correction pattern creation specification Creating cell-level proximity effect correction pattern data from the pattern; A step of creating chip-level proximity effect correction pattern data from the circuit patterns belonging to the second correction pattern group based on the pattern creation specifications; and a mask for producing a mask using the created proximity effect correction pattern data. A method for forming an LSI pattern, comprising: a manufacturing step; and a pattern forming step of forming the plurality of circuit patterns on a semiconductor substrate using the manufactured mask. 33. A plurality of circuit patterns included in an LSI, a first correction pattern group that does not change a pattern shape according to a change in process conditions, and a second correction pattern group that changes a pattern shape according to a change in process conditions. Classifying into a correction pattern group; setting a cell-level correction pattern creation specification for creating a cell-level proximity effect correction pattern for the first correction pattern group; Designing; and determining whether or not the proximity effect correction is effective in the cell-level proximity effect correction pattern created by the cell level correction pattern creation specification for the first correction pattern group; When it is determined that the proximity effect correction is invalid, the circuit pattern or the circuit determined to be invalid is set so that the proximity effect correction becomes valid. A step of re-determining the validity of the proximity effect correction after correcting the cell level correction pattern creation specification of the circuit pattern; and a step of determining the first correction pattern group when the proximity effect correction is determined to be valid. Registering a circuit pattern belonging to and a cell level correction pattern creation specification corresponding to the circuit pattern in a cell library, and registering a circuit pattern belonging to the second correction pattern group in the cell library; and Generating chip-level pattern data from the registered circuit patterns; and, based on the cell-level correction pattern generation specification, converting cell-level proximity effect correction pattern data from the circuit patterns belonging to the first correction pattern group. Based on the process of creating and the specified chip level correction pattern creation specification,
A step of generating chip-level proximity effect correction pattern data from the circuit patterns belonging to the second correction pattern group; a mask manufacturing step of manufacturing a mask using the generated proximity effect correction pattern data; A pattern forming step of forming the plurality of circuit patterns on a semiconductor substrate using a mask. 34. Among a plurality of circuit patterns included in an LSI, a first correction pattern group in which a circuit pattern is determined by a pattern arrangement over a plurality of layers, and a circuit pattern is determined by a pattern arrangement in one layer. A correction pattern group classification step of classifying the plurality of circuit patterns into a second correction pattern group;
An inter-layer correction pattern data generating step of generating an inter-layer proximity effect correction pattern data from the correction pattern group; and, when generating chip data from the plurality of circuit patterns, an intra-layer correction of the intra layer from the second correction pattern group. An intra-layer correction pattern data generating step of generating proximity effect correction pattern data; a mask manufacturing step of manufacturing a mask using the generated inter-layer and intra-layer proximity effect correction pattern data; and A pattern forming step of forming the plurality of circuit patterns on a semiconductor substrate. 35. A first correction pattern group in which a circuit pattern is determined by a pattern arrangement over a plurality of layers among a plurality of circuit patterns included in an LSI, and a circuit pattern is determined by a pattern arrangement in one layer. Classifying into a second correction pattern group; setting an interlayer correction pattern creation specification for creating an interlayer proximity effect correction pattern for the first correction pattern group; Designing the circuit pattern, and determining whether or not the proximity effect correction pattern is effective in the proximity effect correction pattern of the interlayer, which is created based on the interlayer correction pattern creation specification for the first correction pattern group. When the proximity effect correction is determined to be invalid, such that the proximity effect correction becomes effective, Determining the validity of the proximity effect correction again after performing the correction of the fixed circuit pattern; and, when the proximity effect correction is determined to be valid, changing the circuit pattern belonging to the first correction pattern group. A step of registering a circuit pattern belonging to the second correction pattern group in the cell library while registering the cell pattern in the cell library; and a step of creating chip-level pattern data from the circuit pattern registered in the cell library. Setting an intra-layer correction pattern creation specification for creating an intra-layer proximity effect correction pattern for the second correction pattern group; and setting the first layer based on the inter-layer correction pattern creation specification. Generate proximity effect correction pattern data of an interlayer from circuit patterns belonging to a correction pattern group And the extent, on the basis of the intra-layer correction pattern creating specifications,
A step of generating intra-layer proximity effect correction pattern data from the circuit patterns belonging to the second correction pattern group; and a method of manufacturing a mask using the generated inter-layer and intra-layer proximity effect correction pattern data. A method for forming an LSI pattern, comprising: a step of forming the plurality of circuit patterns on a semiconductor substrate using a manufactured mask. 36. Among a plurality of circuit patterns included in an LSI, a first correction pattern group in which a circuit pattern is determined by a pattern arrangement over a plurality of layers, and a circuit pattern is determined by a pattern arrangement in one layer. Classifying into a second correction pattern group; setting an interlayer correction pattern creation specification for creating an interlayer proximity effect correction pattern for the first correction pattern group; Designing the circuit pattern, and determining whether or not the proximity effect correction pattern is effective in the proximity effect correction pattern of the interlayer, which is created based on the interlayer correction pattern creation specification for the first correction pattern group. When the proximity effect correction is determined to be invalid, such that the proximity effect correction becomes effective, After correcting the specified circuit pattern or the specification for creating an interlayer correction pattern of the circuit pattern, after re-determining the validity of the proximity effect correction, when the proximity effect correction is determined to be valid, Registering a circuit pattern belonging to a first correction pattern group and an interlayer correction pattern creation specification corresponding to the circuit pattern in a cell library, and registering a circuit pattern belonging to the second correction pattern group in the cell library; Generating chip-level pattern data from the circuit patterns registered in the cell library; and, based on the interlayer correction pattern generation specification, converting the circuit patterns belonging to the first correction pattern group into an interlayer. A step of creating proximity effect correction pattern data, and a predetermined intra-lay Generating intra-layer proximity effect correction pattern data from the circuit patterns belonging to the second correction pattern group based on the correction pattern generation specification; and using the generated inter-layer and intra-layer proximity effect correction pattern data. Forming a plurality of circuit patterns on a semiconductor substrate by using the manufactured mask, and forming a pattern for an LSI. Method.