JP2008064820A - Method for designing mask pattern, device for designing mask pattern, and method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten the processing time of optical proximity effect correction (OPC). <P>SOLUTION: A mask layout pattern is generated by disposing a plurality of cells subjected to OPC processing. The mask layout pattern is divided into a plurality of segmented areas SA. The segmented area SA is composed of a cell as a base and has information of the cell and information of a reference area including a partial design pattern of other cells adjacent to the periphery of the cell. Each of the plurality of segmented areas SA are adjusted for OPC optimization in parallel. The figure of the reference area is updated between adjacent segmented areas SA. Then a plurality of optimized segmented areas SA are unified to generate a mask layout pattern. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a lithography mask technique, and more particularly to a mask pattern design technique, a mask pattern design apparatus, and a semiconductor device manufacturing technique for forming a pattern smaller than the exposure wavelength of photolithography.

  In the semiconductor industry, as the integration density of semiconductor integrated circuits increases, a technique for improving the resolution of photolithography for transferring an LSI pattern onto a semiconductor wafer has been demanded. Typical examples include super-resolution techniques such as phase shift masks and modified illumination.

  However, at present, it is difficult to maintain the fidelity of an LSI pattern transferred onto a semiconductor wafer only with these techniques. This is because an optical proximity effect (hereinafter abbreviated as OPE) becomes apparent as the LSI pattern to be transferred becomes finer.

  This is because, of the light diffracted by the mask pattern, only the diffracted light of the lower order component is collected on the semiconductor wafer, so that the outline of the mask pattern is not formed on the semiconductor wafer as it is and the corners of the pattern are rounded. This is a phenomenon in which the pattern shape accuracy is greatly deteriorated and the fidelity of the pattern is lowered.

  This OPE problem is diffracted by the mask pattern when half the minimum pitch of the LSI pattern to be transferred (half pitch: hereinafter referred to as hp) becomes less than the exposure wavelength as the semiconductor integrated circuit becomes finer. Of the light, only low order components can pass through the lens, and the order of the diffracted light that can reach the semiconductor wafer is lowered, which becomes remarkable. For example, although the exposure wavelength is 248 nm and hp is 350 nm (hp> exposure wavelength), it is not considered as a problem, but the 90 nm generation (hp <exposure wavelength) where the mainstream exposure wavelength is 193 nm and hp is 90 nm. In such optical lithography, OPE is a serious problem.

  Therefore, at present, optical proximity correction (hereinafter abbreviated as OPC) for generating a correction pattern that cancels the OPE is indispensable in the design of a mask pattern. This OPC is a technique for improving the transfer accuracy of an LSI pattern to a semiconductor wafer by predicting the OPE in advance and correcting the dimension and shape of the mask pattern.

  Currently used OPC methods can be roughly classified into rule-based OPC and model-based OPC.

The rule-based OPC creates a rule table that determines the shape and size of the corrected figure according to the distance and size of the adjacent pattern, and corrects the mask pattern accordingly. This method has the advantages that the calculation speed is fast and the amount of mask data after correction does not become too large.
However, in order to improve the correction accuracy, a more complicated rule is required, so that the workload for creating the rule increases. Further, as the semiconductor integrated circuit is further miniaturized, the influence range of the OPE exceeds the minimum distance between adjacent patterns, and the correction accuracy is rapidly deteriorated due to the OPE from the previous pattern. For this reason, in OPC with an hp of 130 nm or later, rule-based OPC is limited and used only for parts that do not require much accuracy.

  Such rule-based OPC is disclosed in, for example, Japanese Patent Laid-Open No. 2002-303964 (Patent Document 1) and Japanese Patent Laid-Open No. 2001-281836 (Patent Document 2). In the above-mentioned Patent Document 1, a graphic operation is performed according to the line width and the adjacent space width, and in the above-mentioned Patent Document 2, a line segment vectorization process and a line segment sort process are performed to perform the line width and space width Rule-based OPCs that perform pattern correction with reference to a correction table using a hash function are disclosed.

  In model-based OPC, the shape and dimensions of an exposure pattern that varies depending on OPE are predicted by optical simulation, and a corrected figure for canceling this is produced. Since this method can perform more precise correction than the rule-based OPC, it can cope with the correction accuracy of OPC whose hp is 130 nm generation or later.

  However, the model-based OPC has a problem that enormous calculation load (time, amount of mask data) is required because correction calculation is performed on all patterns constituting the mask pattern (chip entire surface OPC). In particular, since the optical simulation uses a calculation model based on the optical theory, the processing time increases in proportion to the square of the area (number of meshes × accuracy) of the layout pattern to be calculated. These calculation loads are increasing with the miniaturization of semiconductor integrated circuits, which is one of the serious factors that raise the mask cost. This problem has been recognized as a serious problem that hinders device miniaturization in the semiconductor industry.

  Such model-based OPC is disclosed in, for example, Japanese Patent Laid-Open No. 2004-061720 (Patent Document 3). Patent Document 3 discloses a model-based OPC that incorporates a process effect by a transfer experiment.

  In the model-based OPC using the optical simulator, the mask pattern is deformed until a desired transfer pattern is obtained. Various methods have been proposed depending on how to drive the mask pattern. For example, if the optical image is partially inflated, thin the part, and if it is thin, thicken that part, then recalculate the optical image in that state and gradually drive it in, so-called sequential improvement method is there. There has also been proposed a method of pursuing using a genetic algorithm. In the method using a genetic algorithm, a pattern is divided into a plurality of line segments, and the displacements of these line segments are assigned as displacement codes. This is a method in which the displacement code is regarded as a chromosome, genetic evolution is calculated, and the desired optical image is driven.

  The genetic algorithm is a search method using population genetics as a model, and is known for excellent performance such as high optimization performance without depending on the target problem. References for genetic algorithms include, for example, by David E. Goldberg, published in 1989 by ADISON-WESLEY PUBLISHING COMPANY, INC. Genetic Algorithms in Search, Optimization, and Machine Learning (Non-patent Document 1). An optimization method of OPC using a genetic algorithm is described in, for example, Japanese Patent No. 3512954 (Patent Document 4).

  In the genetic algorithm, solution candidates for a search problem are expressed by a bit string called a chromosome, and a character string operation is performed on a group consisting of a plurality of chromosomes so that survival competition is performed. Each chromosome is evaluated by an objective function that is a search problem itself, and the result is calculated as a fitness value that is a scalar value. Chromosomes with high fitness are given the opportunity to leave many offspring. Furthermore, a new chromosome is generated by performing crossover between chromosomes in the group and performing mutation. By repeating such processing, a chromosome with a higher fitness is generated, and the chromosome with the highest fitness becomes the final solution.

  However, in the conventional mask pattern design utilizing the above genetic algorithm, the OPC is performed on all the figures of the mask defining the circuit pattern of the semiconductor chip, so the number of figures increases with the miniaturization of the circuit pattern. Due to this, the processing time is enormous.

  There are cases where it takes several tens of hours for a 90 nm node device. In addition, because the exposure contrast is reduced by forming a pattern with a resolution that is extremely limited for exposure, the OPC becomes more complicated and has a larger number of figures for further miniaturization. For example, in the 65 nm node device, the time required for generating the mask pattern is as follows. It has come to last for several days. On the other hand, since the product cycle of the semiconductor device is shortened, shortening the OPC processing time is an extremely important issue in mask pattern design.

  For example, Japanese Patent Laid-Open No. 2002-328457 (Patent Document 5) describes a method of changing a figure for each part instead of the entire mask layout. The procedure first determines the environmental profile expressed in a specific format for each of the correction target cells included in the design layout data, depending on whether or not other figures exist around the target cell. To do. Then, referring to the cell replacement table, a replacement cell name that is the name of the correction pattern to be replaced corresponding to the determined environment profile is read, and after correction, layout data is generated. Finally, a correction pattern corresponding to the read replacement cell name is extracted from the cell library, and mask data that has been corrected is generated.

  Further, Japanese Patent Application Laid-Open No. 2006-058413 (Patent Document 6) and Japanese Patent Application Laid-Open No. 2005-156606 (Patent Document 7) disclose a dangerous place where a short circuit failure or an open failure is likely to occur in an actual lithography process. Is disclosed by optical simulation of the entire chip, and a technique for adjusting an OPC figure by arranging measurement points around a dangerous spot or performing more detailed simulation only around the dangerous spot.

  In addition, when there is a partial change such as ECO (engineering change order) in the mask design data after layout, such as “HALO-OPC” (software product) manufactured by APRIO in the United States, the affected part An EDA (Electronic Design Automation) tool is commercially available in which the processing time can be shortened by performing OPC processing again only for OPC processing of the entire mask layout.

  Puneet Gupta, Fook-Luen Heng and Mark Lavin, Merits of Sellwise Model-Based OPC Design and Process Integration for Microelectronic Manufacturing II (Merits of Cellwise Model-Based) OPC Design and Process Integration for Microelectronic Manufacturing II), edited by Lars W. Liebmann, Proc. Of SPIE Vol.5379,2004 (Non-Patent Document 2) ) Discloses a technique for predetermining an OPC figure inside a cell according to a surrounding situation assumed in advance.

  Further, cell-wise OPC (cell-wise OPC) has been proposed as a means for solving the problem of the model-based OPC on the entire surface of the chip. The feature of this cell-wise OPC is that the OPC is applied to each cell as a pre-stage of the layout design, thereby eliminating the need for the entire chip OPC and reducing the design time and the amount of mask data. In typical cell-wise OPC, OPC is applied to standard cells that are frequently used in the cell library design stage.

  For example, Xin Wang, et al., Exploiting Hi-Archiral Structure to Enhas Cell-Based RL with Localized OPC Reconfiguration Design and Process Integration for Microelectronic Manufacture Exploiting hierarchical structure to enhance cell-based RET with localized OPC reconfiguration, Design and Process Integration for Microelectronic Manufacturing III, edited by Lars W. Liebmann, Proceedings of SP I As described in Proceedings of SPIE Vol.5756,2005 (Non-patent Document 3), cell-wise OPC (Cell- A Wise OPC) scheme is disclosed.

Further, for example, in Japanese Patent Application Laid-Open No. 11-327120 (Patent Document 8), in order to efficiently simulate an enormous amount of mask pattern, the mask pattern is divided into a plurality of regions, and each of a plurality of arithmetic processing processors. A technique for executing light intensity simulation calculation for each mask pattern area divided into two is disclosed.
JP 2002-303964 A JP 2001-281836 A JP 2004-061720 A Japanese Patent No. 3512954 JP 2002-328457 A JP 2006-058413 A JP-A-2005-156606 JP-A-11-327120 David E. Goldberg, Genetic Algorithms in Search, Optimization, and Machine Learning, Addison Wesley Publishing Company (ADDISON-WESLEY PUBLISHINGCOMPANY, INC.) 1989 Gupta, Puneet Gupta, Fook-Luen Heng and Mark Lavin, Merits of Cellwise Model-Based OPC Design and Process Integration for Microelectronic Manufacturing II (Merits of Cellwise Model-Based OPC Design and Process Integration for Microelectronic Manufacturing II, edited by Lars W. Liebmann, Proc. of SPIE Vol.5379,2004 Xin Wang, et al., Exploiting hierarchical structure to enhance cell- Exploiting hierarchical structure to enhance cell-based arty with localized OPC reconfiguration design and process integration for microelectronic manufacturing III based RET with localized OPC reconfiguration, Design and Process Integration for Microelectronic Manufacturing III), edited by Lars W. Liebmann, Proceedings of SPIE Vol.5756,2005

  The method described in Patent Document 5 described above determines the optimum correction pattern to be replaced for all possible environment profiles for the correction target cell, gives a replacement cell name to each correction pattern, and sets the environment profile. And the replacement cell name must be associated with each other and stored in the cell replacement table in advance, so that there is a problem that the cost required for preparation is large and a large amount of storage area is required.

  Further, in Patent Document 6 and Patent Document 7 described above, OPC is performed by arranging measurement points around a dangerous spot obtained by optical simulation of the entire chip, or by performing more detailed simulation only around the dangerous spot. The processing time is shortened. However, these conventional techniques have a problem that the OPC processing time cannot be effectively shortened because a large amount of calculation time is required to detect the dangerous part.

  In addition, the EDA tool such as the above-mentioned HALO-OPC adopts a method in which when the OPC-processed mask layout data is corrected, only the surrounding area is subjected to the OPC process. Since processing is not performed in units, there is a problem that consistency with the design is inferior. In addition, since fidelity degradation called a hot spot is likely to occur during pattern transfer, a large calculation cost is required for the processing that is precisely obtained by the verification tool after the OPC processing at a place where a short circuit or disconnection is likely to occur. There is a problem.

  As described above, the conventional OPC technology has a problem that the processing time increases due to an increase in the number of figures accompanying the miniaturization of the circuit pattern, the semiconductor device manufacturing TAT (Turn Around Time) increases, and the manufacturing cost increases. Is difficult to solve.

  Further, in the above-mentioned sell-wise OPC, it is considered difficult to perform highly accurate correction for the following two reasons. First, since the OPE is affected by the adjacent cell, the optimal OPC figure varies greatly depending on the adjacent environment of the cell. In addition, the neighboring environment of the cell cannot be determined until after the layout. The second assumes an environment in which cells are laid out by defining a specific pattern in the periphery of each cell. For this reason, if an unexpected cell is laid out, it becomes difficult to cancel the OPE. That is, the above cell-wise OPC does not have sufficient correction accuracy for the influence of OPE from adjacent cells after cell layout, and requires more complicated calculations to ensure correction accuracy. The problem remains.

  Further, in the above-mentioned Patent Document 8, when dividing a mask pattern, the range of the divided region is determined so that the OPC processing can be performed efficiently by paying attention to the data amount and area, but the cell is divided although the efficiency is good. (That is, the pattern is divided), there is a problem that the transfer accuracy of a pattern transferred using a mask manufactured by this technique is lowered. Further, in Patent Document 8, sufficient consideration is not given to the change of the OPC graphic during the OPC adjustment, and there is a problem that the OPC graphic cannot be generated with high accuracy.

An object of the present invention is to shorten the OPC processing time.
Another object of the present invention is to shorten the manufacturing period of a semiconductor device.
Another object of the present invention is to reduce the manufacturing cost of a semiconductor device.
Another object of the present invention is to improve the OPC correction accuracy.
Still another object of the present invention is to cope with miniaturization of a semiconductor device.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
The present invention divides a mask layout pattern generated by arranging a plurality of cells subjected to OPC processing into a plurality of regions based on the cells, and adjusts each region for OPC optimization. Are performed in parallel.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

By dividing the mask layout pattern into a plurality of regions, the calculation area of the optical simulation can be reduced, so that the calculation time can be shortened.
Further, by dividing the mask layout pattern into a plurality of regions, the adjustment variable per region can be reduced, so that the convergence to the optimal solution can be improved. Further, since the divided areas can be simultaneously optimized by the parallel processing, the overall adjustment time can be shortened.

In addition, since the OPC processing time can be shortened when designing the mask pattern, the manufacturing TAT of the semiconductor device can be shortened. As a result, the manufacturing cost of the semiconductor device can be reduced.
In addition, since the cells are basically divided in dividing the mask layout pattern, the cells are not divided. For this reason, it is possible to improve the transfer accuracy of the pattern transferred using the mask to be manufactured.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following embodiments, the description is divided into a plurality of sections, examination examples, or embodiments. However, unless otherwise specified, they are not irrelevant to each other and have a supplementary explanation relationship. Or a detailed explanation. In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted as much as possible.

(Examination example 1)
In order to verify the effectiveness of this study example 1, this study example 1 was applied to one of the mask patterns used for the gate of the SRAM (Static RAM) shown in FIG. 1 as a cell.
First, a verification experiment was conducted to determine whether the transfer of the mask pattern is affected by the surrounding environment. Next, the pattern design method using the genetic algorithm which is the method of the present examination example 1 was applied to the pattern having the strongest influence among them, and a verification experiment was conducted as to whether or not the pattern could be optimized. In the experiments described below, verification was performed under lithography conditions as shown in Table 1.

(Verification experiment 1)
First, a verification experiment was conducted to determine whether the mask pattern was affected by the difference in the surrounding environment. Mask patterns P1 to P10 used in this verification experiment are shown in FIGS. Since these ten mask patterns P1 to P10 are designed with a width of 90 nm, the ideal line width is 90 nm. In this experiment, by creating these transfer patterns and comparing two values of the line width (S31) and the gap (S32) shown in FIG. 12 (enlarged view of the region S12 shown in FIG. 1) as evaluation values, The influence of the surrounding environment was verified. The transfer pattern is generated by optical simulation software. As such software, for example, “SOLID-C” of RISOTEC JAPAN is well known to those skilled in the art (reference URL; <http://www.ltj.co.jp/index.html>).
Table 2 shows two evaluation values of the transfer patterns of the mask patterns P1 to P10.

  The pattern P1 has an ideal line width because there is no influence of the surrounding environment, but the pattern P2 or P3 has a large influence from the periphery. Compared with P1, the line width (S31) has a gap ( It can be seen that S32) is also greatly deviated.

  FIG. 13A shows an ideal transfer pattern of the mask pattern P1. FIG. 13B shows a transfer pattern of the mask pattern P3 having the greatest influence. It can be seen that the pattern P3 is largely influenced not by the line width (S31) or the gap (S32) as a whole. Further, when comparing the evaluation values of other patterns, it can be seen that the degree of influence of each pattern on the transfer pattern varies depending on the surrounding environment. Since an actual mask pattern is used in combination with various cells, it can be expected that the influence of each cell is very large and complicated. Therefore, even in the mask pattern of the same design, it is indispensable to make a complicated optimization of the OPC figure according to the surrounding environment.

(Verification experiment 2)
A verification experiment was conducted to determine whether the influence of the surrounding environment proved in the verification experiment 1 can be solved by the method of the present examination example 1. In this verification experiment, as the simplest example, a simulation was performed to optimize the mask pattern P3 (FIG. 14) that was most affected in the verification experiment 1 and the mask pattern P1 (FIG. 15) that is closest to the ideal. . In this simulation, the optimization of the method of the present study example 1 is performed using the two locations (S71 and S72) in the cell shown in FIG. 16 (enlarged view of the transfer pattern of the region S12 shown in FIG. 1) as the optimization parameters. It was.

The following describes how to apply the genetic algorithm. First, the calculation procedure of the genetic algorithm will be described. FIG. 17 is a flowchart showing the most basic calculation procedure of the genetic algorithm. The purpose and outline of each process are as follows.
Initialization: A plurality of chromosomes as solution candidates are randomly generated to form a group. The optimization problem to be solved is expressed as an evaluation function that returns a scalar value.
Chromosome evaluation: The chromosome is evaluated using an evaluation function, and the fitness of each chromosome is calculated.
Generation of the next generation population: Using genetic manipulation (selection, crossover, mutation) gives the opportunity to leave more offspring for chromosomes with higher fitness.
Search end criterion determination: The evaluation of the chromosome and the generation of the next generation population are repeated until a predetermined condition is satisfied.

  The outline of the genetic algorithm is shown below based on FIG. First, in “initialization”, “definition of chromosome expression”, “determination of evaluation function”, and “generation of initial chromosome population” are performed.

  "Definition of chromosome expression" defines what kind of data is transmitted in what form from parental chromosomes to descendant chromosomes during generational changes. FIG. 18 illustrates a chromosome. Here, each element xi (i = 1, 2,..., XD) of a D-dimensional variable vector X = (x1, x2,..., XD) that represents a point in the solution space of the optimization problem of interest. D) is represented by a sequence of M symbols Ai (i = 1, 2,..., M), and this is regarded as a chromosome composed of D × M genes. As the gene value Ai, a set of integers, a range of real values, a symbol string, and the like are used according to the nature of the problem to be solved. FIG. 18 shows the use of four symbols {0, 1} (that is, M = 4) for each variable for one candidate solution of a five-dimensional optimization problem, that is, five variables (that is, D = 5). It is an example when expressed as. The gene string thus symbolized is a chromosome.

  Next, in the “determination of evaluation function”, a fitness calculation method representing how much each chromosome is adapted to the environment is defined. At this time, the design is made so that the fitness of the chromosome corresponding to the variable vector, which is excellent as a solution to the optimization problem to be solved, becomes high.

  In “generation of initial chromosome population”, N chromosomes are normally randomly generated according to the rules determined in “Definition of chromosome expression”. This is because the characteristics of the optimization problem to be solved are unknown, and what kind of chromosome is superior is completely unknown. However, if there is some a priori knowledge about the problem, the search speed and accuracy may be improved by generating a chromosomal population centering on a region that is predicted to have high fitness in the solution space.

  In “chromosome evaluation”, the fitness of each chromosome in the population is calculated based on the method defined in “determination of evaluation function”.

  In the “generation of the next generation population”, a genetic operation is performed on the chromosome population based on the fitness of each chromosome to generate the next generation chromosome population. Typical procedures for genetic manipulation include selection, crossover, mutation, etc., and these are collectively referred to as genetic manipulation.

  In “selection”, a chromosome with high fitness is extracted from the chromosome population of the current generation, left in the next generation population, and conversely, the chromosome with low fitness is removed.

  “Crossover” is an operation of creating a new chromosome by randomly selecting a pair of chromosomes with a predetermined probability from a group of chromosomes extracted by selection and rearranging a part of their genes.

  In “mutation”, chromosomes are randomly selected with a predetermined probability from a group of chromosomes extracted by selection, and a gene is changed with a predetermined probability with a predetermined probability. Here, the probability that a mutation will occur is called the mutation rate.

In “search end criterion determination”, it is checked whether or not the generated next-generation chromosome population satisfies a criterion for ending the search. When the criterion is satisfied, the search is terminated, and the chromosome having the highest fitness in the chromosome population at that time is determined as the solution of the optimization problem to be obtained. If the termination condition is not satisfied, the process returns to the “chromosome evaluation” process to continue the search. The termination criterion of the search process depends on the nature of the optimization problem to be solved, but typical ones are as follows.
(A) The maximum fitness in the chromosome population was greater than a certain threshold.
(B) The average fitness of the entire chromosome population is greater than a certain threshold.
(C) A generation in which the fitness rate of the chromosome population is below a certain threshold has continued for a certain period or more.
(D) The number of generation changes has reached a predetermined number.

  Next, each step of the present embodiment based on the above-described genetic algorithm calculation procedure will be described in detail.

[Initialization: Definition of chromosome expression]
In this simulation, since two locations (S71 and S72) in the cell shown in FIG. 16 are used as optimization parameters, the variable vector X is regarded as a two-dimensional vector such as X = (x1, x2), and each element xi (i = 1, 2) is expressed by a real number. Note that S73 always takes the same value as S72.

[Initialization: Determination of evaluation function]
Since the fitness cannot be defined by an explicit function, the fitness calculation procedure consisting of the following four steps is adopted.
Step (1): A graphic pattern is reconstructed using a variable vector uniquely determined from a chromosome.
Step (2): An optical simulation is performed to calculate an exposure pattern.
Step (3): For the calculated exposure pattern, the line width (S31) and gap (S32) shown in FIG. 12 are measured, and the sum of errors from the design value is calculated.
Step (4): Since the goal here is to obtain an exposure pattern that is as close as possible to the design value, the smaller the error, the better. Therefore, the reciprocal of the sum of the measured errors is set as the fitness.

[Initialization: Generation of early chromosome population]
According to the rule determined in the above-mentioned “initialization: definition of chromosome expression”, a vector composed of two real-value elements is defined as a chromosome. The number of chromosomes N is 100, and 100 chromosomes are randomly generated using a pseudo random number generator.

[Chromosome evaluation]
According to the chromosome evaluation procedure determined in “Initialization: Determination of evaluation function”, all chromosomes are evaluated and fitness is calculated.

[Generation of next generation population: selection]
In this embodiment, roulette selection is used. In this method, the probability that each chromosome can survive in the next generation is proportional to the fitness. In other words, the higher the fitness, the more the arrangement on the roulette, and the higher the probability of hitting the roulette. Specifically, when the size of the chromosome population is N, the fitness of the i-th chromosome is Fi, and the total fitness of all chromosomes is Σ, the procedure for extracting each chromosome with the probability of (Fi ÷ Σ) This is realized by repeating N times. In the above case, since the number of chromosomes is 100, 100 next-generation chromosomes are selected by repeating 100 times.

[Generation of next generation population: crossover]
In this embodiment, uniform crossover is used. This is a method in which two chromosomes are selected from each chromosome group, and at each locus, it is randomly determined whether or not to replace a variable that is a gene. Specifically, the selected two chromosomes are X ¹ = (x ¹ ₁ , x ¹ ₂ ) and X ² = (x ² ₁ , x ² ₂ ), respectively, and 0 or 2 with a probability of 1/2 Random number generation that outputs 1 is performed twice. The first random number is for the first locus. If it is 1, x ¹ ₁ and x ² ₁ are exchanged, and if it is 0, they are not exchanged. The same applies to the treatment for the second locus.

[Generation of next generation population: mutation]
In this embodiment, a process of adding random numbers generated according to a normal distribution to loci selected at a mutation rate PM according to a uniform distribution is adopted. Here, the mutation rate P _M = 1/50, the average of normal distribution u = 0, and the standard deviation σ = 5 × 10 9 are set.

Search termination condition
In the present embodiment, the search is terminated when a chromosome having an error from the design value of 0 is found or when the chromosome is evaluated 5000 times.
As a result of the verification experiment using the genetic algorithm as described above, the results shown in Table 3 were obtained by optimizing the parameters shown in FIG.

  As shown in Table 3, the line width (S31) of the transfer pattern was narrowed by about 16 nm as shown in Table 2 of the verification experiment 1 in the surrounding environment of FIG. It can be seen that it has been optimized to about 90 nm, which is close to the ideal FIG.

  From this experiment, it was confirmed that the technique of the present study example 1 can optimize the shift of the transfer pattern due to the influence of the surrounding environment in the mask pattern design. In the first study example, the case where the simple sum of the errors of the line width (S31) and the gap (S32) is used has been described. Such a simple sum is general-purpose, but a method of calculating a sum by weighting according to the importance of a place is also useful. For example, when dimensional control of the line width (S31) serving as a gate is important, the accuracy of a necessary portion can be relatively improved by multiplying the value of the gap (S32) by a coefficient such as 2 or 3. .

(Examination example 2)
A study example 2 in which a semiconductor device is manufactured using a mask designed by the mask pattern design method of the present application will be described.

19A to 19C show a 2-input NAND gate circuit ND, where FIG. 19A is a symbol diagram, FIG. 19B is a circuit diagram, and FIG. 19C is a plane showing a pattern layout. FIG. FIG. 20 is an enlarged plan view of FIG. 19 (c).
In FIG. 19 (c), a portion surrounded by an alternate long and short dash line is a unit cell 110, two nMOS portions Qn formed on the n-type semiconductor region 111n on the surface of the p-type well region PW, and an n-type well. It is composed of two pMOS portions Qp formed on the p-type semiconductor region 111p on the surface of the region NW.

  In order to manufacture this structure, pattern transfer by normal photolithography was repeatedly used by sequentially using six types of masks M1 to M6 as shown in FIGS. Among these, the masks M1 to M3 have a relatively large size pattern, so the pattern OPC process was not performed. In the drawing, reference numerals 101a, 101b, and 101c denote light transmitting portions, and reference numerals 102a, 102b, and 102c denote light shielding portions made of a chromium film. On the other hand, since the masks M4 to M6 have a fine pattern, the pattern design method of the present embodiment is used to appropriately change the outline and size of the pattern figure and perform optimization. In the figure, reference numerals 101d, 101e, and 101f denote light transmitting portions, and reference numerals 102d, 102e, and 102f denote light shielding portions.

  In FIG. 20 showing the same layout as FIG. 19C, assuming the cross section along the broken line, the steps until the channels Qp and Qn are formed using the cross section are shown in FIGS. And it demonstrates sequentially using FIG. 23 (a)-(e).

  An insulating film 115 made of, for example, a silicon oxide film is formed on the wafer S (W) made of P-type silicon single crystal by an oxidation method, and then, for example, a silicon nitride film 116 is formed thereon by a CVD (Chemical Vapor Deposition) method. Then, a resist film 117 is formed thereon (FIG. 22A). Next, an exposure and development process is performed using the mask M1 to form a resist pattern 117a (FIG. 22B). Thereafter, using the resist pattern 117a as an etching mask, the insulating film 115 and the silicon nitride film 116 exposed from the resist pattern 117a are sequentially removed, and the resist pattern 117a is further removed to form a groove 118 on the surface of the wafer S (W) (FIG. 22). (C)). Next, after an insulating film 119 made of, for example, silicon oxide is deposited by a CVD method or the like (FIG. 22D), a planarization process is performed by, for example, a chemical mechanical polishing (CMP) method, and the like. An element isolation structure SG is formed on (FIG. 22E). In the present examination example 2, the element isolation structure SG is a trench type isolation structure, but is not limited to this, and may be formed of a field insulating film by, for example, a LOCOS (Local Oxidization of Silicon) method.

  Subsequently, exposure and development are performed using the mask M2 to form a resist pattern 117b. Since the region where the n-type well region is to be formed is exposed, phosphorus or arsenic is ion-implanted to form the n-type well region NW (FIG. 23A). Similarly, after a resist pattern 117c is formed by the mask M3, for example, boron or the like is ion-implanted to form a p-type well region PW (FIG. 23B). Next, a gate insulating film 120 made of a silicon oxide film is formed to a thickness of 3 nm by a thermal oxidation method, and a polycrystalline silicon film 112 is deposited thereon by a CVD method or the like (FIG. 23C).

  Subsequently, after applying a resist, a resist pattern 117d is formed using a mask M4, and a gate insulating film 120 and a gate electrode 112A are formed by etching the polycrystalline silicon layer 112 and removing the resist (FIG. 23D). Thereafter, a high impurity concentration n-type semiconductor region 111n for the n-channel MOS functioning as a source, drain region and wiring layer and a high impurity concentration p-type semiconductor region 111p for the p-channel MOS are formed by ion implantation or diffusion method. A channel Qp and a channel Qn are formed in a self-aligned manner with respect to the gate electrode 112A (FIG. 23E).

  In the subsequent steps, a 2-input NAND gate group is manufactured by appropriately selecting the wiring. Here, it goes without saying that another circuit such as a NOR gate circuit can be formed by changing the shape of the wiring. Here, an example of manufacturing a two-input NAND gate will be continued using masks M5 and M6 shown in FIGS. 21 (e) and 21 (f), respectively.

  FIG. 24A to FIG. 24E are cross-sectional views along the broken line shown in FIG. 20 and show a wiring formation process. An interlayer insulating film 121a made of, for example, a silicon oxide film doped with phosphorus is deposited on the two n-channel MOS portions Qn and the two p-channel MOS portions Qp by the CVD method (FIG. 24A). Subsequently, a resist is applied, a resist pattern 117e is formed using the mask M5, and then contact holes CNT are formed by an etching process (FIG. 24B). After removing the resist, a metal such as tungsten, tungsten alloy or copper is buried, and at the same time, these metal layers 113 are further formed (FIG. 24C). Subsequently, a resist is applied, a resist pattern 117f is formed using the mask M6, and then wirings 113A to 113C are formed by an etching process (FIG. 24D). Thereafter, an interlayer insulating film 121b is formed, and further, a through hole TH and an upper layer wiring 114A are formed using another mask (not shown) (FIG. 24 (e)). The connection between components is performed by pattern formation by repeating the same process as many times as necessary to manufacture a semiconductor device.

  As described above, by applying the method of the present study example 2, it is possible to guarantee the pattern accuracy and manufacture a semiconductor device using a highly reliable mask.

  Of the masks constituting the cell library, the light shielding portion 102d in the mask M4 in particular constitutes the gate pattern with the shortest dimension, and the required accuracy of the dimension of the transfer pattern is the strictest. Therefore, when the cell library pattern shown in the mask M4 (FIG. 21D) is arranged on the entire surface of the mask, the method of this examination example 2 is adopted.

The entire mask pattern is composed of a plurality of cells, and two I-shaped figures are arranged in each cell (see FIG. 25). As shown in the figure, each cell has 10 adjustment points from p ₁ to p ₁₀ . Therefore, if the number of _cells is N _cells , it is necessary to adjust (N _cell × 10) parameters in the entire mask pattern.

[Initialization: Definition of chromosome expression]
In Study Example 2, each variable is treated as a real number that directly indicates the size of the figure. In other words, each element x _i (i = 1, 2,..., 10) of the variable vector X is expressed by a real number, and each of them is represented by p _i (i = 1, 2,..., 10) in FIG. It shall correspond to.
At this time, it is also possible to express the difference from the design target instead of the value of the dimension itself. For example, in the case of FIG. 26, the shaded figure is a mask pattern subjected to OPC, and the upper horizontal bar and the lower horizontal bar of one “I” -shaped figure are vertically symmetrical with respect to the design target indicated by a chain line. In addition, the thickness of the vertical bar can be changed symmetrically, and each dimension q _i (i = 1, 2,..., 10) can be specified to specify the mask. A pattern is uniquely determined. That is, an optimal mask pattern is obtained by a genetic algorithm by regarding the variable vector X = (q ₁ , q ₂ ,..., Q ₁₀ ) as a chromosome.

In this example 2, since a mask pattern in which N _{cells of the} same type are arranged is handled, the length of the chromosome is also N _cell times, and X = (X ¹ X ² ... X ^Ncell ) = (x ¹ ₁ , ..., x ¹ ₁₀ , ..., xN ^cell ₁ , ..., xN ^cell ₁₀ ). Here, X ^j represents a variable vector composed of 10 elements for designating the graphic shape included in the j th cell, and x ^j _i represents the i th element of the variable vector corresponding to the j th cell. It shall be shown.

Also, instead of a real value representing the elements x _i of the variable vector X, the upper limit value and the lower limit value, and by determining the number of quantization steps may be n-ary representation.

When the same cells are regularly arranged repeatedly, such as in a memory, the optimal value search is not performed for all the variable vectors of all cells, but the chromosome length is reduced by grouping. , Can facilitate optimization. For example, in FIG. 27, assuming that all the cells are composed of the same kind of graphic pattern and that the graphic is bilaterally symmetric and vertical symmetric, the variable vectors of all the cells are not all optimized, but type A To F, and only the variable vector (X ¹ X ² ... X ⁴ ) that defines the shape of the four cells is optimized, and the result is applied to all cells by type. The same effect as that obtained by adjusting the entire mask can be obtained.

  For example, in FIG. 27, the cell 81 has no upper five cells on the left and eight left cells, and three cells (82, 83, 84) on the right and lower sides. Further, the cell 90 and its surrounding cells (89, 92, 91) are arranged symmetrically with respect to the cell 81 and its surrounding cells (82, 83, 84), and the cell 87 and its surrounding cells (88). , 85, 86) are arranged vertically symmetrically. Therefore, the optimization result of the cell 81 can be used for the cell 90 and the cell 87 as well. In this way, the optimization adjustment process can be omitted.

[Initialization: Determination of evaluation function]
As a method for obtaining the fitness of the chromosome, the procedure similar to that in the examination example 1 is adopted here. However, the measurement of the dimension in step (3) was performed at four places (a _{1 to} a ₄ ) shown in FIG. In the production of a normal semiconductor chip, there are a portion where a slight error is not allowed and a portion where accuracy is not required with respect to the required dimensional accuracy. Therefore, by selectively measuring the size of a portion that requires high accuracy and performing fitness calculation, optimization that reflects the intention of the mask designer can be facilitated. Similarly, in the mask design stage, when it is possible to identify a location where the optical proximity effect is likely to occur, when calculating the fitness, a large weight is given to that portion, so that it is prioritized from a location that is difficult to adjust. Optimization can be facilitated.

  In this examination example 2, in order to compare the resist pattern predicted by simulation and the design value, the dimensions of several places were measured in step (3) of the fitness calculation, but as shown in FIG. By using the area of the difference graphic between the resist pattern and the design pattern, it is possible to detect an unexpected abnormality at a location where the dimension is not measured without omission. In this case, parameter optimization by a genetic algorithm is performed using the reciprocal of the area of the difference graphic as an evaluation value.

  Further, in step (4) of fitness calculation, the reciprocal of the sum of errors is adopted as fitness, but a subtraction value from a predetermined constant may be used as fitness. Further, in the fitness calculation step (2), the acid diffusion simulation is also performed, so that the resist pattern can be predicted more accurately, so that the optimization accuracy can be improved.

[Initialization: Generation of early chromosome population]
Similar to the examination example 1, an initial chromosome population is randomly generated. In order to improve the search speed, it is possible to start from an initial group obtained by applying a small perturbation to the result corrected by the model-based OPC.

[Chromosome evaluation]
Similar to the examination example 1, all chromosomes are evaluated according to the chromosome evaluation procedure determined in the above-mentioned “initialization: determination of evaluation function”, and fitness is calculated.

[Generation of next generation population: selection]
The roulette selection method is used as in the first examination example. Crossover methods such as tournament selection method and rank selection method, and generation change models such as MGG (Minimal Generation Gap) method may be used (reference: Sato et al., “Proposal and Evaluation of Generation Change Models in Genetic Algorithms” "Journal of the Japanese Society for Artificial Intelligence, Vol.12, No.5, 1997).

[Generation of next generation population: crossover]
Similar to the examination example 1, uniform crossover is used. In addition, instead of exchanging randomly selected loci, values obtained by weighted averaging may be used.
To improve search speed and accuracy, UNDX (Unimodal Normal Distribution Crossover), simplex crossover, EDX (Extrapolation-directed Crossover), etc., developed for real-valued chromosomes may be used. (Reference: Sakuma et al., “Optimization of nonlinear functions using real-valued GAs: Problems and solutions in higher-dimensional search space”, 15th Annual Meeting of the Japanese Society for Artificial Intelligence, 2nd AI Younger Gathering, MYCOM2001, 2001).
When a chromosome is represented by a binary vector, multipoint crossover can be used in addition to uniform crossover.

[Generation of next generation population: mutation]
Similar to the first study example, mutation using random numbers generated according to a normal distribution is used. In order to improve the search speed and accuracy, the adaptive speed of the entire population may be monitored and the Adaptive Mutation method may be used in combination to temporarily increase the mutation rate if it has not improved for a certain period of time.

Search termination condition
Similar to the examination example 1, the search is terminated when the error from the design value is 0 or below a certain value, or when the number of chromosome evaluations is above a certain value.
The above is the explanation of the genetic algorithm used in this study example 2. For example, the search can be performed by using other search methods such as hill climbing method, simplex method, steepest descent method, annealing method, dynamic programming method, etc. Speed and accuracy can be improved. In addition to genetic algorithms, the search speed can be increased by using other blind search methods or stochastic search methods such as Evolution Strategy (ES) and Genetic Programming (GP). Improvement and accuracy improvement can be realized.
In the above, a semiconductor chip is created using a cell library that has been subjected to OPC processing in advance, and the influence of surrounding cell libraries is optimized using a genetic algorithm capable of high-speed processing. Compared with the conventional method of processing, the processing time can be shortened to 1/10 or less.

(Examination example 3)
A system LSI having an SRAM portion and a logic circuit portion was manufactured using the mask pattern generation method described in Study Example 1. This system LSI has a minimum gate width of 40 nm and a minimum pitch of 160 nm. The logic circuit section allows arbitrary pitch wiring, and there is no placement restriction other than the minimum spacing between cells. For this reason, the conventional IP can be inherited, the platform is highly deployable, and the layout rule can be applied to various products.

  If a correction pattern of this size is created by the rule-based OPC under the above-described loose layout rule, partial variation occurs in the gate pattern size in the active region. For example, the base portion near the pad is constricted or fattened, which deteriorates the device characteristics. There is also a problem that the exposure margin with respect to the exposure amount fluctuation and the focus fluctuation is small and the yield as a semiconductor device is low. Moreover, when a mask creation pattern was generated by a commercially available model-based OPC, it took a long time of 7 days.

  The system LSI is for a specific user, has a short product cycle, and needs to be manufactured in a short time. The period is a lifeline, and it affects not only the value as a device but also the marketability of products incorporating it. When processing is preferentially performed by single wafer processing, the wafer process period is a minimum of two weeks, and the mask supply becomes quick. Conventionally, in order to make the generation period of the mask creation pattern about a practical one day, rule-based OPC has to be partially applied, which causes problems such as a decrease in yield as described above.

  By applying the mask pattern generation method described in the study example 1, the time required for mask pattern creation is one day, and device characteristics and yield equivalent to those obtained when the model base OPC is applied to the entire surface can be obtained. It was. By applying single wafer processing to the wafer process, the wafer process waiting time can be reduced, and the balance between the mask supply speed and the shipping timing of the system LSI can be obtained.

  The above will be described with reference to FIG. FIG. 30 shows the mask pattern data preparation, mask fabrication, and wafer process steps of the system LSI in the form of a flowchart. The mask pattern data preparation process is shown on the left, the mask production is shown in the center, and the wafer process process and timing are shown on the right.

  When the pattern layout design is completed based on the logical design, the LSI is manufactured. The wafer process flow includes film formation for making element isolation (isolation between active regions), lithography, etching, embedding an insulating film, lithography for manufacturing a dummy pattern for further planarization, etching, and CMP. Subsequently, an element isolation structure is formed. Then, lithography for ion implantation and ion implantation are performed to form a well layer, film formation for gate, lithography, etching, lithography for ion implantation separation, ion implantation, film formation for LDD, LDD processing, ion Implantation is performed to form a gate. Thereafter, an insulating film is formed, contact hole lithography and etching are performed to open the conduction hole, and after forming the conductive film, lithography and etching are performed to form a wiring layer. Thereafter, although not shown, interlayer wiring is formed by forming an interlayer insulating film, forming an opening, depositing a conductive film, and CMP.

  It is necessary to prepare a mask so as to correspond to the wafer process flow described above. Masks are roughly classified into critical layer and non-critical layer that require dimensional accuracy, and the former requires OPC with a large amount of data. In the latter case, simplified OPC, simple graphic operation, or data itself is sufficient. Typical critical layers are isolation, gate, contact, and first and second wirings.

  The mask pattern OPC data first determines whether or not it is a critical layer, and then enters a production procedure. First, preparation for necessary element isolation is performed. Subsequently, a suitable one is extracted from an already created OPE (Optical Proximity Effect) correction cell library, and these patterns are combined to form a 0th-order OPC-completed pattern. Then, based on the genetic algorithm method of the examination example 1, correction is performed in consideration of the influence of the adjacent pattern to create a final OPC pattern, and a mask is manufactured based on the data. Next, pattern data and a mask for the gate layer, contact layer, and wiring layer are prepared by the same method. Here, the procedure for preparing the layers in series has been shown, but they may be prepared in parallel. However, in parallel, multiple data creation systems are required, and large facilities are required. If each layer can be processed in series and the processing speed matches the timing of wafer processing, there is an advantage that the system can be downsized. In the non-critical layer, mask pattern data is prepared using another path as described above.

  Since the isolation layer, which is a critical layer, is a cueing layer, if the mask preparation is delayed, wafer delivery is also delayed. For this reason, the completion period of the mask pattern data of the isolation layer is very important. In this study example 3, it was possible to prepare in one day when combined with mask production, and it was halved compared to the normal two days.

Until the next gate layer lithography, there are 9 steps in this broad category, and there are about 50 steps (not shown) including detailed steps such as cleaning, but if it is processed by single wafer processing, it can be processed in 2 days . If a gate layer mask is not prepared during this period, loss due to standby occurs. Since the gate requires extremely high dimensional accuracy, according to the conventional method, it takes about 1 day for mask drawing and inspection, and 7 days for preparing mask pattern data. Thus, in the case of the conventional method, it is extremely difficult to prepare mask pattern data so as to keep up with the speed of wafer processing even if the data creation facility is enlarged and data creation is started in parallel with the element isolation pattern creation. Met. On the other hand, according to the present examination example 3, it was possible to prepare mask pattern data in one day even with a small pattern data creation facility.
Since high dimensional accuracy is required for the gate pattern, it is difficult to ensure sufficient device characteristics in the rule-based OPC. However, in the model-based OPC, complicated processing is required. This problem is more serious than in other layers. For this reason, the manufacturing method of the present embodiment is particularly effective for creating a gate pattern.

(Examination example 4)
The other examination example of the variable which should be adjusted of this application is shown. Reference numeral 1001 in FIG. 31 denotes a cell of a target cell library, and a pattern formed in the cell library is subjected to an OPC process in advance for a single cell. Among these, a peripheral area (first area) indicated by hatching is an area including a pattern subjected to OPC correction due to the influence of cells arranged in the periphery, and its width 1002 is an exposure wavelength of the exposure apparatus. It depends on λ, the numerical aperture NA of the lens used, the acid diffusion constant of the resist used, and the standard dimensional accuracy.

  The peripheral region is a region for correcting the influence of interference caused by overlapping of diffracted light from patterns constituting adjacent cells. Therefore, in order to determine the range of the peripheral region, the diffraction image intensity indicating the point image intensity distribution of the exposure optical system that projects the mask pattern will be considered.

The intensity I of the diffraction image is represented by I (2π × ρ × NA / λ) = (2 × J ₁ (2π × ρ × NA / λ) / (2π × ρ × NA / λ)) ² . Here, J ₁ : 1st order Bessel function, λ: wavelength, ρ: image radius. The relationship between 2π × ρ × NA / λ and intensity I is shown in FIG. Thus, if the radius at which I = 0 is initially set to ρ1, ρ1 = 0.61λ / NA. Further, assuming that the radius to the second-order diffraction image where I = 0 for the second time is ρ2, and the radius to the third-order third-order diffraction image is ρ3, ρ2 = 1.12λ / NA and ρ3 = 1.62λ / NA. It becomes. Since the maximum intensity of the third-order diffraction image is 0.2% or less of the zero-order diffraction image (see FIG. 44), the influence of interference by the third-order diffraction image may be considered to be negligibly small. That is, it was found that the range of influence of the change in the OPC pattern on the periphery is up to the third-order diffraction image, and sufficient accuracy can be obtained even if the peripheral region is 1.62λ / NA from the end of the cell.

In this case, the wavelength lambda 193 nm, 0.7 to NA, average size 5 × 5 [mu] m ² of the cell, when the chip size is assumed to 81.92 × 81.92μm ^2, the calculation area required to obtain the simulation results The size can be reduced to about 1/3 compared with the whole chip calculation. In lithography simulation, since a two-dimensional projection image on a wafer is calculated, the calculation amount is proportional to the square of the calculation area. Therefore, when the calculation area is reduced to about 1/3, the calculation amount is reduced to about 1/9.

  Further, when the cell arrangement density is sparse or the size of the adjacent cell is small, the diffracted light is reduced and the influence of interference is reduced, so the width of the peripheral region is set to the radius up to the second-order diffraction image. Even with the corresponding 1.12λ / NA, correction with sufficient accuracy is possible. In this case, assuming the average cell size and the chip size in the same manner as described above, the calculation area is about 1/4 compared with the whole chip calculation, and the calculation amount can be reduced to about 1/16.

  Although the width of the peripheral region where sufficient accuracy can be obtained is 1.62λ / NA, if this value is not on the grid of the mask design, the value should be on the grid in the vicinity of 1.62λ / NA. Good.

  An example of the pattern layout in the peripheral area is shown in FIG. In the figure, reference numeral 1003 denotes a cell boundary region, 1004 denotes an active region (diffusion layer region), 1005 denotes a gate and a gate wiring, and 1006 denotes a conduction hole (usually called a contact). The outside of the active region 1004 is an insulating region from the semiconductor substrate called a field, which is a region called isolation (element isolation). In relation to the arrangement of cells, a portion that requires correction processing after being subjected to OPC processing in units of cells will be described separately for an active layer (isolation layer), a gate layer, and a contact layer.

[Isolation layer]
The gate width w1, the contact-diffusion interlayer alignment margins d1, d2, the resolution failure (pattern connection failure) avoidance margin s1 between the adjacent cells, and the gate wiring run-in failure avoidance margin s2 shown in FIG. It is an OPC adjustment site. When the gate width w1 does not fit within the standard accuracy, the transistor characteristics deteriorate due to the narrow channel effect, and if the contact-diffusion interlayer alignment margins d1 and d2 cannot be obtained, conduction failure due to an increase in contact resistance occurs.

  Examples of variables to be adjusted in the active area will be described with reference to FIGS. FIG. 33 shows an example of an adjustment variable for the gate width w1, and the width mw1 is adjusted using the genetic algorithm technique described above. FIG. 34 shows an example of adjustment variables for the contact-diffusion interlayer alignment margins d1 and d2. The end of the diffusion layer is deformed into a hammerhead shape having a width h1 and a length h2, and is adjusted using the genetic algorithm method described above. . FIG. 35 is an example of avoiding a resolution failure (pattern connection failure) between adjacent cells, and the amount of receding at the tip of the active region 1004 is a variable i1. FIG. 36 shows an example of avoiding failure of the gate wiring on the diffusion layer. The length i3 and the width i2 of the receding region of the portion facing the gate wiring 1005 are variables. These variables are adjusted using the genetic algorithm technique described above.

[Gate layer]
The gate length 11 shown in FIG. 37, the resolution failure (pattern connection failure) avoidance margin s4 between adjacent cells, the gate wiring run-up failure avoidance margin s3 to the diffusion layer, and the protrusion amount p1 from the active region are re-OPC adjusted. It is a part. When the gate length 11 is not within the accuracy of the standard, the threshold voltage control of the transistor does not remain and the transistor characteristics vary greatly, and the circuit operation becomes unstable.

  Examples of variables to be adjusted for the gate and the gate wiring pattern will be described with reference to FIGS. 38A and 38B are actual examples of the adjustment variable of the gate length l1. Since the gate length is the dimension that most sensitively affects the transistor characteristics, particularly high dimensional accuracy is required. Usually, since a pad for establishing electrical connection with the wiring layer is formed in a part of the gate wiring, the transfer pattern is deformed by the influence of the diffracted light from the part. In order to prevent the deformation at least on the active region, a complicated OPC as shown by 1005a in FIG. Here, first, OPC is applied so that a desired dimensional accuracy can be obtained in the case of a single cell. Thereafter, referring to another cell pattern arranged on the outer periphery, as shown in FIG. 38 (b), the above-described genetic algorithm method is used with the line width ml1 as a variable while maintaining the outer shape of the OPC. Adjusted.

  FIG. 39 is an example of avoiding a resolution failure (pattern connection failure) between adjacent cells. The tip retraction amount mh1 of the gate wiring pattern 1005a subjected to OPC in the case of a cell alone is used as a variable. FIG. 40 is an example of avoiding the failure of the gate wiring to the diffusion layer. In this case, the variable is the width i4 and the depth i5 of the receding portion of the gate wiring facing the diffusion layer region (active region) 1004.

  FIGS. 41A to 41C are examples of protrusion correction from the active region. The design layout is a rectangular layout as shown in FIG. 41 (a). However, when pattern transfer is actually performed, the pattern ends are as shown in FIG. 41 (b) due to effects such as exposure light diffraction and resist acid diffusion. It becomes a round shape. When this rounded portion is applied to the active region, the transistor characteristics deteriorate due to a phenomenon such as punch-through. Therefore, a certain amount of protrusion must be ensured. As shown in FIG. 41 (c), the variable in this case is a hammer head having a width h3 and a length h4 at the gate end. These variables were adjusted using the genetic algorithm approach described above.

[Contact layer]
FIG. 42 shows a layout example of the contact layer. Patterns for correcting OPC under the influence of external cells are patterns related to the interaction areas 1009a to 1009e from the external cell patterns 1008a to 1008e, and are indicated by reference numerals 1006a to 1006e in the drawing. The radius of these interaction regions 1009a to 1009e is 1.62λ / NA, although it depends on the acid diffusion constant, standard dimensional accuracy, etc. of the resist. As shown in FIG. 43, the variable of the pattern 1006f subjected to the re-OPC is a height h5 and a width h6, and the center position 1020 is also used as a variable to perform positional deviation correction. These variables were adjusted using the genetic algorithm approach described above.

  In addition to the genetic algorithm method, the various variables in the above-described Study Example 4 include the blind search method or the stochastic search method such as evolution strategy, genetic programming, insect search, EDA, hill-climbing method, iteration, etc. It can also be adjusted by a deterministic search method including the golden section method, the Powell method, and the like.

(Examination example 5)
In the examination example 4, the optimum data structure is shown when the cell is handled by the EDA tool. FIG. 52 is a schematic diagram showing a data structure of a cell designed based on Study Example 4. The data structure of the cell is composed of four elements: a design pattern shown in FIG. 5A, an OPC pattern shown in FIG. 5B, an adjustable area (first area), and an evaluation point.

  The design pattern has the same data structure as that of the conventional standard cell. Therefore, compatibility with existing EDA tools can be easily maintained. The OPC graphic pattern is generated using the method described in Study Example 1.

  The adjustable region (first region) is synonymous with the peripheral region described in Study Example 4. Hereinafter, a part other than the adjustable area in the cell is referred to as a “fixed area”. The adjustable area is used to indicate that the OPC figure included therein is an adjustment target. By making the determination in the adjustable area, it is not necessary to classify all OPC figures included in the cell as being individually adjusted, so that the data structure is simplified and the cell design can be facilitated.

  The evaluation point, which is the last element, is arranged at a position where an error should be calculated by comparing the dimension of the exposure pattern obtained by the optical simulation with the dimension of the design pattern. The error information measured at the evaluation point is used in the evaluation of the chromosome in the genetic algorithm as the evaluation function described in the examination example 1. The same applies not only to genetic algorithms but also to stochastic search methods including annealing, insect type search, EDA, etc., and deterministic search methods including hill-climbing method, iterative golden section method, Powell method, etc. It is obvious that you can use it.

  The methods described in Japanese Patent Application Laid-Open No. 2006-058413 (Patent Document 6) and Japanese Patent Application Laid-Open No. 2005-156606 (Patent Document 7) are highly likely to cause a short circuit or an open circuit in an actual lithography process. Dangerous parts are obtained by optical simulation of the entire chip, and measurement points are arranged around the dangerous parts, or only OPC figures are adjusted in detail by simulating only around the dangerous parts. Therefore, it takes a lot of calculation time. On the other hand, in the present embodiment, it is possible to detect a dangerous spot easily and at high speed by simulation in a cell unit, and to place an evaluation point there, so that the dangerous spot is effectively prevented without degrading the detection accuracy. Can know in advance. As a result, it is no longer necessary to simulate the entire chip to find the dangerous part, so the OPC processing time can be greatly reduced.

(Examination example 6)
The cell having the structure based on the examination example 5 is arranged, and the mask pattern adjusted by the OPC according to the examination example 4 shows that the OPE can be corrected by local calculation even if a part of the circuit is corrected. .

  First, as shown in FIG. 45, four types of cells (cell1 to cell4) are arranged to create a pre-correction pattern (pattern A). At this time, the cells (cell1 to cell4) constituting the pattern A each have an adjustable region (shaded portion in FIG. 45) having a width of 1.62λ / NA. The OPC figure shape in the adjustable area is adjusted by using. There are 107 evaluation points in the pattern A, and each evaluation point is set at a location where the line width of the exposure pattern or the dimension of the tip of the exposure pattern is evaluated.

  When evaluation areas are set like A1 to A8 and F1 to F4 in FIG. 46, and the maximum value, minimum value, and average value of line width variation in each evaluation area are indicated by a ratio (%), FIG. 47 is obtained. Note that the line width variation is expressed by an error indicating how much the exposure pattern varies with respect to the design pattern width. FIG. 47 shows that the error of all evaluation points is within 3%.

  Next, cell 4 of pattern A is replaced with cell 5 as shown in FIG. Note that 109 evaluation points of pattern B are set and distributed in the evaluation region shown in FIG. FIG. 50 shows the measurement results of the line width variation generated by changing the cell for each evaluation region. From this, it can be seen that the influence of the optical proximity effect generated by the circuit correction is large only in the evaluation area A5 and can be almost ignored in the other areas.

Therefore, only the OPC graphics included in the adjustable area and those included in the evaluation area A5 were adjusted by the genetic algorithm described above. In FIG. 51, the measurement result of the line | wire width fluctuation | variation in the pattern B after adjustment is shown. From this result, it can be seen that the maximum line width variation of 12.33% that occurred before the adjustment is suppressed within 3%. Furthermore, it can also be confirmed that the adjustment of the evaluation area A5 does not affect other areas.
Thus, it can be seen that by using the method of the present invention, OPC can be executed with local correction even if a part of the circuit is corrected after layout.

(Embodiment)
The inventor has proposed an adaptive OPC technique as a new OPC technique in the study example.

  The adaptive OPC technology lays out an adjustable OPCed cell (hereinafter referred to as an adjustable OPCed cell) having an adjustable area and a fixed area to which OPC is applied in advance, and the adjustable area according to the OPE from the periphery. Is a method of optimizing and adjusting.

That is, the adaptive OPC technology has the following two basic concepts.
The first is an adjustable OPCed cell. This is a cell to which OPC is applied in advance, and has an adjustable area where the OPC graphic can be adjusted and a fixed area where the OPC graphic is fixed. The adjustable area is an area that is located in the periphery of the cell and includes an adjustable graphic. Thereby, OPE due to the influence of adjacent cells can be corrected. On the other hand, the fixed area is located in the center of the cell where the influence of the OPE due to the adjacent cells is small and the OPC figure is fixed, and therefore it is not necessary to recalculate the OPC figure after layout.

The second is optimization adjustment of the OPC figure after cell layout. After the layout is performed using the adjustable OPCed cell, the OPC figure in the adjustable area is adjusted by the optimization method.
According to such an adaptive OPC technique, since the OPC calculation area can be reduced, the OPC processing time can be greatly shortened.

  FIG. 52 (b) shows an adjustable OPCed cell. The adjustable OPCed cell is manufactured by applying OPC to the design pattern of FIG. 52A and then defining the periphery of the cell as an adjustable region (first region) and the center of the cell as a fixed region. The OPC figure in the adjustable area is called an adjustable figure, and the OPC figure in the fixed area is called a fixed figure. The hatched portion in FIG. 52B represents an adjustable region, and the white portion represents a fixed region.

  Note that the evaluation points are set in places where high-precision OPC is required, such as contact portions and wiring portions on the diffusion layer, on the design pattern. At the evaluation point, in order to verify the effect of the OPC graphic, the deviation ratio between the projected image and the design pattern by the optical simulation is measured as an error. In the adaptive OPC technique, the adjustable figure portion is adjusted by an optimization method so that this error is minimized.

  As described above, when the adjustable OPCed cell is adjusted after layout, the adaptive OPC technology can be adjusted without degrading the adjustment accuracy even if the influence range considered in the adjustment is limited to adjacent cells. Is a point. Since the calculation time of the optical simulation for verifying the adjustment effect of the OPC figure increases in proportion to the square of the area to be calculated, if the calculation area can be made as small as possible, the calculation time required for the verification can be suppressed. it can. Therefore, when the adaptive OPC technique is applied to a large layout pattern (mask pattern) such as an LSI chip, adjustment of each laid-out cell can be performed by optimization adjustment limited to a small area adjacent to those cells. If possible, the characteristics can be utilized more effectively, and further reduction of the OPC processing time can be expected without degrading the adjustment accuracy.

  Therefore, in this embodiment, a speed-up method is proposed in which regions of a layout pattern calculated by optical simulation are divided and each region is processed in parallel. In this method, the simulation area per CPU is obtained by dividing the area based on the adjustable OPCed cell of the adaptive OPC technology and processing the OPC optimization in parallel by different CPUs (Central Processing Units). Thus, the number of OPC graphics to be optimized can be reduced, and the time required for the optimization can be reduced. For this reason, it becomes possible to make effective use of the characteristics of the adaptive OPC technology regardless of the scale of the layout pattern.

  According to the present embodiment, as will be described in the experimental results (examples) described later, it is possible to realize about twice as high speed as a typical master-slave model of parallel processing, and within 3% OPC accuracy could be obtained. In other words, the adaptive OPC technique proposed by the present inventor can not only reduce the OPC calculation area, but can also increase the speed with higher accuracy by performing parallel processing by area division.

  Next, specific examples of the configuration of the divided areas generated by dividing the layout pattern (mask pattern) will be described with reference to FIGS.

  FIG. 53 shows an example of a layout pattern before division, and illustrates four types of adjustable OPCed cells cellA (cellA1 to cellA4). Here, a case where four types of adjustable OPCed cells cellA (cellA1 to cellA4) are arranged in a matrix (2 rows and 3 columns) and arranged in a regular manner is illustrated.

  Each adjustable OPCed cell cellA is formed in, for example, a planar rectangular shape, and a plurality of design patterns LP are arranged therein. This design pattern LP is a pattern for forming an integrated circuit pattern, and has the same data structure as that of a conventional standard cell. Therefore, compatibility with existing EDA tools can be easily maintained. Reference sign CL indicates a cell outer peripheral line (cell boundary) indicating the outer periphery of the cell cell. Here, the adjustable area is omitted. Further, the adjustable OPCed cell cellA referred to in the present embodiment is the same as the cell cell adopting the adaptive OPC technology in the examination example.

  FIG. 54 is a layout plan view showing the layout area of FIG. 53 in which the divided areas SA (SA1, SA2) are arranged. FIGS. 55 and 56 are respectively the upper left and upper center divided areas SA1 of the layout pattern of FIG. , SA2 are extracted and shown in a plan view, and FIG. 57 is an explanatory diagram of divided areas.

  Each divided area SA (SA1, SA2) is formed in a planar rectangular shape larger than the adjustable OPCed cell cellA. Each divided area SA (SA1, SA2) has information on the adjustable OPCed cell cellA at the center and information on a reference area (Reference area: second area) RA on the outer periphery of the adjustable OPCed cell cellA. In FIGS. 55 and 56, the reference area RA is hatched with an upper right oblique line for easy viewing.

  As described above, the divided area SA is generated based on the adjustable OPCed cell cellA. For this reason, in this Embodiment, adjustable OPCed cell cellA is not divided | segmented by a division | segmentation process. That is, the design pattern LP in the adjustable OPCed cell cellA is not divided. Therefore, when the reduction projection exposure process is performed using the mask manufactured by the mask pattern design method of the present embodiment, the pattern transfer accuracy can be improved.

  The reference area RA is an area for considering the influence of OPE from other cells (other adjustable OPCed cells) cells adjacent to the adjustable OPCed cell cellA inside. In this reference area RA, a part of the design pattern LP of another adjacent cell is arranged. By including such a reference area RA, an optimal OPC figure can be formed in the adjustable OPCed cell cellA inside.

In the example of the divided area SA of FIGS. 54 to 56, the reference area RA is arranged on the left and right and the lower side of the adjustable OPCed cell cellA and is not arranged on the upper side. This is because other cells (other adjustable OPCed cells) cells are arranged on the left and right and lower sides of the adjustable OPCed cell cellA, but other cells (other adjustable OPCed cells) cells are arranged on the upper side. Because there is no.
However, as shown in the lower part of FIG. 57, when there is another cell (adjustable OPCed cell cellA) around the adjustable OPCed cell cellA, the divided region SA includes the reference region so as to surround the entire periphery of the adjustable OPCed cell cellA. RA is arranged.

  The width W1 of the reference area RA is all equal on the outer periphery of the adjustable OPCed cell cellA. For example, assuming that the wavelength of exposure light used for pattern exposure is λ and the numerical aperture of the lens of the exposure device is NA, 1.62λ / NA or 1 .12λ / NA, which is equal to the width of the adjustable region. That is, the reference area RA of a certain divided area SA (SA1) is also a part of the adjustable area of the adjustable OPCed cell cellA of another divided area SA (SA2) adjacent thereto. Thus, by making the width of the reference area RA equal to the width of the adjustable area, it is possible to easily generate the reference area RA when the divided area SA is generated.

  Further, the OPC graphic in the reference area RA overlaps with the OPC graphic at the center of the adjacent divided area SA, and is updated from the adjacent cell by updating in accordance with the change of the graphic to be adjusted. It is possible to calculate the OPE accurately.

  58 and 59 show how the reference area RA is updated. Here, in order to make the drawing easy to see, the state of updating is shown separately in FIG. 58 and FIG. 59, but when performing parallel processing as will be described later, the updating is performed simultaneously.

  For example, the reference area RA of the left divided area SA1 in FIG. 58 includes the adjustable figure of the adjustable OPCed cell cellA in the right divided area SA2 in FIG. 58. In the initial adjustment state, both figures have the same shape. I am doing. When the adjustment is started, the figure of the reference area RA of the divided area SA1 remains the shape of the figure of the adjustable OPCed cell cellA in the divided area SA2 before the adjustment, but the adjustable OPCed in the left divided area SA2 in FIG. The adjustable figure in the cell cellA is optimized and changed by adjustment, so that there is a difference between the overlapping figures of the left and right divided areas SA1 and SA2 in FIG.

  In the present embodiment, in order to eliminate this difference, the graphics in the reference area RA are mutually updated between the divided areas SA1 and SA2, so that the influence of OPE from the adjacent cell (adjustable OPCed cell) cell is sufficient. Accuracy can be secured.

Next, an example of the OPC processing procedure of the present embodiment will be described with reference to FIG.
First, a cell library used in the LSI chip to be developed is designed (St1). Subsequently, an OPC process is performed on each cell library in advance, and an adjustable OPCed cell is produced by making the OPC figure in the adjustable area (interference area) in the peripheral part an adjustable figure (St2). By completing the OPC for each cell, the OPC process on the entire chip surface after the placement becomes unnecessary. Therefore, the OPC processing time can be greatly shortened.

Next, in the mask pattern design apparatus, an adjustable OPCed cell is arranged and a layout pattern is created (input) according to the circuit design (St3).
Subsequently, in the mask pattern design apparatus, as shown in FIGS. 54 to 59, the layout pattern is divided into regions based on adjustable OPCed cells, thereby generating divided regions SA. The divided area SA includes the figure of the adjustable OPCed cell cellA arranged at the center thereof and the figure of the reference area RA arranged at the periphery thereof. The reference area RA of a certain divided area SA is an area that overlaps with the adjustable area of another adjustable OPCed cell cellA adjacent to the adjustable OPCed cell cellA of the divided area SA (St4).

  Next, in the mask pattern design apparatus, each divided area SA is distributed to each CPU (process) of the parallel computer, and the adjustment adjustment of the adjustable figure is performed in parallel for each divided area SA (St5A). Thus, the processing speed can be improved by reducing the optical simulation area. Further, the processing speed can be improved by reducing the number of OPC graphics to be optimized. Furthermore, the processing speed can be further improved by processing the plurality of divided regions in parallel.

  In the optimization adjustment, by including the reference area RA, an optimal OPC figure can be formed in the adjustable OPCed cell cellA inside thereof. In the optimization adjustment, the pattern of the reference area RA is not optimized, but the graphic of the reference area RA is updated between adjacent divided areas SA (St5B). That is, the graphic of the reference area RA before adjustment is updated to reflect the optimization result of adjacent cells (adjustable OPCed cells). Thereby, since the OPE from the adjacent cell can be accurately calculated, the OPC correction accuracy can be improved.

  Subsequently, after each optimization adjustment is completed in each divided area SA, the optimized divided areas SA are integrated in the mask pattern design apparatus to produce a layout pattern (St6).

Next, the parallel optimization adjustment algorithm used in this embodiment will be described.
In the present embodiment, a genetic algorithm (hereinafter referred to as GA) that can search a plurality of solution candidates in parallel is one of the probabilistic search methods for adjusting an adjustable figure of a region-divided pattern. Abbreviated). For the GA generation alternation model, an MGG (Minimal Generation Gap) model with good balance in maintaining diversity and avoiding local solutions was used. In addition, normal random mutation was used for GA genetic manipulation.

  FIG. 61 shows a flowchart of the parallel optimization adjustment algorithm using GA in the present embodiment. As an overall flow, first, a divided area is assigned to each process performing parallel processing (ASt1).

  Subsequently, in each process (divided region), first, the shape and size of the adjustable figure is encoded as a chromosome to be handled as an adjustment variable of the optimization method, and N initial populations of chromosomes are generated (ASt2). ).

  Next, fitness evaluation of each generated initial individual is performed. In the fitness evaluation, a projection image of a pattern including an OPC figure generated from the parameters of each individual is calculated by optical simulation, and the fitness is evaluated from the difference from the design pattern (Ast 3).

  Thereafter, two parent individuals are selected from the group (ASt4), and two child individuals are generated by genetic manipulation by mutation (σN (0,1)) (ASt5). After this child individual is evaluated for fitness (ASt6), compared with the two original parent individuals, the child individual is hesitant and replaced according to the fitness (ASt7).

In the present embodiment, as an operation in the middle of the search, the parameter of the reference area is updated between adjacent processes for each L generation (ASt8, ASt9). Based on the parameters of the best individual of each process at that time, the numerical value of the reference area of the adjacent process is updated and reflected in the subsequent optical simulation of fitness evaluation.
This optimization adjustment is finished when the number of generational changes exceeds G times (ASt10), and the OPC figure by the parameter of the best individual in each process is integrated into the layout pattern (ASt11).
By the above procedure, the adjustable figure is adjusted so that the projected image by the optical simulation approaches the design pattern.

  Next, a description will be given of a method for coding an adjustable figure into a chromosome and calculating fitness.

In coding, the variable that determines the shape of the adjustable figure is represented by a one-dimensional array composed of the same number of adjustment points. FIG. 62 shows, as an example of coding, the adjustment location of the adjustable figure and the chromosome gene sequence in the optimization corresponding to this adjustment location.
The chromosome is composed of the same number of genes as the adjustment location, and each gene is a polygon side (a, b, c, d in FIG. 62) or a line width of the polygon (FIG. 62) as the adjustment location. e, f, g, h), which are expressed as real values.

Calculation of fitness used in optimization is performed in the following procedure. First, the projection image of the mask pattern determined by the chromosome is calculated using an optical simulator. Based on this result, the ratio of deviation between the projected image dimension P and the design pattern dimension O is calculated as an error F at the evaluation point by the following equation.
Fi = | Oi−Pi | / Oi Formula (1)
Here, i represents an evaluation location. As described above, errors at all evaluation points are calculated, and the fitness is calculated by the following equation using the maximum error max {Fi} among them.
Fitness = 1 / max {Fi} Equation (2)
A maximum fitness value (smaller error) means that an optimal adjustable figure is generated.

  Since the projection image evaluation method differs between the line width and the tip, this will be described with reference to FIG. When the line width is evaluated, the distance between the two evaluation points E1a and E1b is defined as the dimension O1 of the design pattern, and the width of the projected image on the line connecting the evaluation point E1a and the evaluation point E1b is defined as the projected image dimension P1. Calculate F1 using equation (2).

  When evaluating the tip of the projected image, a reference point R is provided on the perpendicular of the line segment including the evaluation point E2 outside the design pattern, and the distance from this point to the evaluation point E2 is defined as the dimension O2 of the design pattern, Using the distance to the tip of the projected image as the dimension P2 of the projected image, F2 is calculated by the above equation (2).

According to this embodiment, the following effects can be obtained.
(1) By dividing the area as described above, it is possible to divide the area of the layout pattern for performing the simulation (evaluation of the exposure pattern), and to shorten the calculation time of the projected image.
(2) By dividing the region as described above, the adjustment variable per one divided region can be reduced, so that the convergence to the optimal solution can be improved. Furthermore, since the divided regions can be simultaneously optimized by parallel processing, the overall adjustment time can be shortened.
(3) According to the above (1) and (2), the manufacturing TAT of the semiconductor device manufactured using the mask manufactured by the mask pattern design method of the present embodiment can be shortened. As a result, the manufacturing cost of the semiconductor device can be reduced.
(4) By giving a reference area including an OPC graphic of an adjacent cell to the periphery of the divided area, and changing the graphic of the reference area after the division according to the optimization of the original OPC graphic, Since OPE from adjacent cells can be accurately taken into account, highly accurate adjustments can be made.

(5) Adjustable OPCed cells are basically used for generation of divided areas so that the divided areas are not divided. Thereby, the transfer accuracy of the pattern transferred to the resist film using the mask manufactured using the mask pattern design method manufactured in this embodiment can be improved.
(6) According to the above (4) and (5), since the fidelity of pattern transfer can be improved, the yield and reliability of the semiconductor device can be improved.
(7) By the above (1) to (6), it is possible to suppress an increase in the amount of data and manufacturing time when designing a mask pattern accompanying the miniaturization of the pattern of the semiconductor device. can do.

  The design pattern data (mask pattern data) generation method, OPC figure pattern generation method, reduced projection exposure method using a mask, semiconductor device manufacturing method, and the like are the same as those described in the above-described study example. Is omitted.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiment, the case where the adaptive OPC technique is adopted and the adjustable OPCed cell is used has been described. However, the present invention is not limited to this, and the present invention can be applied even when a normal cell is used. That is, in the above-described embodiment, the OPC graphic of the adjustable area of the adjustable OPCed cell is adjusted in the OPC optimization process. However, the present invention is not limited to this, and the OPC graphic of the entire area in the cell is adjusted. You may do it.

  For example, in the present embodiment, the case where the created mask is applied to a process of reducing and exposing a desired pattern in a semiconductor device has been described. However, the present invention is not limited to this, and for example, a liquid crystal device, a micromachine, a magnetic head, or the like The desired pattern can be applied to the reduction projection exposure process.

  Next, a simulation experiment conducted for verifying the effectiveness of the method of the embodiment will be described.

  In the experiment, optimization adjustment was performed by parallel processing divided into regions using the method of the above embodiment, using a test pattern in which six cells are arranged. As a comparative method for verifying the effectiveness, optimization adjustment was performed with the same test pattern using a master-slave model, which is a typical parallel process of GA adjustment. In the following, first, the simulation experimental conditions and preparation for the experiment such as layout pattern preparation are described, and then the simulation experiment result is shown.

Experimental conditions For the optical simulation, an optical simulator produced based on partially coherent theory was used. The performance of the parallel computer used in the simulation experiment is as follows: CPU: Xeon processor 3.4 GHz, memory: 4 GB, operating system (OS): SUSE LINUX Enterprise Server 9, Compiler: gcc3.3, communication library: mpic-1.2. 6 buildby gcc3.3, number of parallel processors: 6. In the optical simulation, the wavelength = 193 nm and NA = 0.7 (k1 = 0.32) were assumed as the optical conditions of the 90 nm library circuit which is currently mainstream. In the experiment, since the circuit pattern of the 130 nm library was used, in order to make the k1 value equal, the simulation was performed with the wavelength = 193 nm and NA = 0.48. Other optical conditions were set as annular illumination (σ (outer diameter / inner diameter) = 0.85 / 0.55) and phase shift mask (transmittance 6%).

Here, in order to verify the effectiveness of the method of the embodiment, an experiment was performed using the following three methods.
(1) Conventional adaptive OPC technology using one CPU (2) Master-slave model using six CPUs (excluding the master) (3) Method of the above embodiment using six CPUs

  FIG. 64 shows comparison conditions for the above experimental methods. By comparing these conditions, it is possible to verify the advantages of the method of the embodiment. The parameters used in the optimization method GA common to these methods were GA individual number N = 50, generation number G = 500, and normal random mutation parameter σ = 1 nm. Note that the update interval of the reference area in the method of the embodiment is L = 100.

Preparation for Experiment In preparation for the experiment, four adjustable OPCed cells of cell cellA1 to cellcellA4 were fabricated using a 130 nm library developed by Semiconductor Research Center for Semiconductor Science (STARC). This is a cell for producing a test pattern used for a verification experiment. In each cell, the size was set to 2.4 × 3.6 μm ² , the adjustable region was set to a region 446.65 nm from the end of the cell, and the rest was set to a fixed region. The width of this region is a value calculated considering the range up to the third order diffraction image (third order (3rd order in FIG. 65)) of the diffraction image intensity distribution shown in FIG. 65 as the influence range of OPE. The adjustment figure of each adjustable OPCed cell is adjusted in advance in the state of the cell alone, and the correction accuracy is determined by the International Technology Roadmap for Semiconductor (ITRS). The accuracy was 3%.

  FIG. 66 shows a test pattern used in an experiment, which was prepared by randomly arranging four adjustable OPCed cells of cell cellA1 to cellcellA4. In this test pattern, the maximum error value deteriorated to 5.51% due to the arrangement. This shows that even if each cell is adjusted to within 3%, the error is increased due to OPE from the adjacent cells arranged. In this experiment, an experiment for verifying the effectiveness of the method of the above-described embodiment was performed with the state of the test pattern having the maximum error value of 5.51% as the initial state.

Verification Experiment Using the Method of the Embodiment FIG. 67 shows the adjustment results of the method of the embodiment and the comparison 2 method. It can be seen that the master slave in parallel processing by the same six CPUs and the method of the above embodiment have the earlier adjustment time and less error after adjustment. When the adjustment time of the conventional method is used as a reference, the master-slave can realize a speed increase of about 6 times as theoretically, and the method of the above embodiment can achieve a speed increase of about 11.4 times. Comparing this experimental result with the experimental conditions shown in FIG. 64, it can be seen that the speed can be effectively increased by reducing the calculation area of the layout pattern rather than reducing the number of evaluations per CPU.

  FIG. 68 shows the optical simulation time required for one evaluation. It can be seen that the optical simulation time is shortened by area division. Therefore, it has been found that the technique of the above-described embodiment has made it possible to shorten the optical simulation time by dividing the region and to increase the processing time of the OPC calculation. In addition, it can be seen that the adjustment result by the method of the above embodiment has a smaller error than the other two methods and can be generated with an accurate OPC pattern that satisfies the required accuracy of 3% defined by ITRS. That is, in the method of the above embodiment, the OPC correction can be performed with higher accuracy in addition to the higher speed.

  FIG. 69 shows the convergence of the adjustment experiment using the method (solid line) and master slave (broken line) of the above embodiment. The horizontal axis of the graph indicates the number of generations, and the vertical axis indicates the maximum error. While the method of the embodiment converges efficiently, the master slave converges during the optimization. In the master / slave, since there are many adjustment figures for one CPU, the probability of staying in the local solution is high, and it seems that the optimal solution could not be reached in a short time. On the other hand, the method of the above embodiment has realized the speed of the optimization adjustment by improving the convergence to the optimal solution because the number of adjustment figures per CPU is small. .

  As described above, the region division described in the above embodiment makes it possible to effectively utilize the features of the adaptive OPC technique regardless of the scale of the layout pattern. The conventional adaptive OPC technology is difficult to apply to a large layout pattern. For example, in a logic part in a certain 2 mm square LSI chip, the number of used cells is 266,953, and it seems impossible to apply without area division and parallel processing by the method of the above embodiment. If there are 16 adjustment figures in one cell as in the cell used in the verification experiment, the number of adjustment figures in the LSI chip is 42.70 million, and it is almost impossible to make simultaneous adjustments. . On the other hand, in the method of the above embodiment, the number of figures to be adjusted at the same time is 16 by performing area division, so that optimization adjustment can be performed.

  The calculation was performed for the calculation time when the method of the above embodiment was applied to the logic part. Since the parallel processing used in the OPC calculation may be 1000 or more, in the trial calculation, 1000 parallel processing was assumed. From the verification experiment here, when the time for the error to reach 3% by the method of the above embodiment is calculated as 3 hours, it is realistic that 266,935 cells × 3 hours ÷ 1000 units = about 800 hours = about 33 days. It was a great time. Instead of the optical simulation used here, this trial calculation time becomes faster by using a commercially available high-speed optical simulation.

  As described above, by introducing the technique of the above-described embodiment, the adaptive OPC technique functions as a practical OPC generation technique and can be applied to an actual large-scale LSI chip. In addition, the method of the above embodiment does not require special know-how and trial and error, satisfies the accuracy required by the most advanced process defined by ITRS, and functions sufficiently as an OPC technology after the 90 nm generation.

  The present invention can be used in a mask pattern design method using a cell library pattern subjected to optical proximity effect correction (OPC) processing.

It is a top view which shows the mask pattern used for the gate of SRAM which applied the examination example in order to verify the effectiveness of the examination example. It is a top view which shows the mask pattern used for verification of the examination example. It is a top view which shows the mask pattern used for verification of the examination example. It is a top view which shows the mask pattern used for verification of the examination example. It is a top view which shows the mask pattern used for verification of the examination example. It is a top view which shows the mask pattern used for verification of this invention. It is a top view which shows the mask pattern used for verification of the examination example. It is a top view which shows the mask pattern used for verification of the examination example. It is a top view which shows the mask pattern used for verification of the examination example. It is a top view which shows the mask pattern used for verification of the examination example. It is a top view which shows the mask pattern used for verification of the examination example. FIG. 2 is a partially enlarged plan view of the mask pattern shown in FIG. 1. (A) is a top view which shows the transfer pattern of the mask pattern shown in FIG. 2, (b) is a top view which shows the transfer pattern of the mask pattern shown in FIG. It is a top view which shows the mask pattern used for verification of the examination example. It is a top view which shows the mask pattern used for verification of the examination example. It is the elements on larger scale of the transfer pattern of the mask pattern shown in FIG. It is a flowchart explaining the calculation procedure of a genetic algorithm. It is a figure which shows an example of the expression of the chromosome used for the OPC processing method of the examination example. (A) is a figure which shows the symbol of a NAND gate, (b) is a circuit diagram of a NAND gate, (c) is a top view which shows the pattern layout of a NAND gate. FIG. 20 is a plan view showing a unit logic cell and a broken line defining a cross section in the NAND gate pattern layout shown in FIG. (A)-(f) is a figure which shows the mask pattern used when forming the unit logic cell part shown in FIG. (A)-(e) is sectional drawing which shows to an element isolation process in order of a process. (A)-(e) is sectional drawing showing a channel formation to process order. (A)-(e) is sectional drawing which shows to formation of a part of wiring in order of a process. It is a block diagram which shows the pattern of the mask shown in FIG.21 (d). It is a figure which shows the example which expressed the difference dimension from the design target in FIG. 25 by gene. It is a figure which shows the example which performed cell grouping based on the relative position. It is a figure which shows the measurement location of the dimension for obtaining the fitness of a chromosome. It is a figure which shows the difference image of a design pattern and a resist pattern. It is a figure which shows the manufacturing process flow of a semiconductor device. It is a top view which shows the cell of the cell library in which the OPC process by the single cell was performed. FIG. 32 is an enlarged view of a main part of the cell shown in FIG. 31. It is a figure which shows the example of the adjustment variable of gate width. It is a figure which shows the actual example of the adjustment variable of the alignment margin between contact-diffusion layers. It is a figure which shows the actual example of the resolution failure avoidance between adjacent cells. It is a figure which shows the example of the gate wiring boarding failure avoidance to a diffused layer. It is a figure which shows the re-OPC adjustment site | part of the gate length, the resolution defect (pattern connection defect) avoidance margin between adjacent cells, the gate wiring board imperfection avoidance margin to a diffused layer, and the protrusion amount from an active region. (A) And (b) is a figure which shows the example of the adjustment variable of gate length. It is a figure which shows the actual example of the resolution failure avoidance between adjacent cells. It is a figure which shows the example of the gate wiring boarding failure avoidance to a diffused layer. (A)-(c) is a figure which shows the example of the protrusion correction | amendment from an active area | region. It is a figure which shows the example of a layout of a contact layer. It is a figure which shows the example of the adjustment variable of a contact pattern. It is a graph which shows the relationship between the intensity | strength of a diffraction image, and 2 (pi) * (rho) * NA / (lambda). It is a figure which shows the adjustable area | region of four types of cells in which the OPC figure shape was adjusted. It is a figure which shows the evaluation area | region of the cell shown in FIG. It is a figure which shows the maximum value of line width fluctuation | variation in the evaluation area | region shown in FIG. 46, the minimum value, and an average value by a ratio. It is a figure which shows the adjustable area | region when replacing a part of cell shown in FIG. 45 with another cell. It is a figure which shows the evaluation area | region of the cell shown in FIG. It is a figure which shows the measurement result of the line | wire width fluctuation | variation which generate | occur | produced by having changed the cell for every evaluation area | region. It is a figure which shows the measurement result of the line | wire width fluctuation | variation after adjusting with a genetic algorithm for every evaluation area | region. (A), (b) is a schematic diagram which shows the data structure of a cell. FIG. 10 is a layout plan view before dividing a mask pattern in a mask design process which is a manufacturing process of a semiconductor device according to an embodiment of the present invention; FIG. 54 is a layout plan view showing a layout area shown in FIG. 53 in which divided areas are arranged. FIG. 57 is a plan view showing the upper left divided region of the layout pattern of FIG. 54. FIG. FIG. 55 is a plan view showing an upper center divided region extracted from the layout pattern of FIG. 54; It is a top view of the division area in the mask design process which is one embodiment of the present invention. FIG. 57 is a plan view showing how a reference area is updated in the divided areas shown in FIGS. 55 and 56. FIG. 57 is a plan view showing how a reference area is updated in the divided areas shown in FIGS. 55 and 56. It is explanatory drawing which showed an example of the process sequence of the optical proximity effect correction | amendment in the mask pattern design method which is one embodiment of this invention. It is a flowchart figure of the parallel optimization adjustment algorithm which used the genetic algorithm in adjustment of the adjustable figure of the division area in the mask pattern design method which is one embodiment of this invention. It is explanatory drawing which showed the adjustment | control location of the adjustable figure and the gene sequence of the chromosome in the optimization corresponding to this adjustment location as an example of encoding. It is explanatory drawing of the evaluation method of a projected image. It is a figure which shows the comparison conditions of each experimental method of the conventional adaptive optical proximity effect correction technique, a master slave model, and embodiment. It is a graph which shows a diffraction image intensity distribution. FIG. 7 is a layout plan view of an experimental test pattern produced by randomly arranging four adjustable opseed cells. It is a figure which shows the adjustment result of each experiment of the conventional adaptive optical proximity effect correction technique, a master slave model, and embodiment. It is the figure which showed the optical simulation time concerning 1 evaluation. It is a graph which shows the mode of convergence of the adjustment experiment by the method (solid line) and master slave (broken line) of embodiment.

Explanation of symbols

81-92 cells 101a-101f light transmitting portions 102a-102f light-shielding portions 110 unit cells 111n n-type semiconductor region 111p p-type semiconductor region 112 polycrystalline silicon film 112A gate electrode 115 insulating film 116 silicon nitride film 117 resist films 117a-117d resist Pattern 118 Groove 119 Insulating film 120 Gate insulating films 121a and 121b Interlayer insulating film 1001 Cell 1002 Width 1003 Cell part boundary region 1004 Active region (diffusion layer region)
1005 Gate and gate wiring 1005a Gate wiring pattern 1006 Conductive holes 1006a to 1006e Pattern 1008a to 1008e Pattern 1009a to 1009e Interaction region 1020 Center position cell, cell1 to cell4 Cell cellA, cellA1 to cellA4 Adjustable OP seed cell LP Design pattern CL Cell perimeter (cell boundary)
SA, SA1, SA2 divided area RA divided area (second area)

Claims (16)

(A) a step of performing proximity effect correction for correcting a shape change that occurs when a mask pattern is exposed to transfer a pattern for each of a plurality of cells included in a cell library;
(B) arranging the plurality of cells subjected to the proximity effect correction to design a mask pattern;
(C) dividing the mask pattern designed in the step (b) to generate a plurality of divided regions;
(D) after the step (c), adjusting the correction amount of the proximity effect correction for each of the plurality of divided regions;
(E) after the step (d), integrating the plurality of divided regions,
Each of the plurality of divided regions in the step (c)
Information on the cell;
An area that extends outward from the cell boundary of the cell and includes information on a partial area of another cell adjacent to the cell;
In the step (d),
(D1) performing optimization adjustment of the whole or a part of the cell in each of the plurality of divided regions;
(D2) A method of designing a mask pattern, comprising: updating information of a partial area of another cell adjacent to the cell in each of the plurality of divided areas.   The mask pattern design method according to claim 1, wherein each of the plurality of divided regions is a region outward from a cell boundary of the cell, and a width of a partial region of another cell adjacent to the cell is: 1. A mask pattern design method, wherein a wavelength of exposure light used for pattern exposure is λ, and a numerical aperture of a lens of an exposure machine is NA, which is 1.62λ / NA.   The mask pattern design method according to claim 1, wherein each of the plurality of divided regions is a region outward from a cell boundary of the cell, and a width of a partial region of another cell adjacent to the cell is: 1. A mask pattern design method, wherein λ is the wavelength of exposure light used for pattern exposure, and NA is the numerical aperture of a lens of an exposure machine, which is 1.12λ / NA. (A) a step of performing proximity effect correction for correcting a shape change that occurs when a mask pattern is exposed to transfer a pattern for each of a plurality of cells included in a cell library;
(B) arranging the plurality of cells subjected to the proximity effect correction to design a mask pattern;
(C) dividing the mask pattern designed in the step (b) to generate a plurality of divided regions;
(D) after the step (c), adjusting the correction amount of the proximity effect correction for each of the plurality of divided regions;
(E) after the step (d), integrating the plurality of divided regions,
Each of the plurality of cell libraries in the step (a)
A first region that is inward from the cell boundary of the cell and may be affected by the shape change from other cells arranged around the cell;
Each of the plurality of divided regions in the step (c)
Information on the cell;
A region extending outward from the cell boundary of the cell, and having information on a second region of a part of another cell adjacent to the cell;
In the step (d),
Performing optimization adjustment of information of the first region;
And a step of updating the information of the second region.   5. The mask pattern design method according to claim 4, wherein a width of the first region is equal to a width of the second region.   5. The mask pattern design method according to claim 4, wherein the width of each of the first region and the second region is 1 when the wavelength of exposure light used for pattern exposure is λ and the numerical aperture of the lens of the exposure machine is NA. A mask pattern design method, characterized in that it is 62 λ / NA.   5. The mask pattern design method according to claim 4, wherein the width of each of the first region and the second region is 1 when the wavelength of exposure light used for pattern exposure is λ and the numerical aperture of the lens of the exposure machine is NA. A mask pattern design method characterized by being 12λ / NA. (A) means for designing a mask pattern by arranging a plurality of cells subjected to proximity effect correction for correcting a shape change that occurs when the mask pattern is exposed to transfer the pattern;
(B) means for dividing the mask pattern to generate a plurality of divided regions;
(C) means for adjusting a correction amount of the proximity effect correction for each of the plurality of divided regions;
(D) integrating the plurality of regions adjusted by the means (c),
Each of the plurality of divided regions is
Information on the cell;
An area that extends outward from the cell boundary of the cell and includes information on a partial area of another cell adjacent to the cell;
The means (c) includes:
(C1) means for performing optimization adjustment of all or a part of the cell in each of the plurality of divided regions;
(C2) A mask pattern design apparatus comprising means for updating information of a partial area of another cell adjacent to the cell in each of the plurality of divided areas. (A) a step of performing proximity effect correction for correcting a shape change that occurs when a mask pattern is exposed to transfer a pattern for each of a plurality of cells included in a cell library;
(B) arranging the plurality of cells subjected to the proximity effect correction to design a mask pattern;
(C) dividing the mask pattern designed in the step (b) to generate a plurality of divided regions;
(D) after the step (c), adjusting the correction amount of the proximity effect correction for each of the plurality of divided regions;
(E) after the step (d), integrating the plurality of divided regions;
(F) after the step (e), exposing the mask pattern to transfer the pattern to a semiconductor wafer,
Each of the plurality of divided regions in the step (c)
Information on the cell;
An area that extends outward from the cell boundary of the cell and includes information on a partial area of another cell adjacent to the cell;
In the step (d),
(D1) performing optimization adjustment of the whole or a part of the cell in each of the plurality of divided regions;
(D2) A method of manufacturing a semiconductor manufacturing apparatus, comprising: updating information of a partial region of another cell adjacent to the cell in each of the plurality of divided regions.   10. The method of manufacturing a semiconductor device according to claim 9, wherein each of the plurality of divided regions is a region extending outward from a cell boundary of the cell, and a width of a partial region of another cell adjacent to the cell is A method of manufacturing a semiconductor device, wherein the wavelength of exposure light used for pattern exposure is λ, and the numerical aperture of the lens of the exposure device is NA, which is 1.62λ / NA.   10. The method of manufacturing a semiconductor device according to claim 9, wherein the pattern is a gate electrode pattern of a field effect transistor.   10. The method of manufacturing a semiconductor device according to claim 9, wherein the pattern is an element isolation pattern.   10. The method of manufacturing a semiconductor device according to claim 9, wherein the pattern is a contact hole pattern connecting conductive layers. (A) a step of performing proximity effect correction for correcting a shape change that occurs when a mask pattern is exposed to transfer a pattern for each of a plurality of cells included in a cell library;
(B) arranging the plurality of cells subjected to the proximity effect correction to design a mask pattern;
(C) dividing the mask pattern designed in the step (b) to generate a plurality of divided regions;
(D) after the step (c), adjusting the correction amount of the proximity effect correction for each of the plurality of divided regions;
(E) after the step (d), integrating the plurality of divided regions;
(F) after the step (e), exposing the mask pattern to transfer the pattern to a semiconductor wafer,
Each of the plurality of cells in the step (a)
A first region that is inward from the cell boundary of the cell and may be affected by the shape change from other cells arranged around the cell;
Each of the plurality of divided regions in the step (c)
Information on the cell;
A region extending outward from the cell boundary of the cell, and having information on a second region of a part of another cell adjacent to the cell;
In the step (d),
Performing optimization adjustment of information of the first region;
And a step of updating the information in the second region.   15. The method of manufacturing a semiconductor device according to claim 14, wherein a width of the first region is equal to a width of the second region.   15. The method of manufacturing a semiconductor device according to claim 14, wherein the width of each of the first region and the second region is set such that the wavelength of exposure light used for pattern exposure is λ and the numerical aperture of the lens of the exposure machine is NA. A method for manufacturing a semiconductor device, wherein 1.62λ / NA.

Images