JP2013073139A - Mask layout division method, mask layout division device and mask layout division program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a mask layout division method and mask layout division device that can prevent a yield drop.SOLUTION: A mask layout division method includes steps of: acquiring cell layout data for each of multiple types of cells; setting multiple candidates for a pattern parting section generated when dividing the cell layout into multiple mask layouts, as multiple parting candidates, and generating cell layout data with the parting candidates corresponding to each of the types of cells; generating full-chip layout data showing a layout of full chips including multiple cells, on the basis of the cell layout data with the parting candidates, and selecting a parting candidate group to be adopted from the parting candidates shown in the data; dividing a layout shown in the full-chip layout data, so as to part the pattern at the selected parting candidate group; and generating division layout data showing a division result.

Description

  The present invention relates to a mask layout dividing method, a mask layout dividing apparatus, and a mask layout dividing program.

  In a manufacturing process of a semiconductor device, a film to be processed (for example, a silicon film) is processed by a lithography process. In the lithography process, a multiple patterning method may be employed. In the multiple patterning method, one layout is divided into a plurality of mask layouts, and multiple exposure is performed using a plurality of masks. By using the multiple patterning method, the processing dimension can be reduced.

  When using the multiple patterning method, how to divide the layout is important. As a related technique, Patent Document 1 (Japanese Unexamined Patent Application Publication No. 2009-13938) discloses a method for performing pattern decomposition of a full chip design. Patent Document 1 discloses that a full chip design is divided into a plurality of individual patches, each patch is individually disassembled and colored and divided, and patch processing is executed in parallel.

  As another related technique, Japanese Patent Application Laid-Open No. 2009-294308 discloses a pattern verification method. In this pattern verification method, a point in which the overlay error of the second pattern with respect to the first pattern is reflected in at least one of the first pattern and the second pattern, and the first pattern after reflecting the overlay error And a point for calculating a relative distance between the second pattern and a point for determining whether or not the relative distance satisfies a criterion.

  As still another related technique, Patent Document 3 (US Patent Publication US2010 / 0115489A1) discloses a method of verifying a lithography process of a double patterning process.

  As another related technique, Patent Document 4 (Japanese Patent Laid-Open No. 2010-175733) discloses a pattern layout creation method. The pattern layout creating method includes generating a graph in which each pattern generated based on a pattern layout diagram is set as a node, and nodes of patterns adjacent to each other at a first distance are connected to each other by an edge; A classification process for classifying each pattern into two types, and a grouping of the patterns into groups of nodes connected by edges, and adjacent patterns of the same type belonging to different groups adjacent by the second distance. A classification correction step of correcting the classification result by inverting the type of the pattern belonging to the same group as one pattern of the pair. The pattern layout diagram is divided based on the classification result corrected by the classification correction step.

  As still another related technique, Patent Document 5 (US Patent Publication US2010 / 0199253A1) discloses a method for designing a double patterning mask.

  On the other hand, a cell library is used when designing a mask layout of a semiconductor device. In the cell library, data indicating the cell layout is stored for each cell for realizing the unit function. When designing a mask layout, an automatic placement and routing tool or the like refers to a cell library and determines the arrangement of a plurality of cells on a full chip so that a desired function can be obtained. Thereby, a mask layout (full chip layout) in a full chip is determined. Relatedly, Patent Document 6 (Japanese Patent Application Laid-Open No. 2011-1244223) discloses a cell library. This cell library is a cell library which is a library of design data for each cell that realizes a unit function, which is used for layout design of a semiconductor integrated circuit. In this cell library, the design data is an attribute value indicating whether the cell has an end, whether or not an adjacent defect is likely to occur through the end, and whether or not a defect is likely to be generated from the adjacent cell. And attribute information in association with each other.

JP 2009-139938 A JP 2009-294308 A US Patent Publication US2010 / 0115489A1 JP 2010-175733 A US Patent Publication US2010 / 0199253A1 JP 2011-124223 A

  By the way, when one layout is divided into a plurality of mask layouts, a pattern included in the layout may be divided. This point will be described below. FIG. 1 is a diagram illustrating an example of a layout to be divided. The layout shown in FIG. 1 includes a plurality of patterns. The plurality of patterns are arranged at intervals of the distance S1 or the distance S2. The distance S1 is smaller than the production limit, and the distance S2 is larger than the production limit. In the following description, attention is paid to the layout of seven patterns arranged in the central portion as the processing target layout. The seven patterns include four patterns having a pattern width of W1 and three patterns having a pattern width of W2. These seven patterns are arranged at an interval of a distance S1. Further, W1 is assumed to be larger than W2.

  FIG. 2 is a conceptual diagram illustrating an example of pattern division processing. FIG. 2A shows a processing target layout. In the processing target layout, as described above, a plurality of patterns are arranged at a distance S1 that is smaller than the manufacturing limit. Therefore, when seven patterns included in this processing target layout are assigned to one mask, adjacent patterns are not resolved in the lithography process as shown in FIG. 2B. Therefore, as shown in FIG. 2C, the processing target layout is divided so that adjacent patterns are assigned to different masks (mask A and mask B). FIG. 2D shows a mask layout assigned to one mask A, and FIG. 2E shows a mask layout assigned to the other mask B. Here, as shown in FIG. 2D, in the layout assigned to the mask A, adjacent patterns are sufficiently separated from each other, and no problem occurs in the lithography process. On the other hand, as shown in FIG. 2E, in the layout assigned to the mask B, there is still a portion where the interval between adjacent patterns is smaller than the manufacturing limit. Therefore, as shown in FIG. 2F, a divided portion C is set for each of the three patterns having the pattern width W2, and each pattern is divided at the divided portion C. As a result, in the layouts assigned to the same mask, it is possible to eliminate portions where patterns are adjacent at intervals smaller than the manufacturing limit.

  FIG. 3 is a flowchart showing an operation method in the case where the pattern cutting process is executed by the computer. First, the computer arranges a plurality of cells by arrangement and wiring, and generates full chip layout data indicating a full chip layout (step S100). Next, in the full chip layout, adjacent patterns are grouped (step S101). Next, in each group, each pattern is assigned to one of a plurality of masks (step S102). After the processing in step S102 is performed for all groups, it is determined whether or not there is a portion where the distance between patterns assigned to the same mask is an error (a distance smaller than the manufacturing limit). The If such a part exists, the part is detected as an error part (step S103). Next, based on the detection result of the error part, the patterns are divided so that the patterns assigned to the same mask are not adjacent to each other (step S104), and the divided layout data is output (step S105). In steps S103 and S104, if the error portions are close to each other, the pattern division is given up and the placement and routing (step S100) is performed again.

  As described above, by dividing the pattern, it is possible to prevent a portion that is not resolved in the lithography process. However, in the method shown in FIG. 3, it is necessary to redo the placement and routing when error portions exist close to each other. Therefore, there is a problem that the design man-hour increases.

  Further, in a portion where the pattern is divided, processing deterioration occurs due to an overlay error of a plurality of masks. When a pattern with a small width is divided, processing deterioration increases, and the yield may decrease. Furthermore, high processing accuracy is required for patterns (critical paths, etc.) that are important for circuit operation. Even when such an important pattern is divided, there is a problem that the yield is lowered.

  In addition, the above-described Patent Documents 1 to 5 disclose techniques related to double patterning, but there is no description on how to determine a portion where the pattern is divided. Further, Patent Document 6 discloses a point in which attribute information is given to a cell, but there is no description about double patterning, and there is no description about how a part where a pattern is divided is determined.

  A mask layout dividing method according to the present invention includes a step of obtaining cell layout data indicating a cell layout of each of a plurality of types of cells, and a pattern dividing portion generated when the cell layout is divided into a plurality of mask layouts. Setting a plurality of candidates as a plurality of division candidates, generating cell layout data with division candidates corresponding to each of the plurality of types of cells, and a plurality of cells based on the cell layout data with division candidates Generating full chip layout data indicating a layout of a full chip including the positions of the plurality of division candidates in a full chip, and selecting a division candidate group to be adopted from among the plurality of division candidates indicated in the full chip layout data; , The pattern will be divided by the selected candidate group In comprises a step of dividing the layout the illustrated full chip layout data, and generating a divided layout data indicating the division result.

  A mask layout dividing device according to the present invention acquires cell layout data indicating a cell layout of each of a plurality of types of cells, and a plurality of pattern division portions generated when the cell layout is divided into a plurality of mask layouts. A candidate is set as a plurality of division candidates, and cell layout data with division candidates corresponding to each of the plurality of types of cells is generated, and a plurality of division candidates are generated based on the cell layout data with division candidates. Generating a full chip layout data indicating a layout of a full chip including the cells and positions of the plurality of division candidates in a full chip, and selecting a division candidate group to be adopted from among the plurality of division candidates indicated in the full chip layout data; In order to divide the pattern in the selected division candidate group, Dividing the layout indicated by the play-out data to generate divided layout data indicating the result of division, includes a pattern division unit.

  The data structure of the cell library according to the present invention includes cell layout data indicating a cell layout of each of a plurality of cells, and a plurality of candidates for pattern division portions generated when the cell layout is divided into a plurality of mask layouts. Division candidate data indicated as a plurality of division candidates.

  ADVANTAGE OF THE INVENTION According to this invention, the data structure of the mask layout division | segmentation method, mask layout division | segmentation apparatus, and cell library which can divide | segment a pattern in an appropriate part is provided.

It is a figure which shows an example of the layout divided | segmented. It is a conceptual diagram which shows an example of the division process of a pattern. It is a flowchart which shows a pattern parting process. It is a figure which shows the outline | summary of this invention. It is a block diagram which shows the mask layout division | segmentation apparatus which concerns on embodiment. It is a flowchart which shows the process with respect to each kind of cell. It is a figure which shows an example of a cell layout. It is a figure which shows a division | segmentation candidate pattern. It is a figure which shows a division | segmentation candidate pattern. It is a figure which shows an example of cell layout data with a division | segmentation candidate with which the rank value was set. It is a conceptual diagram which shows an example of the data structure of a cell library. It is a figure which shows the example of a description of the cell by a GDSII format. It is a flowchart which shows the process in a full chip. It is a figure which shows a part of full-chip layout. It is a figure which shows a some division | segmentation candidate pattern. It is a figure which shows a some division | segmentation candidate pattern. It is a figure which shows an example of the division | segmentation method of a full chip pattern. It is a figure which shows an example of the division | segmentation method of a full chip pattern. It is a figure which shows an example of the division | segmentation method of a full chip pattern. It is a figure which shows the some division | segmentation candidate pattern in 2nd Embodiment. It is a figure which shows the some division | segmentation candidate pattern in 2nd Embodiment.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 4 is a diagram showing an outline of the present invention. As shown in FIG. 4, in this embodiment, a plurality of pattern division part candidates (hereinafter, division candidates) and rank values of the division candidates are set for each cell layout of a plurality of types of cells. (Cell division rank generation). Thereby, cell layout data with division candidates indicating each type of cell is obtained. The rank value is a parameter indicating the degree of risk when a pattern is divided at each division candidate, and is obtained by process simulation. After that, cell layout data with division candidates for a plurality of types of cells is used as a cell library, and a plurality of cells are arranged so as to obtain a desired function by arrangement and wiring, and full chip layout data indicating a full chip layout is obtained. . At this time, information indicating a plurality of division candidates and their rank values is taken into the full chip layout data. Next, the rank value of each division candidate in the full chip layout data is changed based on the full chip layout data and the design intent information. The design intent information is information that is generated when full-chip layout data is generated, and is information that indicates the position of an important part in the operation of the circuit. Then, based on the changed rank value, a division candidate group to be adopted is selected from among a plurality of division candidates so that the degree of risk becomes small, and the full chip layout is divided into a plurality of mask layouts.

  According to the processing as described above, a plurality of division candidates are set for each cell in the design stage of the cell library. Since a plurality of division candidates are set, it is possible to increase the degree of freedom when dividing the full chip layout and to prevent re-arrangement and wiring. Further, since a rank value is set for each division candidate, it is possible to divide the full chip layout so as to reduce the degree of risk. Furthermore, since the rank value is changed based on the design intent information, it is possible to make it difficult for a pattern important for circuit operation to be divided.

(First embodiment)
The mask layout dividing apparatus 1 according to the first embodiment will be described below. FIG. 5 is a block diagram showing the mask layout dividing apparatus 1 according to this embodiment. The mask layout dividing apparatus 1 includes an input unit 2, an adjacent pattern generation unit 3, a division candidate generation unit 4, a process simulation unit 5, a rank generation unit 6, a pattern division unit 8, a design intent input unit 9, and an output unit 10. I have. These are realized, for example, when the CPU executes a mask layout division program stored in a ROM (Read Only Memory).

  The mask layout dividing apparatus 1 according to the present embodiment performs processing (processing for building a cell library) and full-chip processing for each of a plurality of types of cells. First, processing for each type of cell will be described. FIG. 6 is a flowchart showing processing for each type of cell.

Step S1: Cell Layout Input First, the input unit 2 acquires cell layout data indicating the cell layout of each of a plurality of types of cells. FIG. 7A is a diagram illustrating an example of a cell layout. The cell layout shown in FIG. 7A includes seven patterns as in the example shown in FIG. The seven patterns include four patterns having a pattern width W1 (hereinafter referred to as pattern W1) and three patterns having a pattern width W2 (hereinafter referred to as pattern W2). The width W1 is larger than the width W2. These patterns are arranged at a distance S1 that is smaller than the manufacturing limit. In the following description, processing for the cell layout shown in FIG. 7A will be described as an example.

Step S2: Creation of Dividing Candidate Subsequently, a plurality of dividing candidates are set in the cell layout. Specifically, the adjacent pattern generation unit 3 obtains a distance between patterns in the cell layout based on the cell layout data, and recognizes a portion where the obtained distance is smaller than the manufacturing limit. Then, based on the recognition result, the division candidate generation unit 4 sets a plurality of portions where the pattern may be divided as a plurality of division candidates, and generates cell layout data with division candidates. FIG. 7B shows an example of cell layout data with division candidates. In the example shown in FIG. 7B, seven patterns are arranged at a distance S1 that is smaller than the manufacturing limit. Therefore, a division candidate 11 is set for each of the seven patterns.

Step S3: Creation of Division Candidate Pattern Subsequently, the division candidate generation unit 4 determines a plurality of division candidate patterns based on the plurality of division candidates 11 set. 8A and 8B are diagrams illustrating a plurality of division candidate patterns. In the division candidate pattern shown in FIG. 8A, three division candidates 11 set for three patterns W2 are employed. On the other hand, in the division candidate pattern shown in FIG. 8B, four division candidates 11 set in four patterns W1 are employed.

Step S4: Process Simulation Subsequently, the process simulation unit 5 performs a lithography process simulation for each of a plurality of division candidate patterns, and calculates a finished shape.

Step S5: A rank is assigned to a division location. Next, the rank generation unit 6 employs each division candidate 11 based on a simulation result in the process simulation unit 5, a target pattern shape, a mask overlay error, and the like. The processing accuracy in case is obtained. The rank generation unit 6 sets a rank value indicating the degree of risk for each division candidate based on the obtained machining accuracy. That is, the lower the machining accuracy, the larger the rank value is set. FIG. 9 is a diagram illustrating an example of cell layout data with division candidates in which rank values are set. When a pattern with a small width is divided, the processing accuracy is lower than when a pattern with a large width is divided. Therefore, in the example shown in FIG. 9, the rank value of each division candidate 11 set in the pattern W2 having a smaller width than the rank value (= 1) of each division candidate 11 set in the wide pattern W1. (= 2) is larger.

Step S6: Have all the cells been completed?
Next, the rank generation unit 6 determines whether or not the processing in steps S2 to S5 has been performed for all of the plurality of cells. If there is an unprocessed cell, the unprocessed cell is selected as a cell to be processed, and the processes in and after step S2 are repeated.

Step S7: Cell layout output with division candidates When the processing of steps S2 to S6 is completed for all of a plurality of cells, the rank generation unit 6 sets the cell layout data with division candidates set with rank values (see FIG. 9). ) Is output. Thereby, the cell library 7 which shows cell layout data with a division | segmentation candidate about each of several cells is constructed | assembled.

  FIG. 10 is a conceptual diagram showing an example of the data structure of the cell library 7. In the example shown in FIG. 10, a cell B and a cell C are included in the cell A. Each of the cell B and the cell C includes graphic information indicating a cell layout and division information indicating division candidates. The graphic information includes a layer number and polygon coordinate information. The division information also includes the layer number and polygon coordinate information. The rank value of the division candidate is reflected in the layer number of the division information. That is, the cell B includes a division candidate having a rank value of “1”, and the cell C includes a division candidate having a rank value of “2”. FIG. 11 is a description example of the cell B in the GDSII format. In the example shown in FIG. 11, the cell B is defined as “STRUCTURE”. Further, the layer number of the division candidate is defined by “LAYER”. Furthermore, a rank value is defined by “DATATYPE”. Further, “COORDINATES” defines the position (division mark figure) of the division candidate.

  Next, full chip processing will be described. FIG. 12 is a flowchart showing processing in a full chip.

Step S8: Full Chip Layout Generation The pattern dividing unit 8 refers to the cell library 7, arranges a plurality of cells so as to obtain a desired function by arrangement and wiring, and generates full chip layout data indicating the full chip layout. At this time, the division candidate and the rank value are captured in the full chip layout data. Also, design intent information is generated when full-chip layout data is generated. As described above, the design intent information is information indicating an important part in the operation of the circuit. In the present embodiment, information indicating a critical path is generated as design intent information.

Step S9: Input of Design Intent Information Subsequently, the design intent input unit 9 acquires design intent information.

Step S10: Rank addition based on design intent information Next, the pattern dividing unit 8 changes the rank value of each division candidate in the full chip layout data based on the full chip layout data and the design intent information. FIG. 13 is a conceptual diagram showing a part of the full chip layout indicated by the full chip layout data, and is a diagram showing a part where the cells shown in FIG. 9 are arranged. FIG. 13 also shows the position of the critical path 13. As shown in FIG. 13, in the full chip layout, one of the four patterns W <b> 1 overlaps the critical path 13. Therefore, the pattern dividing unit 8 increases the rank value of the division candidate 11 that overlaps the critical path. In the example illustrated in FIG. 13, the rank value of the division candidate 11 that overlaps the critical path 13 is changed from “1” to “5”.

Step S11: Generation of Candidate Patterns from Dividing Marks Subsequently, the pattern dividing unit 8 generates a plurality of dividing candidate patterns for each arranged cell based on the plurality of dividing candidates 11 indicated in the full chip layout data. 14A and 14B are diagrams illustrating a plurality of division candidate patterns. In the division candidate pattern shown in FIG. 14A, the division candidate 11 of four patterns W1 is adopted. On the other hand, in the division candidate pattern shown in FIG. 14B, the division candidate 11 of the three patterns W2 is adopted.

Step S12: Select Candidate Pattern with Low Total Rank Next, the pattern division unit 8 selects a division candidate pattern having the smallest rank value from among a plurality of division candidate patterns. In the division candidate pattern shown in FIG. 14A, the sum of rank values is 8 (= 1 + 1 + 1 + 5). On the other hand, in the division candidate pattern shown in FIG. 14B, the total rank value is 6 (= 2 + 2 + 2). Therefore, the pattern division unit 8 selects the division candidate pattern shown in FIG. 14B. Thereby, a division candidate group to be adopted is selected from among a plurality of division candidates shown in the full chip layout data.

Step S13: Generate Dividing Pattern Next, the pattern dividing unit 8 divides the full chip layout into a plurality of mask layouts so as to be divided by the selected dividing candidate pattern.

Step S14: Is there a similar color in the adjacent pattern?
Next, the pattern dividing unit 8 determines whether there is a portion where adjacent patterns are assigned to the same color (mask). When there is a portion where adjacent patterns are assigned to the same mask, the operations after step S12 are repeated.

Step S15: Have all the cells been completed?
If there is no portion where adjacent patterns are assigned to the same mask, the pattern dividing unit 8 checks whether or not the processing has been completed for all the arranged cells. When there is an unfinished cell, the operations after step S11 are repeated.

Step S16: Divided layout output When all the cells are completed, the output unit 10 outputs the division result of the full chip layout as divided layout data.

  Then, the effect of this embodiment is demonstrated.

  According to the present embodiment, in the cell library 7, a plurality of division candidates are set for each cell, and the plurality of division candidates are taken into full-chip layout data. For this reason, the freedom degree at the time of dividing a full chip layout can be increased, re-doing of placement and routing can be prevented, and design man-hours can be reduced.

  Moreover, according to this embodiment, the rank value which shows a danger level is set to each division | segmentation candidate. Therefore, based on the rank value, the full chip layout can be divided so that the degree of risk is reduced, and the yield can be increased. For example, in the case of the example shown in FIGS. 14A and 14B, the division candidate pattern shown in FIG. 14B is adopted as described above. Thereby, it is possible to prevent the pattern forming the critical path 13 from being divided. In a portion important for the operation of the circuit, the influence of the manufacturing deterioration due to the mask deviation can be reduced, and the yield can be improved and the performance deterioration can be prevented. If no pattern overlaps the critical path 13 in FIG. 13, the sum of rank values in the division candidate pattern shown in FIG. 14A is 4 (= 1 + 1 + 1 + 1), and the division candidates shown in FIG. 14A. A pattern is selected. Thereby, it is possible to prevent a pattern having a small width from being divided. That is, a pattern with a smaller width can be made difficult to be divided.

  15A to 15C are diagrams illustrating an example of a full-chip pattern dividing method. FIG. 15A shows an example of the layout of each cell registered in the cell library 7. This cell includes a central pattern arranged in the center and a pair of side patterns arranged on both sides. In this cell, division candidates 11 are set for each of the central pattern and the pair of side patterns. 15B and 15C are diagrams illustrating an example of the division result of the full chip layout, and are diagrams of portions corresponding to the cells illustrated in FIG. 15A. In FIG. 15B and FIG. 15C, the critical path 13 is drawn in an overlapping manner. Normally, the division result shown in FIG. 15B is adopted so that the critical path 13 is not taken into consideration and only one division is required. On the other hand, in this embodiment, since the critical path 13 is considered, the division candidate 11 that overlaps the critical path 13 is not employed, and the division result illustrated in FIG. 15C is employed. That is, according to this embodiment, it is avoided that the pattern is divided in the critical path 13.

  In step S12, the pattern dividing unit 8 preferably selects the division candidate patterns so that the patterns overlapping the critical path 13 are assigned to the same mask. Since the patterns overlapping the critical path 13 are formed by the same mask, it is possible to easily manage the accuracy of the completed mask.

  In addition, a mask is manufactured based on the divided layout data generated in the present embodiment. The mask is subjected to defect inspection after manufacturing. At this time, the accuracy in the defect inspection may be determined according to the rank value obtained in the present embodiment. A yield can be improved by inspecting a place where higher accuracy is required with high accuracy.

(Second Embodiment)
Next, the second embodiment will be described. In the first embodiment, the case where information indicating the critical path 13 is used as the design intent information has been described. In contrast, in the present embodiment, information indicating the position of the diffusion layer of the transistor is used as the design intent information. The other points are the same as in the first embodiment.

  16A and 16B are diagrams showing a plurality of division candidate patterns, and are diagrams corresponding to FIGS. 14A and 14B in the first embodiment. As shown in FIGS. 16A and 16B, in this layout, two of the four patterns having the width W1 overlap the diffusion layer 12. Therefore, as shown in FIG. 16A, the rank value of the division candidate set in the two patterns overlapping with the diffusion layer 12 is changed from “1” to “3”. As a result, the sum of the rank values in the division candidate pattern shown in FIG. 16A is “8 (= 1 + 3 + 3 + 1)”, and “6 (= 2 + 2 + 2)”, which is the sum of the rank values in the division candidate pattern shown in FIG. 16B. Is also getting bigger. Therefore, the division candidate pattern shown in FIG. 16B is adopted, and the pattern overlapping the diffusion layer is prevented from being divided.

  If a pattern is divided at a portion where a transistor is formed, the transistor operation may be greatly affected. According to the present embodiment, the portion of the transistor that overlaps with the diffusion layer 12 is difficult to be divided, so that it is possible to prevent deterioration in processing accuracy in the transistor formation portion and to prevent a decrease in yield.

  The present invention has been described above using the first and second embodiments. These embodiments are not independent from each other, and can be used in combination within a consistent range.

DESCRIPTION OF SYMBOLS 1 Mask layout division | segmentation apparatus 2 Input part 3 Adjacent pattern production | generation part 4 Dividing candidate production | generation part 5 Process simulation part 6 Rank production | generation part 7 Cell library 8 Pattern division part 9 Design intent input part 10 Output part 11 Dividing candidate 12 It overlaps with a diffusion layer Area 13 Critical Path

Claims (16)

Obtaining cell layout data indicating the cell layout of each of the plurality of types of cells;
A plurality of candidates for pattern division portions generated when dividing the cell layout into a plurality of mask layouts are set as a plurality of division candidates, and cell layout data with division candidates corresponding to each of the plurality of types of cells is set. Generating step;
Generate full-chip layout data indicating a layout of a full chip including a plurality of cells based on the cell layout data with division candidates, and select a division candidate group to be adopted from among the plurality of division candidates indicated in the full-chip layout data And steps to
Dividing the layout indicated by the full-chip layout data so that a pattern is divided by the selected division candidate group;
Generating split layout data indicating the split results;
A mask layout dividing method comprising: The mask layout dividing method according to claim 1,
Furthermore,
Obtaining the cell layout data with division candidates, and setting a rank value indicating a degree of risk for each of the plurality of division candidates;
Comprising
The step of selecting the division candidate group includes a step of selecting the division candidate group to be adopted based on the rank value. The mask layout dividing method according to claim 2,
The step of selecting the division candidate group includes:
Changing the rank value of each division candidate in the full-chip layout data based on design intent information that is prepared in advance and indicates the position of an important part;
And a step of selecting the division candidate group to be adopted based on the changed rank value. The mask layout dividing method according to claim 3,
The design intent information includes information indicating the position of the critical path,
The step of changing the rank value includes a step of increasing the rank value when each of the division candidates overlaps the critical path. The mask layout dividing method according to claim 3 or 4,
The design intent information includes information indicating the position of the diffusion layer in the transistor,
The step of changing the rank value includes a step of increasing the rank value when each of the division candidates overlaps the diffusion layer. A mask layout dividing method according to any one of claims 3 to 5,
The method of dividing a mask layout includes the step of dividing the layout indicated by the full-chip layout data so that a pattern overlapping the important part is assigned to the same mask. The mask layout dividing method according to any one of claims 2 to 6,
Furthermore,
Calculating a pattern shape actually formed when each of the division candidates is adopted by simulation,
Comprising
The step of setting the rank value includes a step of calculating a manufacturing error in the case where each of the division candidates is adopted based on the calculated pattern shape, and determining the rank value based on the manufacturing error. Including mask layout division method.   A mask layout dividing program for realizing the mask layout dividing method according to claim 1 by a computer. Cell layout data indicating the cell layout of each of a plurality of types of cells is obtained, and a plurality of candidates for pattern division portions that occur when the cell layout is divided into a plurality of mask layouts are set as a plurality of division candidates. A division candidate generation unit that generates cell layout data with division candidates corresponding to each of the plurality of types of cells;
Based on the cell layout data with division candidates, a full-chip layout including a plurality of cells and full-chip layout data indicating positions of the plurality of division candidates in a full chip are generated, and the plurality of division candidates indicated in the full-chip layout data Selecting a division candidate group to be adopted from the above, dividing the layout indicated by the full-chip layout data so that the pattern is divided by the selected division candidate group, and generating divided layout data indicating a division result A dividing section;
A mask layout dividing apparatus comprising: The mask layout dividing apparatus according to claim 9, wherein
Furthermore,
A rank generation unit that acquires the cell layout data with division candidates and sets a rank value indicating a degree of risk for each of the plurality of division candidates.
Comprising
The said pattern division part is a mask layout division apparatus which selects the division candidate group to employ | adopt based on the said rank value. The mask layout dividing apparatus according to claim 10,
The pattern dividing unit is prepared in advance and changes the rank value of each division candidate in the full-chip layout data based on design intent information indicating the position of an important part, and based on the changed rank value A mask layout dividing device for selecting the division candidate group to be adopted. The mask layout dividing apparatus according to claim 11,
The design intent information includes information indicating the position of the critical path,
The pattern dividing unit is a mask layout dividing device that increases the rank value when each of the division candidates overlaps the critical path. The mask layout dividing apparatus according to claim 11 or 12,
The design intent information includes information indicating the position of the diffusion layer in the transistor,
The pattern dividing unit is a mask layout dividing device that increases the rank value when each of the division candidates overlaps the diffusion layer. A mask layout dividing apparatus according to any one of claims 11 to 13,
The pattern division unit is a mask layout division apparatus that divides a layout indicated by the full-chip layout data so that a pattern overlapping the important part is assigned to the same mask. The mask layout dividing apparatus according to any one of claims 10 to 14,
Furthermore,
A process simulation unit that calculates a pattern shape that is actually formed when each of the division candidates is adopted by simulation,
Comprising
The rank generation unit calculates a manufacturing error when each division candidate is adopted based on the calculated pattern shape, and determines the rank value based on the manufacturing error. Cell layout data indicating the cell layout of each of the plurality of cells;
Dividing candidate data indicating a plurality of candidates for pattern dividing portions generated when dividing the cell layout into a plurality of mask layouts, as a plurality of dividing candidates;
A data structure of a cell library comprising:

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