JP2002055431A - Mask data pattern forming method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a mask data pattern forming method which is capable of drastically shortening the TAT up to mask delivery of products. SOLUTION: This method is applied to semiconductor products which stepwise form layout patterns like ASIC product, such as gate arrays, and the cell patterns which are not changed in the patterns by each of product logic's is previously subjected to OPC processing prior to arranging and wiring. The cell patterns subjected to the OPC processing are previously registered in a data base. Separately therefrom, the wiring patterns formed in accordance with the arranging information of the product logic is subjected to the OPC processing and the wiring patterns subjected to the OPC processing and the arranging patterns arranged with the cell patterns subjected to the OPC processing registered in the data base are synthesized and the chip patterns subjected to the OPC processing are formed. The mask is formed by using the chip patterns subjected to the OPC processing as the mask data patterns.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask data pattern generation technique, and more particularly, to a mask data pattern generation method which can greatly reduce the TAT of a semiconductor product such as an ASIC until a mask is paid out. About technology.

[0002]

2. Description of the Related Art In recent years, as the miniaturization of wiring of semiconductor products has progressed, the mask pattern is required to be close to the layout design pattern (expected pattern to be completed) in order to correct the optical proximity effect when transferring the mask pattern. There has been used a method of forming a pattern on which an OPC (Optical Proximity Effect Correction) process is performed in consideration of the effect.

A technique relating to a method of generating a mask data pattern subjected to such an OPC process is described in, for example, “Advanced Electronics I-17 ULSI Process Technology” published on June 10, 1997 by Baifukan Co., Ltd. The techniques described are mentioned.

[0004]

The inventors of the present invention have studied the technique of generating a mask data pattern on which the above-described OPC processing has been performed, and as a result, the following has been found. The contents of the study will be described with reference to the explanatory diagram of the OPC process in FIG. 10 and the flowchart of the mask data pattern generation method by the chip batch OPC process in FIG.

In drawing a pattern of a semiconductor device or the like,
In order to obtain a pattern close to the target during product processing, FIG.
In some cases, OPC processing is performed based on a design pattern, and mask / reticle drawing is performed using a pattern different from the design pattern, as shown in FIG. For example, if the design pattern 31 is used as a mask pattern 32 as shown in FIG.
Since the completed shape is significantly different from the design pattern 31, OPC patterns such as a dog bone 35 for suppressing the shortening 33 of the wiring tip and a serif 36 for preventing the sagging 34 at the corner are added as shown in FIG. 10B. By using the OPC-processed pattern 37 to make the finished shape close to the design pattern 31, a method is adopted.

The generation of such an OPC-processed pattern is usually performed in steps S201 to S2 as shown in FIG.
In step S204, the OPC process is performed on the chip pattern immediately before the generation of the mask pattern after the placement and routing based on the product logic (step S204). When the number of elements integrated on one chip increases, the mask is created. Each time, the overhead caused by performing the OPC process on the entire chip becomes large, so that the TAT for creating the mask becomes long. That is, in a semiconductor product that requires a short TAT, the time required for the OPC process occupies a large proportion of the TAT until the mask is paid out.

Therefore, the present inventor has proposed that in a semiconductor product such as an ASIC that generates a layout pattern stepwise, most of the contact patterns connected to the diffusion layer pattern and most of the lower wiring patterns constituting the circuit cells are formed. Since the cell pattern is occupied, it was conceived that if the OPC processing of the cell pattern could be speeded up, the TAT until the product was dispensed with the mask could be significantly reduced.

A semiconductor product that generates a layout pattern stepwise corresponds to a layout pattern of a wiring layer corresponding to one type of layout pattern of a diffusion layer such as an ASIC. Combining diffusion layer patterns prepared in common for all products, arranging cell patterns that constitute circuit elements, generating wiring patterns connected between the arranged cells, and generating product layout patterns This is a product that generates a layout pattern step by step.

Accordingly, an object of the present invention is to provide a semiconductor product such as an ASIC that generates a layout pattern step by step, in order to speed up the OPC process of the cell pattern, use a cell pattern prepared in advance for the product in common. On the other hand, by providing an OPC process and registering the mask data pattern, it is possible to provide a mask data pattern generation method capable of greatly shortening the TAT until the mask is paid out of the product.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

In the present invention, a plurality of types of wiring layer layout patterns correspond to one type of diffusion layer layout pattern such as an ASIC, and the wiring layer layout patterns are prepared in advance in common for all products. The layout pattern is generated step by step by arranging the cell patterns that constitute the circuit elements by combining the diffusion layer patterns, generating the wiring patterns connected between the arranged cells, and generating the product layout patterns. By adding an OPC pattern to a cell pattern prepared in advance for a product, the OPC of the product mask
In the processing, only the OPC processing of the wiring pattern connecting the cells can be performed. In many cases, the wiring pattern connecting the cells is a combination of simpler element patterns than the cell pattern.
In some cases, the processing can be simplified as compared with the processing of the C processing cell pattern, so that the processing can be further speeded up.

That is, the method of generating a mask data pattern according to the present invention has the following features.

(1) OPC-processed pattern or OP
The pattern for the C processing operation is held in the design layout data, not as a temporary pattern at the time of generating the mask. The design layout data is a cell library pattern that can be used for all products. The design layout data is a chip fixed pattern depending on a chip series (type). Data for distinguishing between an area where the OPC process is performed and an area where the OPC process is not performed is held in the data. The cell pattern and the wiring pattern are held as different layers in the layout data even if they are the same mask layer.

(2) A layout design in which a cell pattern and a wiring pattern are completely separated so that OPC processing can be performed independently. The separation method is the same layer pattern as the cell pattern, and no connection is made between the cell patterns. The separation method is to make the wiring pattern connection portion of the cell a special shape so that the wiring layer pattern does not become inconsistent even when independently subjected to the OPC process.

(3) When the cell pattern and the wiring pattern interfere with each other, the addition and subtraction patterns are arranged so that the portions match. The shape of the wiring pattern connection portion of the cell is divided into patterns, and correction is performed using an addition / subtraction pattern prepared in advance. An addition / subtraction pattern is generated using software for automatically creating the above addition / subtraction pattern.

(4) A detailed OPC process is performed on the cell pattern, and a simple OPC process is performed on the wiring pattern. An uneven OPC process level is set in the product. The cell pattern is corrected in detail by simulation, and the wiring pattern is simplified by making the layout rule a rule that does not require detailed correction. The wiring pattern does not provide the layout flexibility like the cell pattern, but limits the types of wiring width, restricts the bending of the wiring pattern, and prohibits the intersection, thereby simplifying the category classification of the OPC correction pattern and increasing the speed. Perform the conversion.

(5) When a cell pattern is arranged, the OP of the cell pattern depends on the type of the adjacent cell at the arranged position.
The C correction pattern is different. The correction based on the adjacent cell type is processed by a combination of a main pattern irrespective of the adjacent cell and a sub-pattern depending on the adjacent cell.
The case of the adjacent cells is not a combination of all cells, but a combination of categories of cells having the same kind of geometry. A program for generating the adjacent cell correction pattern is prepared. It is assumed that the cell pattern has a correction pattern so that the category classification of adjacent cells is reduced. If there is no neighbor cell, a dummy neighbor cell is placed.

(6) A cell pattern is prepared for each process such as a wiring material, a wiring film thickness, and an exposure device, and a cell pattern used when a process such as a wiring material, a wiring film thickness, an exposure device is changed, or a production line is changed. By replacing the pattern library, it is possible to respond to a new process specification without requiring OPC processing of a new cell pattern.

Therefore, according to the mask data pattern generation method, a new O
The product creation TAT can be significantly reduced as compared with the case where PC processing is performed. As a result, an optimized OPC process can be performed on a cell pattern, which is a common pattern in advance, without concern for TAT, thereby increasing the process margin and reducing the cost by improving the yield and the selling price by improving the product performance. Improvement can be achieved. In addition, even a miniaturized semiconductor product can be manufactured with a short TAT, and short-term delivery can be realized.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a flowchart showing a mask data pattern generation method (hierarchical OPC processing) according to an embodiment of the present invention, and FIGS. 2 to 9 show details of the OPC processing in the mask data pattern generation method in this embodiment. FIG.

First, referring to FIG. 1, a procedure of an example of a mask data pattern generation method by the hierarchical OPC process according to the present embodiment will be described. In the present embodiment, the present invention is applied to a semiconductor product that generates a layout pattern in stages, such as an ASIC product such as a gate array.
The C-processed pattern or the pattern for the OPC process calculation is held in the design layout data, not as a temporary pattern at the time of generating the mask. This design layout data is a cell library pattern that can be used in common for all products, and a chip series (type: difference in power consumption model, presence or absence of RAM for the same size, etc.)
It is a chip-fixing pattern that depends on it.

In the mask data pattern generation method according to the present embodiment, a cell pattern forming a circuit element of product logic is first created based on FIG. 1 (step S101).
Before placing and routing a cell pattern (including a chip fixing pattern) whose pattern does not change for each product logic,
PC processing is performed in advance (step S102). This OPC
The cell pattern generated by the processing is registered in a database.

Further, using the cell pattern registered in the database, the cell pattern is arranged according to the product logic arrangement information stored in the chip logic file (step S103). The cell pattern at this time is an OPC-processed cell pattern (step S104).

Separately, a wiring pattern is generated according to the product logic arrangement information stored in the chip logic file (step S105), and the OPC process is performed on the wiring pattern (step S106). This OPC
The wiring pattern generated by the processing becomes the OPC-processed wiring pattern (step S107).

Thereafter, the arrangement pattern of the OPC-processed cell pattern and the OPC-processed wiring pattern are combined to generate an OPC-processed chip pattern (step S).
108). A mask can be generated by using the OPC-processed chip pattern as a mask data pattern.

Next, the operation of this embodiment will be described with reference to FIG.
A specific example of the OPC process in the mask data pattern generation method will be described in detail with reference to FIGS.

FIGS. 2A to 2C are explanatory diagrams showing the interference between OPC patterns of different levels. FIGS. 2A to 2C show cases where the cell pattern and the wiring pattern do not interfere with each other.
Each shows a plane pattern in the case of interference.

In order to perform the OPC process for the cell pattern and the OPC process for the wiring pattern independently as shown in FIG.
As shown in FIG. 2 (c), they must not interfere with each other. If the two interfere as shown in FIG. 2 (f), there will be a discrepancy with the case where the independently processed OPC patterns are combined as shown in FIG. 2 (h). That is,
When the cell pattern and the wiring pattern do not interfere with each other, the OPC processing is performed on the wiring pattern 1 as shown in FIGS. 2A to 2C, and the OPC processing of the OPC-processed cell pattern 2 and the wiring pattern 3 is performed. Processed wiring pattern 4
May be synthesized. In this case, the mask pattern 5 is OK
Becomes However, when the cell pattern and the wiring pattern interfere with each other, if the OPC-processed wiring pattern 4a obtained by performing the OPC processing on the wiring pattern 3a as shown in FIGS. Becomes
The single pattern 6 differs from the originally expected OPC-processed single pattern 7 as shown in FIGS. Further, as shown in FIG. 2 (i), when the OPC process is performed independently, a difference occurs in the interference portion 8 where the pattern interferes.

FIGS. 3A and 3B are explanatory diagrams showing a method (separation by layers) for ensuring the independence of the OPC pattern. FIG. 3A is a perspective structure of the OPC pattern, and FIGS. Each pattern is shown.

In order not to cause a discrepancy with the expected pattern as shown in FIG. 2, the terminal of the cell is not connected to the terminal of the cell by wiring of the same layer as in FIG. The connection makes it possible to prevent the cell pattern and the wiring pattern from independently interfering in the same layer. That is, as shown in FIG. 3A, the cell pattern 1b is arranged on the M1 layer, the wiring pattern 3b is arranged on the M2 layer, and the space therebetween is connected by the via pattern 9 of the via layer. Thereby, as shown in FIGS. 3B and 3C, the O of the cell pattern 1b is changed.
O of PC processed cell pattern 2b and wiring pattern 3b
Although the wiring pattern 4b appears to interfere with the PC-processed wiring pattern 4b on the plane, the mask pattern 5b does not actually interfere with the M1 layer pattern and the M2 layer pattern as shown in FIG. .

Further, according to the mask data pattern generation method of the present embodiment, in the process of FIG.
In order to distinguish between data to be subjected to C processing and data not to be processed, link information to the data, coordinate positions on the chip,
By dividing the processing by area and layer by distinguishing by additional information such as data layer name (layer number) and property,
For example, the amount of data processed at one time can be reduced. It is also possible to combine data that has been distinguished after the OPC process and integrate them as one mask data.

By dividing the OPC process into a plurality of stages as described above, the product TAT is not affected even if the OPC process of the cell pattern takes time. For this reason, detailed processing is performed on the cell pattern by simulation-based OPC processing, which takes a longer time, and the wiring pattern is usually processed by the entire chip.
Non-uniform OPC processing in the product, such as performing C processing, becomes possible. In particular, the ability to perform a detailed OPC process in a cell having a complicated pattern shape enables a finer shape to be described by a layout tool for a wiring portion, resulting in an increase in the process margin or the degree of integration.

Further, in order to further speed up the processing of the wiring portion, the OPC rule is simplified or a higher-speed OPC processing algorithm is applied by adding a restriction different from that in the cell to the pattern shape of the wiring portion. It can be used. Here, the shape restriction includes, for example, limiting the type of wiring width to be used, prohibiting bending (bending) of wiring patterns, prohibiting intersection of wiring patterns on the same layer, prohibiting vias at wiring ends,
For example, there are restrictions on cell terminal positions.

FIG. 4 is an explanatory diagram showing a case where a cell pattern is devised so as not to cause a problem due to hierarchization.
When (a) to (c) add a pattern for wiring pattern connection to a part of the cell pattern and provide an OPC processing suppression area in the connection part, particularly, (d) to (f) show wiring in the connection part. Are connected, and (g) to (h) show planar patterns when no wiring is connected to the connection portion, respectively.

For example, by devising the shape of the connection portion between the cell pattern and the wiring pattern, it is possible to obtain a pattern having no problem as a product even if both interfere. As an example, the terminals of the cell may be arranged in a pattern as shown in FIG. 4A so that the OPC process around the terminals is not performed. That is, as shown in FIG. 4A, a wiring connection part connection pattern 10 is added to a part of the cell pattern 1c, and this wiring pattern connection part 11 is made to be the OPC processing suppression area 12, whereby the wiring pattern connection part 11 becomes the OPC processing suppression area 12. Like O
The non-patterned portion 13 is created where a normal OPC pattern occurs in the PC processed cell pattern 2c. When there is no OPC processing suppression area 12 as shown in FIG. Further, the connection direction of the wiring pattern 3c is restricted as shown in FIG. 4D, and when the wiring pattern 3c is connected to the non-patterned portion 13 of the connection portion, the OPC is performed as shown in FIG.
Generation of the OPC pattern of the connection portion to the processed wiring pattern 4c is suppressed, and an integrated OK pattern is generated like the mask pattern 5c in FIG. on the other hand,
When the wiring pattern is not connected to the connection part, FIG.
As shown in FIG. 4G, the pattern length is shortened at that portion as shown in FIG. 4B, but as shown in FIG. 4H, the pattern is a connection pattern from the beginning, so that the product is affected as the mask pattern 5d. Never.

FIGS. 5A to 5H are explanatory views showing the correction of the interference portion by combining the difference patterns. FIGS. 5A to 5H show a difference pattern to be subtracted when the wiring pattern is connected to the connection portion. In addition, a plane pattern in a case where an interference pattern is removed by a differential pattern when there is a connection is shown.

As a modification of FIG. 4, when a cell and a wiring pattern overlap as shown in FIG. 5, by adding processing for synthesizing a pattern that cancels the OPC processing, errors in DRL can be avoided. it can. That is, in FIG. 5, the wiring pattern connection portion 11e is provided in the wiring connection portion connection pattern 10e of the cell pattern 1e as shown in FIG. 5A, and the OPC-processed cell pattern 2e as shown in FIG.
Even if the pattern portion 14e is generated normally,
A difference pattern 15 for subtraction processing is generated as shown in (c), the connection direction of the wiring pattern 3e is restricted as shown in (d), and the OPC-processed wiring pattern 4 as shown in (e).
Even if e is generated and becomes a combined pattern 16 as shown in (f), the difference pattern 15 for subtraction processing is subtracted as shown in (g), thereby causing interference as a mask pattern 5e as shown in (h). The portion can be corrected to be an OK pattern.

FIGS. 6A to 6G are explanatory diagrams showing the categorization of the interference area correction pattern. FIGS. 6A to 6G show OPC correction patterns based on terminal shapes when wiring is not allowed to bend.
(H) to (m) show the planar patterns of the OPC correction pattern depending on the terminal shape when the wiring is allowed to bend.

For example, the number of usable wiring layers is small,
When the cell pattern and the wiring pattern cannot be completely separated from each other, a stepwise OPC process can be performed by synthesizing a correction pattern on the interference portion as shown in FIG. As for the correction patterns, five types of correction patterns are selectively used for OPC correction of all terminal shapes, and interference cases are classified in advance into 7 types without M1 bend and 13 types with M1 bend. A pattern may be prepared, or a window may be set for an interference portion, and a new OPC process may be performed.

That is, in FIG. 6, when the bend is not permitted in the wiring, if the terminal is in the X direction at the wiring end point as shown in FIG. 6A, the terminal is in the Y direction at the wiring end point as shown in FIG. In the case of the upper and lower mirrors in (b) as in (c), and in the case where the terminal is at the bending point as in (d),
In the case of the upper and lower mirrors of (d) as in (e), when the terminal is on a wiring that penetrates in the Y direction as in (f),
This is an example where the terminal is located on a T-shaped wiring intersection as shown in FIG. On the other hand, when bend is permitted to the wiring, as shown in (h), the case of -90 degree rotation of (b), as shown in (i), and with the upper and lower mirrors of (b) +90 degree rotation as shown in (j), as shown in (j) In the case of the 90-degree rotation of (a), the case of the -90-degree rotation of (a) as in (k), the case of the upper and lower mirrors of (d) + 90-degree rotation as in (l), and the case of (m) -D of (d)
There is an example in the case of degree rotation.

When this processing is performed, ordinary AND, OR
By holding the data as a pattern for performing the subtraction processing as well as the processing, the processing at the time of the mask calculation is simplified. In addition, the speed can be increased by supporting arithmetic hardware that performs processing specialized for such arithmetic.

FIGS. 7A and 7B are explanatory diagrams showing the influence of adjacent cells. FIGS. 7A and 7B show the case where the shape of the OPC correction does not change, and FIGS. 7C and 7D show the case where the shape of the OPC correction changes. Are respectively shown.

When arranging patterns which have been subjected to the OPC processing in advance, if the density of the pattern changes depending on the shape of the adjacent cells and the shape of the OPC correction changes, it is necessary to correct the cell pattern. That is, as shown in FIG. 7, the cell (B) 18 as shown in FIG. 7A or the cell (C) 19 as shown in FIG.
Are arranged adjacently to the cell (A) 17 adjacent to the cell (B) 18 or the cell (C) 19, the shape of the OPC-processed cell (A1R (L)) pattern 20 shown in FIG. And (d) OPC-processed cells (A2R
(L)) If the pattern is staggered as in the pattern 21 and the difference is large enough to affect the product, the cell adjacent to the cell (A) 17 is the cell (B) 18 or the cell (C) 19. The OPC-processed cell (A1
R (L)) pattern 20 and the OPC-processed cell (A
2R (L)) patterns 21 are arranged separately. The cell pattern may be created for all of the neighboring cells, or the neighboring cell patterns may be classified and the cell patterns may be summarized for each classification group. After the cells are arranged, they may be newly generated by a program in parallel with performing the wiring processing (routing).

FIGS. 8A to 8D are explanatory diagrams showing adjacent cell correction sub-patterns. FIG. 8A to FIG. 8D show an example in which a cell (A) main pattern and a cell (A1R (L)) sub-pattern are added and subtracted.
When the PC-processed cell (A1R (L)) pattern is generated, (e) to (h) perform addition / subtraction processing of the cell (A) main pattern and the cell (A2R (L)) sub-pattern to perform OPC-processed cell ( A plane pattern when an A2R (L)) pattern is generated is shown.

As shown in FIG. 8, the OPC-processed cell (A1R (L)) pattern and the OPC-processed cell (A2
The (R (L)) pattern is not a pattern that replaces the main pattern as it is, but can also be processed by mask generation calculation by holding data as a sub-pattern of a difference from the main pattern. That is, in FIG.
Cell (B) on the right (left) of cell (A) 17a
When the cells 18a are arranged adjacent to each other, a cell (A1R (L)) sub-pattern (no pattern) 23 as shown in (c) is prepared for a cell (A) main pattern 22 as shown in FIG. Then, the OPC-processed cell (A1R (L)) pattern 20a as shown in (d) can be generated by addition and subtraction processing. On the other hand, when the cell (C) 19a is arranged adjacent to the right (left) of the cell (A) 17a as shown in (e), the cell (A) main pattern 22 as shown in (f) is used. On the other hand, cell (A2R (L)) sub-pattern 2 as shown in (g)
4 is prepared and subjected to addition / subtraction processing to generate an OPC-processed cell (A2R (L)) pattern 21a as shown in (h).

FIG. 9 is an explanatory diagram showing the addition of a dummy pattern for reducing the adjacent cell correction category.
(A) and (b) show the case where it is not necessary to add a dummy pattern.
(C) and (d) show plane patterns when a dummy pattern is added, respectively.

In contrast to the example of FIG. 8, for example, as shown in FIG. 9, by adding a pattern to the original data of the cell so as to reduce the influence of adjacent cells, the difference in density between adjacent cell patterns is reduced. It is also possible to reduce these categorizations. That is, the adjacent portions are all the same pattern like the cell (A) 17b and the cell (B) 18b in FIG. 9A, and the OPC-processed cell (A1R (L)) pattern 20b in FIG. If no pattern change occurs in any adjacent cell as described above, or if there is a pattern vacancy in the adjacent portion as shown in cell (A) 17b and cell (C) 19b in FIG. 25 are arranged so as to prevent the influence of the density from affecting the adjacent pattern like the OPC-processed cell (A1R (L)) pattern 20b in FIG. 9D. Accordingly, even when the cell (C) 19b is arranged adjacent to the right (left adjacent) of the cell (A) 17b, the OPC processing is performed in the same manner as when the cell (B) 18b is arranged adjacent. Cell (A1R
(L) The pattern 20b can be generated.

When there is a pattern shared by adjacent cells, such as a power supply pattern of a cell, an OPC process is performed by masking a region with the adjacent cell, and an effect is produced when the cell is connected to the adjacent cell. Not to be. Further, as described with reference to FIGS. 4 and 5, it is also possible to allow the sagging of the unconnected end point portion or to correct by calculation using a difference pattern.

As described above, by separating the OPC process in the portion of the cell pattern where the process margin becomes strict, even if the processing device is changed due to the change of the manufacturing line, the mask process of all the products can be performed on the entire chip OP.
It is also possible to cope with a device change by generating and replacing only the OPC processing pattern of the cell without performing the C processing.

Therefore, according to the mask data pattern generation method by the hierarchical OPC processing of the present embodiment, the product creation TAT is greatly reduced as compared with the case where the OPC processing is newly performed on all the mask data patterns. As a result, the cell pattern which is a common pattern is
Since the optimized OPC process can be performed without concern for T, the process margin is increased, and the cost can be reduced by improving the yield and the selling price can be improved by improving the product performance. In addition, miniaturized semiconductor products can be produced with a short TAT, and short-term delivery is possible.

That is, since the main components of the diffusion layer contact pattern and the lower wiring pattern, which are the masks at the initial stage of product production, are cell patterns, by registering the OPC-processed pattern in advance in the cell pattern, the OP
The time required for the C treatment is greatly reduced. Further, since a precise OPC operation can be performed on a cell pattern that can be prepared in advance, an optimized cell pattern can be prepared. Therefore, a margin for avoiding a combination of critical patterns at the time of exposure is increased, so that a large process margin can be obtained, which is an element for improving the yield. In addition, since a pattern close to the layout pattern at the time of design can be generated, the performance in simulation can be close to the performance of the actual product, so it is possible to reduce the margin and design up to the performance limit Becomes

Further, a cell pattern is prepared for each process such as a wiring material, a wiring film thickness, and an exposure device, and the cell pattern used when a process such as a wiring material, a wiring film thickness and an exposure device is changed, or when a production line is changed. By replacing the library, it is possible to respond to a new process specification without requiring OPC processing of a new cell pattern.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. It goes without saying that it is possible. For example, in the above-described embodiment, the case where the present invention is applied to an ASIC product such as a gate array has been described. However, the present invention can be widely applied to general miniaturized semiconductor products.

[0055]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) An OPC-processed pattern of a cell pattern commonly prepared for a product or an OPC processing operation pattern is held in the design layout data in advance, so that all the mask data patterns can be processed. The product creation TAT can be greatly reduced as compared with the case where a new OPC process is performed.

(2) According to the above (1), an optimized OPC process can be performed on a cell pattern which is a common pattern in advance without concern for the TAT, so that the process margin is increased and the cost due to the improvement of the yield is reduced. It is possible to improve the selling price by reducing and improving the product performance.

(3) According to the above (1), even a miniaturized semiconductor product can be manufactured with a short TAT.
Short-term delivery can be realized.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a mask data pattern generation method (hierarchical OPC processing) according to an embodiment of the present invention.

FIGS. 2A to 2I are explanatory diagrams showing interference between OPC patterns having different hierarchies in one embodiment of the present invention.

FIGS. 3A to 3D are explanatory diagrams showing a method (separation by layers) for ensuring the independence of the OPC pattern in one embodiment of the present invention.

FIGS. 4A to 4H are explanatory diagrams showing a case in which a cell pattern is devised so as not to cause a problem due to hierarchization in one embodiment of the present invention.

FIGS. 5A to 5H are explanatory diagrams showing correction of an interference portion by combining differential patterns in one embodiment of the present invention.

FIGS. 6 (a) to (m) are explanatory diagrams showing categorization of an interference area correction pattern in one embodiment of the present invention.

FIGS. 7A to 7D are explanatory diagrams showing the influence of an adjacent cell in one embodiment of the present invention.

FIGS. 8A to 8H are explanatory diagrams showing adjacent cell correction sub-patterns in one embodiment of the present invention.

FIGS. 9A to 9D are explanatory diagrams showing addition of a dummy pattern for reducing adjacent cell correction categorization in one embodiment of the present invention.

FIGS. 10 (a) and (b) show OP as a premise of the present invention.
It is explanatory drawing which shows C processing.

FIG. 11 is a flowchart showing a method of generating a mask data pattern by chip batch OPC processing as a premise of the present invention.

[Explanation of symbols]

1, 1b, 1c, 1e Cell pattern 2, 2b, 2c, 2e OPC-processed cell pattern 3, 3a, 3b, 3c, 3e Wiring pattern 4, 4a, 4b, 4c, 4e OPC-processed wiring pattern 5, 5a, 5b, 5c, 5d, 5e Mask pattern 6 Single pattern 7 OPC-processed single pattern 8 Interference part 9 Via pattern 10, 10e Wiring connection part connection pattern 11, 11e Wiring pattern connection part 12 OPC processing suppression area 13 No pattern part 14, 14e Patterned portion 15 Difference pattern 16 Composite pattern 17, 17a, 17b Cell (A) 18, 18a, 18b Cell (B) 19, 19a, 19b Cell (C) 20, 20a, 20b OPC-processed cell (A1R)
(L)) pattern 21, 21a OPC-processed cell (A2R (L)) pattern 22 cell (A) main pattern 23 cell (A1R (L)) sub-pattern 24 cell (A2R (L)) sub-pattern 25 dummy pattern 31 Design pattern 32 Mask pattern 33 Shortening 34 Drip 35 Dog bone 36 Serif 37 OPC processed pattern

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Kenji Hirao 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Within the semiconductor group of Hitachi, Ltd. (72) Inventor Toshiro Takahashi 6-16 Shinmachi, Omachi-shi Address 3 F-term in the Hitachi, Ltd. Device Development Center Co., Ltd. (Reference) 2H095 BB01 5B046 AA08 BA04 FA04 FA06 FA12 GA06 KA06 5F064 AA03 DD03 DD05 EE03 HH09 HH12

Claims (5)

[Claims] 1. A plurality of types of wiring layer layout patterns correspond to one type of product diffusion layer layout pattern;
A cell pattern prepared in common for a product is arranged in advance, and a wiring pattern connected between the arranged cells is generated to generate a product layout pattern.
What is claimed is: 1. A method of generating a mask data pattern of a product, wherein a layout pattern of said wiring layer is generated step by step, comprising:
A method of generating a mask data pattern, wherein a C-processed pattern or an OPC processing operation pattern is held in design layout data in advance. 2. An OPC process is performed on a cell pattern whose pattern does not change for each product before placement and routing.
Generating a C-processed cell pattern and registering it in a database; arranging the OPC-processed cell pattern registered in the database according to product placement information; and a wiring pattern created according to the product placement information. To generate an OPC-processed wiring pattern, and to generate an OPC-processed chip pattern by combining the OPC-processed cell pattern and the OPC-processed wiring pattern. And generating a mask using the OPC-processed chip pattern as a mask data pattern. 3. The method of generating a mask data pattern according to claim 2, wherein in the step of generating the OPC-processed chip pattern, the OPC-processed cell pattern and the OP are generated.
A method for generating a mask data pattern, comprising: when an interference occurs with a C-processed wiring pattern, arrange and correct an addition / subtraction pattern so that the interfering portion matches. 4. The method of generating a mask data pattern according to claim 2, wherein in the step of performing an OPC process on the cell pattern and the step of performing an OPC process on the wiring pattern, A detailed OPC process is performed by simulation, a simple OPC process is performed on the wiring pattern, and a non-uniform OP in the product logic is performed.
A method of generating a mask data pattern, comprising setting a C processing level. 5. The mask data pattern generation method according to claim 2, wherein in the step of arranging the OPC-processed cell pattern, the OPC-processed cell pattern is arranged when the OPC-processed cell pattern is arranged. A correction pattern of the OPC processing of the OPC-processed cell pattern is different depending on a type of a cell adjacent to the specified position.