JPH06110972A - Method for extracting circuit connection information from integrated circuit mask pattern - Google Patents

Abstract

PURPOSE:To provide a method capable of extracting desired circuit connection information in a short processing time by performing an efficient arithmetic operation. CONSTITUTION:Integrated circuit mask patterns are digitized and fetched as digital data (S1), a specific cell is specified on the integrated circuit mask pattern (S2), respective text names are imparted to the respective terminals of the specified cell for connecting to the outside of the cell so as to impart the same text name to the terminals to be at the some potential and at the same time, the position information of the respective terminals is extracted (S3). The circuit connection information is extracted with the mask pattern present in the outside of the specified cell and the respective terminals imparted with the text names as objects (S4) and the circuit connection information is corrected so as to secure mutually conducted connection relations for the plural terminals imparted with the same text name in the extracted circuit connection information (S5).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of extracting circuit connection information from an integrated circuit mask pattern, and more particularly to a method of fetching the circuit connection information by using a mask pattern as digital data.

[0002]

2. Description of the Related Art When designing an integrated circuit, first, a circuit diagram is created and an integrated circuit mask pattern is designed based on this circuit diagram. When a circuit expressed on this integrated circuit mask pattern is examined (for example, by collating with the original circuit diagram), a circuit connection indicating how each circuit element on the mask pattern has a connection relationship. Information needs to be extracted. The degree of integration of integrated circuits is increasing year by year, and it is very difficult to manually extract such circuit connection information. Therefore, the extraction work using a computer is usually performed.

Extraction processing of circuit connection information using a computer is performed in the following process. First, the designed integrated circuit mask pattern is digitized and taken into the computer as digital data (graphic data). When the mask pattern is defined with a hierarchical structure, the hierarchical information is expanded so that all the graphic patterns are expanded on the plane. Then, an operation for recognizing each circuit element is performed on the developed graphic pattern. For example, in a MOS integrated circuit, the graphic pattern obtained by performing an AND operation between the graphic pattern of the diffusion layer and the graphic pattern of the polysilicon layer can be recognized as the gate channel layer. After recognizing each circuit element by such a graphic operation, if the equipotential is recognized for each node, connection information between the circuit elements can be obtained. The recognition of the equipotential is performed by calculating the phase between the layers of the mask pattern. For example, if a contact hole pattern is present in the overlapping portion of two different conductive layers, it can be recognized that the two conductive layers are equipotential.

[0004]

Increasing the scale of integrated circuits,
Due to miniaturization, integrated circuit mask patterns have become very complicated. Therefore, in order to efficiently design the mask pattern, a hierarchical design method is adopted. In other words, the design is advanced from a simple combination to a more complicated one, and a higher level circuit is designed by converting a lower level circuit into a macro. For example, basic logic gates such as NOR gates and NAND gates are designed by combining lower level transistor elements, and units such as ALUs are designed by combining these logic gates. Further, by combining such units, a unit having a complicated function such as a microprocessor can be designed. Even for such a large-scale circuit, the data amount can be reduced by adopting a hierarchical representation.
The integrated circuit mask pattern designed by such a method has a hierarchical structure.

However, in the conventional circuit connection information extraction method for the integrated circuit mask pattern, as described above, after digitizing and capturing the mask pattern, all the hierarchical information is expanded and all the graphic patterns are expanded on the plane. Since the graphic calculation and the phase calculation are performed in this state, the processing time is extremely long. Further, the circuit connection information extracted is limited to the connection information about the lowest level hierarchy.

Therefore, an object of the present invention is to provide a method capable of extracting desired circuit connection information in a short processing time by performing efficient calculation.

[0007]

Means for Solving the Problems (1) The first invention of the present application is a method of extracting connection information about a circuit expressed as a mask pattern from an integrated circuit mask pattern by using a computer. The first step of digitizing the pattern to capture it as digital data, the second step of designating a specific cell on the integrated circuit mask pattern, and the equipotential for each terminal for connecting to the outside of the cell of the designated cell Make sure that the same text name is attached to the terminals that become
A third step of assigning the text name to each terminal and extracting the position information of each terminal, and extracting the circuit connection information for each terminal to which the mask pattern existing outside the designated cell and the text name are assigned The fourth stage,
In the extracted circuit connection information, for the plurality of terminals to which the same text name is given, the fifth step of correcting the circuit connection information so as to secure the connection relationship in which they are electrically connected to each other is performed. It is a thing.

(2) The second invention of the present application is the method according to the first invention, wherein in the fourth step, a mask pattern relating to the wiring passing through the inside of the designated cell is further extracted in the circuit connection information extracting process. It is intended to be the target.

(3) A third invention of the present application is the method according to each of the above-mentioned inventions, when a plurality of designated cells are adjacent to each other,
Based on the position information of each terminal, it is confirmed whether or not there is a terminal in contact with each other, and in the fifth step, for the terminals in contact with each other, the circuit connection information is ensured so that a mutually conductive connection relationship is secured. Is to be corrected.

[0010]

[Operation] In the method according to the present invention, a predetermined cell is designated by an operator before performing various arithmetic processes for extracting circuit connection information. The process of extracting the circuit connection information is performed only for the circuit outside the designated cell and not for the circuit inside the cell. However, a text name is given to the external connection terminal of the designated cell, and equipotential processing is performed based on this text name. Thus
As for the outside of the designated cell, the circuit connection information about the lowest level hierarchy is extracted as in the conventional method, but the circuit connection information about the inside of the designated cell is not extracted. In other words, the element-level connection information can be obtained outside the specified cell, but the specified cell remains in the form of a cell as it is, and the connection information in the state where the element and the cell are mixed can be extracted. . Therefore, it is possible to perform an efficient calculation only for a necessary portion, and it is possible to extract desired circuit connection information in a short processing time.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to illustrated embodiments. FIG. 1 is a diagram showing a procedure of a circuit connection information extracting method from an integrated circuit mask pattern according to an embodiment of the present invention. First, in step S1 of the first stage, a process of digitizing the integrated circuit mask pattern 1 and loading it as digital data into a computer is performed. The integrated circuit mask pattern 1 is designed based on the original circuit diagram, but since it is usually designed hierarchically,
The mask pattern also has a hierarchical structure. In the conventional method, with respect to the mask pattern input as digital data, the hierarchical structure is developed and all the graphic patterns in the lowest hierarchy are developed on one plane. It is not necessary to perform the process of expanding all the hierarchical structures in, and only the necessary parts are expanded as described later.

Here, for convenience of explanation, the following explanation will be given by taking a simple mask pattern as shown in FIG. 2 as an example. This mask pattern is designed with a hierarchical structure as shown in FIG. That is, the name of TOP is given to the whole circuit which is the highest layer,
A cell A and a cell B are defined in a layer below it, and a cell C and a cell D are further defined therebelow. The lower left black dot of each cell in FIG. 2 indicates the origin position of imposition of each cell on the upper layer. The spatial position of each cell on the mask pattern can be indicated by the coordinate value of the origin with respect to the cell in the upper layer. Specifically, the coordinate value indicating the imposition position as shown in FIG. 4 is defined.
With a mask pattern designed with a hierarchical structure, such a hierarchical structure of cells can be easily recognized.

Now, in step S2 of the second step, a desired cell is designated. The designation of this cell is performed based on the cell designation input from the operator. here,
The following description will be continued assuming that the operator has designated the cell A and the cell D, and the designated cells A and D will be referred to as "designated cells". Which cell to specify is determined based on the intention of the operator, but normally, a cell for which internal circuit connection information does not need to be extracted is specified. Specifically, a cell that has been used many times in the past and that has a high frequency of use and is guaranteed to have no problem in the circuit operation of that cell is specified. It will be decided. For such cells, it is not necessary to extract the circuit connection information again. When the cell designation is completed in this way, the hierarchical structure is expanded only outside the designated cell, and the hierarchical structure inside the designated cell is ignored. For example, cell A,
When D is specified, as shown in FIG. 5, the hierarchical structure is expanded only outside the specified cells A and D indicated by solid lines, and the hierarchical structure inside the specified cells A and D is ignored. As a result, cell B is expanded and cell C is ignored, and the hierarchical structure shown in FIG. 3 is changed to the structure shown in FIG. The expanded cell B is in the form included in TOP.

Then, in step S3 of the third step, a text name is given to each terminal for connecting to the outside of the designated cell, and the position information of each terminal is extracted.
This process will be explained with a concrete example. It is now assumed that the designated cells A and D designated in step S2 are cells having a structure as shown in FIGS. 7 (a) and 7 (b). The designated cell A includes a cell C of a lower hierarchy, has a wiring layer CW inside, and is connected to wiring layers W1 to W4 outside the cell. On the other hand, the designated cell D has two transistor elements TR inside and is connected to the wiring layers W5 and W6 outside the cell. Thus, the text name is given to each terminal for connecting to each wiring layer outside the cell. At this time, the same text name is given to the terminals that are equipotential. For example, as for the cell A, as shown in FIG. 7A, the terminal connected to the wiring layer W1 and the terminal connected to the wiring layer W2 are connected to each other by the wiring layer CW and thus have the same potential. Therefore, the same text name "a" is given to these terminals.
Thus, the four terminals of cell A are respectively a, a,
The text names b and c are given, and the two terminals of the cell D are given the text names a and b, respectively. At the same time, the position information about each of these terminals is extracted as coordinate values related to the origin of each cell (lower left point in this example). In this way, the result as shown in FIG. 8 is obtained. In the above example, the operator inputs the text name, but normally the text name of each terminal is added as a character code to the mask pattern. Are given the same text name. Therefore, if the text name added as a character code to this mask pattern is automatically fetched, the operator does not need to input the text name one by one.

In the next step S4 of the fourth step, the circuit connection information is extracted with respect to the mask pattern outside the designated cell. In the above example, the cells A and D are designated, so that the circuit connection information is extracted for the portions outside the designated cells A and D shown by hatching in FIG. The extraction process of the circuit connection information may use exactly the same method as the conventional method. Specifically, the calculation for recognizing each circuit element is performed. For example, in a MOS integrated circuit, the graphic pattern obtained by performing an AND operation between the graphic pattern of the diffusion layer and the graphic pattern of the polysilicon layer can be recognized as the gate channel layer. After recognizing each circuit element by such a graphic operation, if the equipotential is recognized for each node, connection information between the circuit elements can be obtained. The recognition of the equipotential is performed by calculating the phase between the layers of the mask pattern. For example, as shown in FIG. 10, wiring layers W1, W provided as two different graphic patterns
If the figure pattern CT of the contact hole exists in the overlapping region of the two, it can be recognized that the wiring layers W1 and W2 are equipotential.

As described above, the process of step S4 is exactly the same as the conventional circuit connection information extracting process, but the extraction target area is limited to the outside of the designated cell. The difference is. Specifically, the extraction process is performed with the mask pattern data inside the designated cells A and D in a masked state. In such an extraction process, the circuit connection information is not extracted for the inside of the designated cell, so that the circuit connection information is divided at the boundary portion corresponding to the contour of the designated cell. For example, as shown in FIG.
Since the connection relation regarding the elements inside the cell A for No. 1 cannot be obtained, the connection information of the wiring layer W1 is divided by the boundary line of this cell A. The same applies to the cell D shown in FIG. 11 (b). Therefore, for this divided portion, the connection relationship with each terminal of the cell is obtained based on the terminal position information extracted in step S3. That is,
As shown in FIG. 4, if the information regarding the imposition position coordinates of each cell is used, the absolute coordinates of the imposition position of each cell with respect to TOP, which is the highest layer, can be obtained. For example, the absolute coordinates of the imposition position on TOP for the designated cells A and D are as shown in FIG. After all, the terminal coordinates (coordinate values in the cell) of each terminal shown in FIG.
It is possible to convert to absolute coordinates for P. Therefore, for example, the terminals a, a, and
Since the absolute position coordinates of b and c can be obtained, the wiring layers W1 to W4
It can be recognized that the ends of are connected to the terminals a, a, b, c. Thus, for example, the wiring layer W1 is connected to the terminal a of the cell A, and the wiring layer W5 is connected to the terminal a of the cell D.
You will be able to obtain connection information such as that you are connected to.

By the way, a power supply wiring layer is generally provided in each cell constituting the integrated circuit. For example, the cell D'shown in FIG. 13 is obtained by further adding power supply wiring layers Vdd and Gnd to the cell D shown in FIG. 7B, and these power supply wiring layers respectively pass through the cell D '. It is arranged to do. Such a power supply wiring layer is a layer that has no meaning for the function of the cell D ′, but has an important meaning for a circuit outside the cell D ′. That is, in FIG. 13, the wiring layers W7, W8, W9, W1
If 0 is still divided at the boundary of the cell D ', correct circuit connection information cannot be obtained. Therefore, regarding such power supply wiring layers Vdd and Gnd, the cell D
Although it is the mask pattern inside the ‘′, it is convenient to set it as the target of the circuit connection information extraction processing in step S 4. Usually, such power supply wiring layers Vdd and Gn
Since d is given as a mask pattern arranged on the layer dedicated to the power supply wiring, it is easy to include it in the target of the circuit connection information extraction processing, distinguishing it from other mask patterns in the cell D ′. After all, as for the cell D ′, as shown in FIG. 14, the terminals a and b and the power supply wiring layer Vd are provided.
Only d and Gnd should be included in the target of the circuit connection information extraction processing. Generally, there are wiring layers other than the power wiring layer that simply pass through the inside of the cell. As described above, the wiring layer passing through the cell may be included in the circuit connection information extraction processing even if it is other than the power supply wiring layer. In this way, if the wiring layer that passes through the inside of the cell is included in the extraction processing target, when performing the equipotential processing,
In the example of No. 4, it is recognized that the wiring layers W7, Vdd, W8 are equipotential, and similarly, the wiring layers W9, Gnd, W10 are equipotential.

Finally, in step S5 of the fifth step, the circuit connection information obtained in step S4 is corrected.
That is, the terminals to which the same text name is assigned in the same designated cell are assumed to be equipotential, and correction is performed so that a mutually conductive connection relationship is obtained. For example, in FIG. 11, the connection information that both the wiring layers W1 and W2 are connected to the terminals to which the same text name a of the designated cell A is given can be obtained. In this case, since the wiring layers W1 and W2 are equipotential, these wiring layers are corrected to have a connection relationship in which they are electrically connected to each other.

Further, for example, as shown in FIG.
When the two designated cells X and Y are adjacent to each other, it is confirmed whether or not there are terminals contacting each other based on the absolute position coordinates of the terminals of each designated cell, and the terminals contacting each other are electrically connected to each other. In order to secure the connection
Make corrections to the circuit connection information. In the example of FIG. 15, the terminal a and the terminal d are in contact with each other on the boundary line Z between both cells. Therefore, the connection relationship in which the terminals a and d are conducted is ensured. As a result, the wiring layers W1, W3, W
The circuit connection information is corrected so that the connection relationships of 7 and W8 are conductive.

In this way, the final circuit connection information is obtained. This circuit connection information is, so to speak, information in which element level connection information and cell level connection information are mixed. That is, although the connection information at the element level is shown for the hatched circuit in FIG.
Regarding D, only the information that the cells A and D are present at this position and the information indicating the connection relationship between the external connection terminals of the cells A and D and the circuit of the hatched portion are shown. The element-level connection information of the circuits inside A and D is omitted. In this way, by omitting the extraction of the connection information for the cells A and D that do not require detailed internal information, an efficient extraction operation can be performed in a short time.

Although the present invention has been described based on the illustrated embodiment, the present invention is not limited to this embodiment. In particular, the above-described embodiment is for a very simple model for convenience of explanation, and the present invention is actually applied to a more complicated mask pattern.

[0022]

As described above, according to the present invention, in the circuit connection information extracting method from the integrated circuit mask pattern,
Since a predetermined cell is designated in advance and the circuit connection information extraction processing is performed only for the portion outside the designated cell, efficient calculation is performed to shorten the processing time.
It becomes possible to extract desired circuit connection information.

[Brief description of drawings]

FIG. 1 is a diagram showing a processing procedure of a circuit connection information extracting method from an integrated circuit mask pattern according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a specific mask pattern having a hierarchical structure used for explaining the procedure of FIG.

3 is a diagram showing a hierarchical structure of the mask pattern shown in FIG.

FIG. 4 is a table showing the imposition position of each cell in the mask pattern shown in FIG.

FIG. 5 is a diagram showing a state in which cells are designated for the mask pattern shown in FIG.

6 is a diagram showing a hierarchical structure after the cell designation shown in FIG.

FIG. 7 is a diagram showing an internal structure of designated cells A and D.

8 is a table showing an example in which data regarding external connection terminals is extracted for the designated cells A and D shown in FIG.

FIG. 9 is a diagram showing an external portion of cells A and D which are targets of circuit connection information extraction processing.

FIG. 10 is a diagram showing a method of recognizing equipotential in the circuit connection information extraction processing.

FIG. 11 is a diagram showing information left for designated cells A and D when performing circuit connection information extraction processing.

12 is a table showing the imposition positions of TOPs of designated cells A and D, which are obtained based on the table shown in FIG.

FIG. 13 is a diagram showing a cell D ′ having a power supply wiring layer passing therethrough.

FIG. 14 is a diagram showing information left when the circuit connection information extraction processing is performed on the cell D ′ shown in FIG. 13;

FIG. 15 is a diagram illustrating a process of recognizing adjacent terminals as equipotential when two adjacent designated cells exist.

[Explanation of symbols]

 1 ... Integrated circuit mask pattern A-D, X, Y ... Cell a-d ... External connection terminal W1-W10 ... Wiring layer CT ... Contact hole TR ... Transistor Vdd, Gnd ... Power supply wiring layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 21/82

Claims (3)

[Claims] 1. A method for extracting connection information about a circuit expressed as a mask pattern from an integrated circuit mask pattern by using a computer, wherein the integrated circuit mask pattern is digitized and captured as digital data. And a second step for designating a specific cell on the integrated circuit mask pattern, and for each terminal for connecting to the outside of the cell of the designated cell, the same text name is given to the terminal having the same potential. As described above, the third step of extracting the position information of each terminal while assigning a text name to each terminal, and the circuit for the terminals to which the mask pattern existing outside the specified cell and the text name are assigned The fourth step of extracting the connection information, and a plurality of circuits having the same text name in the extracted circuit connection information The terminal, the modifying the circuit connection information so that the connection relationship of continuity with each other is secured 5
The method for extracting circuit connection information from an integrated circuit mask pattern, comprising: 2. The extraction method according to claim 1, wherein in the fourth step, a mask pattern regarding a wiring passing through the inside of the designated cell is further targeted for the circuit connection information extraction processing. A method for extracting circuit connection information from a circuit mask pattern. 3. The extraction method according to claim 1, wherein when a plurality of designated cells are adjacent to each other, it is confirmed whether or not there are terminals that are in contact with each other based on position information of each terminal. In the step of 5, the circuit connection information is modified so that the terminals that are in contact with each other are corrected so as to ensure a connection relationship in which they are electrically connected to each other. .