JP2001358223A - Method of designing lsi circuit using hard blocks and method of restoring cell-placement information of hard blocks for lsi - Google Patents

Abstract

PROBLEM TO BE SOLVED: To design an LSI circuit using hard blocks without increasing chip size. SOLUTION: Hard-block cells 110 are used for the design by restoring cell- placement information inside a hard block, which is otherwise conventionally treated as a black box. Each transistor is recognized on a layout pattern of the hard block, and is collated with a transistor on a netlist in terms of coordinate values to recognize placement of each cell with each instance name. The power source lines and wiring originally contained in the hard block are not used. In designing a soft block 200, hard-block cells 110 are incorporated to design the total LSI circuit. By determining the placement of the soft-block cells 210 and the wiring for the hard-block cells 110 and for the soft-block cells 210 with an automatic placement and routing tool, it is possible to share the power-source lines 220 and to pass the chip wiring 300 within each block, and consequently it is possible to reduce the chip area.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an LSI circuit design method, and more particularly, to an LSI circuit design method in which hard blocks and soft blocks are mixed. Further, the present invention relates to a method for restoring cell arrangement information of LSI hard blocks necessary for designing such an LSI circuit.

[0002]

2. Description of the Related Art Today, LSIs are being incorporated into various devices, and it is expected that demands for a variety of LSI circuits will continue to grow. Such an LSI circuit is
Usually, it is designed by combining various cells prepared as components for performing a predetermined basic logical operation. As an LSI circuit design method, a cell having a desired function is selected from a cell library prepared in advance, a netlist showing a connection relation of these cells is created, and an automatic placement and routing tool is used. In general, a method of automatically generating the layout data indicating the geometric layout of each layer formed on the semiconductor substrate by automatically arranging and wiring the cells.
However, when designing an LSI circuit having a certain scale, a great deal of labor is required to design all circuits by combining cells in a cell library. For this reason, recently, a method of efficiently designing an LSI by preparing a logic circuit having a specific function as a hard block in advance and using the hard block as an existing component is becoming common. is there. Inside the hard block, a large number of cells performing a basic logic operation, a power supply line for supplying power to the cells, and wiring connecting between the cells and between the cells and the power supply line are pre-installed. I have. Therefore, the designer of the LSI circuit can omit the design of the circuit portion related to the specific function by using the hard block as a component having the specific function as it is.

[0003]

As described above, when an LSI circuit is designed using an existing hard block, labor is greatly reduced as compared with the case where the same functional block is designed by combining individual cells. The advantage that reduction can be obtained is obtained. However, when an LSI circuit is designed using a hard block by a conventional method, there is a problem that the size of the LSI chip must be increased. In general, when designing an LSI circuit according to individual demands, it is not enough to use only the logic functions of the existing hard blocks, and the designer himself / herself combines the cells while partially using the existing hard blocks. In this way, the target LSI is created by creating a soft block and mixing the hard block and the soft block.
You will be designing a circuit. However, since the hard block is treated as a so-called black box as a component having a specific logical function, it is not possible to design such that the chip wiring of the LSI circuit passes over the hard block. Therefore, the necessary chip wiring is
All the blocks need to be arranged so as to bypass the area of the hard block, and it becomes necessary to secure an extra wiring area around the hard block. Also, the power line is already built in the hard block, but the inside of the hard block is treated as a black box,
The power line in the hard block cannot be used to supply power to the soft block. Therefore,
It is necessary to provide a power supply line in the hard block and a power supply line in the soft block separately and independently, and it is necessary to secure an area for a useless power supply line which is originally unnecessary. For this reason, in the conventional method, an LSI circuit design is performed by mixing an existing cell set provided as a hard block and a cell set in a soft block created based on a designer's intention. In this case, there has been a problem that the size of the LSI chip increases.

Accordingly, an object of the present invention is to provide an LSI circuit design method capable of designing an LSI circuit using a hard block without increasing the size of an LSI chip. In order to achieve the object, an object of the present invention is to provide a method for restoring cell arrangement information of an LSI hard block.

[0005]

Means for Solving the Problems (1) The first aspect of the present invention relates to an existing cell set provided as a hard block and a cell set in a soft block created based on a designer's intention. , An LSI circuit design method using a hard block for designing an LSI circuit by mixing the cell arrangement information, wherein the cell arrangement information indicating the internal cell arrangement is restored for the hard block used for the design, and the restored cell arrangement information Designing a target LSI circuit using the hard block cells specified by the above and the soft block cells selected based on the intention of the designer; and a common power supply for the hard block cells and the soft block cells. A step of arranging lines and performing wiring between cells and wiring between each cell and a common power supply line.

(2) The second aspect of the present invention relates to the above-described first aspect.
In the LSI circuit designing method using the hard block according to the aspect, for the hard block cell, the cell arrangement based on the restored cell arrangement information is used as it is, and the wiring is performed by using the automatic arrangement and wiring tool, As for the cells, the cell arrangement is determined and the wiring is performed by using an automatic arrangement and wiring tool.

(3) The third aspect of the present invention is the above-described second aspect.
In the method for designing an LSI circuit using hard blocks according to the aspect of the present invention, a cell library showing the contents of individual cells used as hard block cells and soft block cells, and a netlist showing a connection relationship of these cells are provided. Then, the cell placement information restored for the hard block is given to the automatic placement and routing tool, and for the hard block cells, the cell placement is determined based on the restored cell placement information and the cell library and netlist information are Based on the information of the cell library and the netlist, the automatic placement and routing tool performs the placement and routing of the soft block cells.

(4) The fourth aspect of the present invention is the above-mentioned first aspect.
In the LSI circuit designing method using the hard blocks according to the first to third aspects, the cell library indicating the contents of each cell used as the hard block cell, and the hard block layout indicating the geometric layout in the hard block A data and a hard block netlist indicating a connection relation of each cell used as a hard block cell are prepared, and cell arrangement information on the hard block is restored based on the prepared data. The cell arrangement information for the cell corresponding to the above instance is obtained.

(5) According to a fifth aspect of the present invention, for a hard block in which a plurality of cells, power supply lines, and wirings are already incorporated, an LSI hard block for restoring cell arrangement information indicating an internal cell arrangement is provided. In the cell arrangement information restoring method, a cell library indicating the contents of individual cells used in the hard block, hard block layout data indicating a geometric layout in the hard block, and a cell library used in the hard block. A hard block netlist showing the connection relationship for each cell
And, based on the prepared cell library and the hard block layout data, determining individual cell areas.Based on the prepared hard block layout data and the hard block netlist,
The cell arrangement is searched by extracting the coordinates of the transistor in the cell and comparing the determined cell area with the extracted transistor coordinates, and the cell arrangement information on the hard block is stored in an instance on the hard block netlist. And restoring the information as information about the cell corresponding to.

(6) The sixth aspect of the present invention is the above-mentioned fifth aspect.
In the method for restoring cell arrangement information of an LSI hard block according to the aspect, when the step of determining individual cell areas is performed, a cell size is extracted from a cell library, and a cell position is extracted and extracted from hard block layout data. The cell area is determined based on the cell size and cell position thus determined.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on an embodiment shown in the drawings.

§1. Basic concept of the present invention First, an LSI using a hard block according to the present invention
The basic concept of the circuit design method is described. FIG. 1 is a plan view showing the internal configuration of a general hard block 100. As shown in the figure, the hard block 100 is composed of a hard block cell 110 composed of a group of a large number of cells C, a power supply line 120 composed of several conductive layers L, and inter-cell and inter-cell power supply lines 120. It is composed of wiring connecting between them. However, from the standpoint of a designer using such a hard block 100, it is sufficient that the hard block 100 can be used as a component having a function of performing a specific logical operation. It is not necessary to recognize each time. Therefore, the designer may treat the hard block 100 as a so-called black box. Normally, when designing LSI circuits according to individual demands, designers themselves create soft blocks by combining cells while partially using existing hard blocks, and mix hard blocks and soft blocks. In this way, a target LSI circuit is designed.

FIG. 2 shows an LS designed in this manner.
It is a top view of an I circuit. The portion shown with hatching in the figure is the hard block 100, which is treated here as a black box. Of course, the hard block 100 is provided with several input terminals and output terminals, and the designer can use the hard block 100 by connecting external wiring to these terminals. Become. On the other hand, on the right side of the hard block 100, a soft block 200 is arranged. The soft block 200 includes a soft block cell 210 composed of a group of a large number of cells C, a power supply line 220 composed of several conductive layers L, and a power supply line 220 between each cell.
And a wiring (not shown) for connecting between each cell and each cell.
Is the same as From the viewpoint of the basic configuration, the hard block 100 and the soft block 200 are substantially the same. The difference between the two is that the hard block 100
However, the soft block 200 is an off-the-shelf circuit block prepared in advance, whereas the soft block 200 is an order-made circuit block created based on the intention of the designer. Therefore, the designer can use the soft block 200
Needs to be designed by itself, but it is not necessary to be aware of the inside of the hard block 100, so the labor is greatly reduced compared to the case where all circuits are designed as soft blocks. The advantage is that it can be done.

However, as shown in FIG. 2, when the LSI circuit is designed by mixing the hard block 100 and the soft block 200, there is a problem that the chip area of the LSI increases. The first reason is that since the hard block 100 is treated as a so-called black box, it is not possible to design such that the chip wiring of the LSI circuit passes over the hard block. FIG. 2 shows a simple model in which one hard block 100 and one soft block 200 are arranged adjacent to each other. However, in an actual LSI circuit, a larger number of blocks will be arranged. Therefore,
In consideration of the wiring of the entire LSI circuit, a so-called chip wiring that crosses a specific block is required. Such a chip wiring can be arranged so as to pass through the soft block 200, but cannot pass through the hard block 100 treated as a black box. For this reason, as shown by the thick arrows in FIG. 2, the soft block 200 can be designed to pass through the chip wiring 300, but the hard block 100 can be designed to pass through the chip wiring 30.
Design must be made to bypass 0. As a result, when a hard block is used as compared with a case where all are designed as soft blocks, the chip area is increased only by a region for bypassing the chip wiring 300. The second reason is that power supply lines cannot be shared. As shown in FIG.
In 0, the power supply line 120 is already prepared. However, since the hard block 100 is treated as a black box, the power supply line 120 cannot be used to supply power for the soft block cell 210. Therefore, as shown in FIG. 2, a separate power supply line 220 must be provided in the soft block 200. Physically, the power supply line 120 and the power supply line 220 are arranged close to each other. Therefore, even if both can be shared, it is practically possible to perform such commonization. It is impossible to secure a region for useless power lines that are not originally required. This is,
This is the second reason for increasing the chip area.

The present invention has been made to solve such a conventional problem. The basic concept of the present invention is to restore the internal cell configuration of a hard block to be used and to change the cell arrangement of the hard block cells 110. The hard block cell 110 and the soft block cell 21
With respect to 0, the point is that the wiring is performed again. FIG.
Is a plan view of an LSI circuit designed based on such a basic concept. The configuration of the soft block 200 shown in the right half of the figure is the same as that of the conventional LSI circuit shown in FIG. 2, but is different from the hard block 100 shown in the left half of the figure. That is, in the conventional LSI circuit shown in FIG. 2, the hard block 100 as a black box is arranged, whereas in the LSI circuit according to the present invention shown in FIG.
Are extracted and arranged. As shown in FIG. 1, the original hard block 100 includes a power supply line 120 and wiring (wiring between cells or wiring between the power supply line 120 and each cell). Existing power line 1
20 and the wiring are all removed, and only the portion of the hard block cell 110 is used.

The hard block cell 110 shown in FIG.
Since the internal cell configuration has been restored, it is no longer necessary to handle as a black box, and handling equivalent to that of the soft block cell 210 is possible. Therefore, as shown in the plan view of FIG. 4, the chip wiring 300 can be similarly arranged on the soft block cell 210 and the hard block cell 110 so as to pass therethrough. Also, the wiring between the hard block cells 110 and the wiring between the power supply line and each cell are newly redone, so that
By using the power supply line 220 in 0 as a common power supply line, wiring for the hard block cell 110 can be performed together with wiring for the soft block cell 210. For this reason, the power supply line 120 originally included in the hard block 100 becomes unnecessary. Thus,
A region for bypassing the chip wiring 300 and a region for an extra power supply line, which are required in the conventional LSI circuit shown in FIG. 2, are not required in the LSI circuit of the present invention shown in FIG. An increase in chip area can be suppressed.

After all, the gist of the present invention is to design an LSI circuit by mixing an existing cell set provided as a hard block and a cell set in a soft block created based on a designer's intention. In this case, for the hard block 100 to be used, a process of restoring cell arrangement information indicating an internal cell arrangement is performed, and as shown in the example of FIG. 3, the hard block cell 110 identified by the restored cell arrangement information And the soft block cell 210 selected based on the intention of the designer,
An I-circuit is designed, and the hard block cell 110
In addition, a common power supply line 220 for the soft block cell 210 is arranged, and wiring between cells and wiring between each cell and the common power supply line 220 are performed. Normally, the work of arranging and wiring cells is performed using an automatic arrangement and wiring tool. Therefore, in practice, in the example shown in FIG.
As for (2), the cell placement is determined and the wiring is performed by using the automatic placement and routing tool. On the other hand, for the hard block cells 110, the cell arrangement based on the restored cell arrangement information is used as it is, and only the wiring uses the automatic arrangement and wiring tool.

§2. Used in specific embodiments of the invention
Next, a more specific embodiment of the present invention will be described with reference to the flowchart of FIG. As described above, in the present invention, it is necessary to perform a process of restoring cell arrangement information indicating an internal cell arrangement for a hard block used for LSI circuit design. In this specification, a method of the restoration processing will be described with reference to a specific example. First, as shown in the upper part of FIG. 5, for a hard block to be restored, a cell library CL and hard block layout data LD (hereinafter, when no misunderstanding occurs, simply referred to as layout data LD) And a hard block netlist NL (hereinafter, simply referred to as a netlist NL when no misunderstanding occurs). In the present invention, the cell arrangement information is restored using these data. Therefore, first, the contents of these data will be briefly described.

The cell library CL includes, for each cell, data indicating the cell name, cell size, input / output terminal name, input / output terminal position, and data indicating the internal structure. FIG. 6 shows a cell library C
FIG. 4 is a diagram showing a specific example of L, and FIGS. (A), (b) and (c) show the contents of each cell having cell names “Cell-1”, “Cell-2” and “Cell-3”, respectively; The data indicates FIG.
Although a cell library CL composed of three types of cells is shown for convenience of description, actually, data on a large number of cells is prepared as the cell library CL.
Actually, data indicating the internal structure of each cell is also included, but illustration is omitted here. In FIG. 6, for example, the description “CELL Cell-1” on the first line in the data shown in FIG. 6A is data on a cell whose cell name is “Cell-1”. The description “SIZE 60 100” in the second line indicates that the size of this cell is 60 × 100, and the description “PI 60
“N IN1 (20 40)” indicates that this cell has an input terminal “IN1” at the coordinate position (20 40).
The description “PIN IN2 (40 40)” on the line indicates that (40
40) indicates that the input terminal “IN2” exists at the coordinate position “50”, and the description “PIN OUT (50 40)” on the fifth line indicates that “OUT1” is at the coordinate position (50 40) in this cell. The description "END" on the sixth line indicates that there is an output terminal
This indicates that the description of this cell ends here. Similarly, the data shown in FIGS.
2 ”and“ Cell-3 ”.

FIGS. 7 (a), (b) and (c) show FIGS. 6 (a) and 6 (b).
FIG. 4 is a diagram showing images of three types of cells shown in FIGS. The coordinate value indicating the position of each terminal is a two-dimensional coordinate value when the origin is set at the lower left corner point. Here, a short diagonal line is given to the upper right corner, which is a diagonal of the origin, to indicate the direction of the cell. Each of these cells, for example,
It corresponds to a logic element that performs a basic logic operation such as a NAND gate or an inverter, and is usually used as a hard block cell forming a hard block and also used as a soft block cell forming a soft block. As described above, the hard block and the soft block are essentially the same circuit block, and the cell library CL provides a large number of cells commonly used for the design of the hard block and the design of the soft block. Will do.

The hard block layout data LD is:
This is data indicating a geometric layout in the hard block, and is composed of, for example, data as shown in FIG. Generally, LSI circuits are defined with a hierarchical structure. In the case of the example shown in FIG. 8 (only a part thereof is shown in FIG. 8), the description “STRUCTURETOP
Defines a top-level block “TOP”. The description on the second and subsequent lines is the top-level “TO
P "is a description indicating a second-layer block included in" P ".
For example, "Cell-1 (100,300) 180 FLIP" on the second line
Is described as one of the blocks in the second hierarchy, the cell with the cell name “Cell-1” is arranged at the position of the coordinates (100, 300), rotated by 180 °, and further turned upside down. Is shown. Similarly, the description in the third to fifth lines further describes three cells “Cell-2”, “Cell-1”, and “Cell-
No. 3 "(a total of four cells are used, but" Cell-1 "is used twice). The symbols indicating the cell rotation angle and the front / back inversion indicate eight arrangement patterns as shown in FIG. The description “TEXT TI1 (20,260)” on the sixth line indicates that a character string “TI1” (indicating an input / output terminal to the outside) should be placed at the position of coordinates (20,260). By including such a description, when the layout pattern is displayed on the display screen, the character index can be displayed together with the pattern. The description “WIRE (20,260) (120,260)” on the seventh line indicates the coordinates (20,
This indicates that wiring is arranged from (260) to coordinates (120,260). Hereinafter, similarly, a description for arranging a character string and a wiring follows, followed by a description (not shown in FIG. 8) regarding the arrangement of power supply lines and the like. When the description of the block “TOP” of the highest hierarchy is completed in this way, a description indicating the contents of each block of the second hierarchy (not illustrated in FIG. 8, but a description indicating a pattern in each cell) Will follow.

FIG. 10 shows the layout data L shown in FIG.
FIG. 9 is a diagram showing a layout pattern corresponding to D, showing an image of a block “TOP” in the highest hierarchy.
The four cells arranged near the center of the figure are cells in the cell library CL shown in FIG. 6 (cells shown in FIG. 7) and are arranged at predetermined positions in predetermined directions. The origin of the coordinate system of this block "TOP" is set at the lower left position as shown in the figure, and the arrangement of each cell is performed based on the coordinate values on this coordinate system. Power supply lines are arranged on both sides of the four cells, and wiring (black thick lines) is provided between cells and outside the cells. For reference, a circuit diagram of the block “TOP” is shown in FIG.

As described above, FIG. 8 shows only a portion of the hard block layout data LD indicating the configuration of the block "TOP" of the highest hierarchical level. The data LD contains the second
A description indicating the contents of the hierarchical block is also included. FIG.
2 is a diagram showing an image of a block “Cell-1” in the second hierarchy, showing an internal layout pattern of a cell “Cell-1” (each character shown in the figure is It is for convenience of explanation and is not actually displayed.) As a result, the layout data LD shown in FIG.
0 or a pattern shown in FIG. 12, which defines a geometric layout pattern in a hard block for each layer. By using this layout data LD, The plane figure of each area to be formed is determined.

The hard block netlist NL is data indicating a connection relation for each cell in the hard block, and is composed of, for example, data as shown in FIG. In this example, the netlist NL has four parts P
1 to P4, and the portion P1 has a circuit name "Cell
-A ", part P2 describes the circuit name" Cell-B ", part P3 describes the circuit name" Cell-C ", and part P4 describes the top-level circuit name" TOP ". . For example, ".subckt" in the first line of the portion P1
The description "Cell-A IN1 IN2 OUT1" indicates that the following description is a description relating to the cell having the cell name "Cell-A", and the cell has an input / output terminal "IN1 IN2 OUT1". This is a description that indicates that ".ends
The description “Cell-A” is a description indicating the end of the description of the cell having the cell name “Cell-A”. The second sandwiched between
The description in the fifth to fifth lines is a description of the transistors included in this cell, and indicates that this cell includes four transistors M1 to M4 (M1 to M4 are: Instance name of individual transistor).

Specifically, the second line “M1 VCC IN1 OUT
The description “1 VCC / P” describes the four terminals (source, gate, drain,
The order of the back gate, and so on) are connected to VCC (voltage power supply), IN1 (first input terminal of this cell), OUT1 (output terminal of this cell) and VCC, respectively, and this transistor is a PMOS transistor. It is shown that. Similarly, the description “M2VCC IN2 OUT1 VCC / P” on the third line indicates that the four terminals of the transistor having the instance name “M2” are VCC, IN2 (the second input terminal of this cell), OUT1, Connected to VCC and this transistor
This indicates that the transistor is an OS transistor. Also, the fourth
The description “M3 OUT1 IN1 net1 GND / N” on the line indicates that the four terminals of the transistor with the instance name “M3” are indicated by OUT1, IN1 and net1 respectively (“net1” of another transistor in this cell) Terminal: Specifically, it is connected to the source of the transistor having the instance name “M4”) and GND (ground power supply), indicating that this transistor is an NMOS transistor, and “M4 net1 IN” on the fifth line.
The description “2 GND GND / N” means that the four terminals of the transistor with the instance name “M4” are connected to net1 (the terminal indicated by “net1” of another transistor in this cell: specifically, the instance name “ M3 "), IN2 GND is connected to GND, indicating that this transistor is an NMOS transistor.

The parts P2 and P3 are similarly composed of descriptions showing the transistor configurations of "Cell-B" and "Cell-C". The part P4 is a description related to a circuit “TOP” of the highest hierarchy configured using these three cells. For example, “.subck” in the first row of the part P4
The description “t TOP TI1 TI2 TI3 TI4 TI5 TO1” indicates that the following description is a description related to the block named “TOP”, and this block includes the description “TI1 TI2
This is a description indicating that there is an input / output terminal “TI3 TI4 TI5 TO1”, and the description “.ends TOP” on the sixth line is a description indicating the end of the description of the block having the circuit name “TOP”. The description in the second to fifth rows interposed therebetween is a description of a cell included in this block, and it is shown that this block includes four cells X1 to X4. (X1 to X4 are instance names of individual cells).

Specifically, the second line “X1 TI1 TI2 net
The description “1 / Cell-A” indicates that each terminal of the cell having the instance name “X1” (input / output terminal enumerated in the first row of the portion P1) is TI1 (the first terminal of this block “TOP”). Input terminal), TI2 (second input terminal of this block "TOP"), net1 (terminal indicated by "net1" of another cell in this block: specifically, the cell of instance name "X3" 1st input terminal), and this cell is connected to the portion P
It is “Cell-A” defined in 1. Similarly, the third to fifth rows also show the configuration of each cell X2, X3, X4.

The cell library C shown in the upper part of FIG.
L, hard block layout data LD, and hard block netlist NL have been described based on specific examples. When a design using a hard block is performed in a conventional general LSI circuit design method, the data used in the actual design is the layout data LD among these data. As shown in FIG. 10 or FIG. 12, the layout data LD is data indicating a layout pattern defined with a hierarchical structure as a set of specific figures. If such data is prepared, it is formed on a semiconductor substrate. The specific pattern to be determined is determined. The designer who has received the provision of the hard block layout data LD can use the layout without knowing what each pattern means because the specific layout pattern has already been determined.

However, the layout data LD
Is data that is originally created based on the cell library CL and the hard block netlist NL.
Using the cells in L, the hard block netlist N
L, and the hard block layout data LD is obtained using the automatic placement and routing tool), and the hard library provider provides the cell library CL and the netlist NL together with the layout data LD. be able to. Therefore, in the present invention, as shown in the upper part of FIG. 5, a process of restoring the cell arrangement inside the hard block using the three pieces of information including the cell library CL, the hard block layout data LD, and the hard block netlist NL. Do. Hereinafter, the procedure will be described based on the flowchart of FIG.

§3. A cell according to a specific embodiment of the present invention.
Restore procedure Le arrangement First, in step S1 of FIG. 5, the cell library C
A process of extracting a cell size of a required cell from L is performed. In step S2, layout data L
A process of extracting a cell position from D is performed. Specifically, for example, from the cell library CL as shown in FIG. 6, the size of the cell “Cell-1” is 60 × 100, the size of the cell “Cell-2” is 40 × 100, and the size of the cell “Cell
With respect to “-3”, data having a size of 80 × 100 is extracted. From the layout data LD as shown in FIG. 8, the position (100, 300) of the cell “Cell-1” described in the second row,
The position of cell "Cell-2" described in the third row (140,10
0), the position of cell “Cell-3” described in the fourth row (160,
300), the position of cell “Cell-3” described in the fifth row (14
0,100) will be extracted. Thus, if the size and position of each cell arranged in the hard block can be extracted, the cell area occupied by each cell can be determined. Step S shown in FIG.
3 shows a process for determining the cell area in this manner. Here, each cell area is defined by the lower left coordinates (Xm
in, Ymin) and the upper right coordinates (Xmax, Ymax).
Will be obtained for four types of cells as shown in FIG. FIG. 15 is a plan view showing an image of the cell area determined in this way.

Subsequently, in step S4, a process of extracting the coordinates of the transistor in the cell based on the layout data LD and the netlist NL is performed. As described above, the layout data LD is shown in FIGS.
Since the data is a graphic pattern defined with a hierarchy as shown in FIG. 2, by performing a predetermined graphic operation,
The region where the transistor is formed can be recognized. For example, FIG. 12 shows an image of the block “Cell-1”. Here, an intersection region between the polysilicon layer shown by the broken line and the diffusion layer shown by the dashed line is This is a region of the MOS transistor. As shown in FIG. 10, the block “Cell-1” is arranged at a predetermined position in the block “TOP” in the upper hierarchy. This arrangement is based on the “Cell-1 (100,300) 180 FLIP
The block "Cell-1" shown in FIG. 12 is actually defined as shown in FIG.
After turning 180 °, turn the block `` T
It is arranged so that the upper left corner is located at the position of coordinates (100, 300) in "OP". In FIG. 16, a hatched rectangular area is an intersection area between the polysilicon layer shown by the broken line and the diffusion layer shown by the dashed line, that is, the MO area.
This is the region of the S transistor. Here, the lower left corner point of each transistor is defined as coordinates indicating the position of the transistor. Therefore, for the block "Cell-1", four transistor regions are recognized as shown, and four coordinate values are extracted.

Since the layout data LD is merely graphic pattern data, the layout data LD identifies what instance name of each transistor recognized as a crossing area of the graphic is called on the netlist NL. Can not be directly recognized from. Therefore, by comparing the layout data LD with the netlist NL, a process of checking the correspondence between each transistor recognized on the layout data LD and each transistor on the netlist NL is performed. This processing can be performed by tracing the wiring from the external terminal.
For example, an image of a block "TOP" as shown in FIG. 10 can be obtained from the layout data LD. Here, the pattern of the wiring and the conductive layer from the character string "TI1" indicating the external terminal is represented as a figure. As you follow,
It can be seen that they are connected to the transistor arranged at the coordinates (118, 220) and the transistor arranged at the coordinates (118, 270) shown in FIG. On the other hand, when the external terminal (signal name) “TI1” is searched for the netlist NL shown in FIG. 13, as described in the second row of the portion P4, the cell having the instance name “X1” (“Cell- A "), and further connected to" IN1 "of the portion P1. And finally, the part P1
As described in the second and fourth lines of the above, it can be seen that they are connected to the PMOS transistor having the instance name “M1” and the NMOS transistor having the instance name “M3”.

Thus, the netlist NL shown in FIG.
The transistor indicated by the instance name “X1-M1” above has the coordinates (11
8, 220), and the transistor indicated by the instance name “X1-M3” on the netlist NL shown in FIG. 13 is arranged at the coordinates (118, 270) in the layout pattern shown in FIG. It can be confirmed that this is a transistor. By a completely similar method, it can be confirmed that the transistor indicated by the instance name “X1-M2” on the netlist NL shown in FIG. 13 is a transistor arranged at the coordinates (135, 220) in the layout pattern shown in FIG. It can be confirmed that the transistor indicated by the instance name “X1-M4” on the netlist NL shown in FIG. 13 is a transistor arranged at the coordinates (135, 270) in the layout pattern shown in FIG. With such a method, a correspondence relationship as shown in FIG. 17 can be obtained as a result of the coordinate extraction process in step S4. That is, coordinate values can be obtained for each transistor indicated by the instance name.

The reason for obtaining the coordinate values for each transistor in the netlist NL in this way is to ensure consistency between the individual cells on the netlist NL and the individual cells on the layout pattern. In the embodiment shown here, as shown in FIG. 6, "Cell-1", "Cell-2", "Cell- A cell name including a numeral such as “3” is given, and in the netlist NL, FIG.
As shown in 3, “Cell-A”, “Cell-B”, “Cell-C”
Cell names containing alphabets such as
Of course, here, "Cell-1" = "Cell-A", "Cell
-2 "=" Cell-B "," Cell-3 "=" Cell-C ". However, since each cell is a basic logic element, many identical cells are usually used in the hard block, and each cell on the netlist NL and each cell on the layout pattern are usually used. Consistency with the cell is lost. For example, referring to the image of the cell area shown in FIG. 15, “Cell-1” is arranged on the left and right of the upper row, respectively. On the other hand, referring to the portion P4 of the netlist NL shown in FIG. 13, both the cell having the instance name “X1” in the second row and the cell having the instance name “X3” in the fourth row are both “Cell-A”. ". Therefore, if only the correspondence “Cell-1” = “Cell-A” is used, the instance name “X1” on the netlist NL is used.
Is the actual layout pattern, "Cell-1" arranged on the upper right of the row, or "Cell-" arranged on the left of the upper row
1 "cannot be recognized.

Therefore, in the present embodiment, a process for obtaining consistency between the two is performed using the coordinate values of the transistors. The cell arrangement search process in step S5 in the flowchart of FIG. 5 is a search process for ensuring such consistency. That is, in this cell arrangement search processing,
By comparing the cell area (FIG. 15) determined in step S3 with the transistor coordinates (FIG. 17) extracted in step S4, a cell arrangement is searched. FIG. 18 is a table showing the result of such a cell arrangement search. The left side of this table shows the coordinate values of each transistor shown in FIG. 17, and the right side shows the search results. For example, the first row of the table indicates that the coordinates of the transistor having the instance name “X1-M1” are (118,220). When the position indicated by the coordinates (118, 220) is searched on the image of the cell area shown in FIG. 15, “Ce
ll-1 ”. Similarly, FIG.
Also, when the coordinates of each transistor in the second to fourth rows of FIG. 8 are searched in the cell area shown in FIG. 15, after all, these transistors are all “Cell-1” in the upper left column shown in FIG. It can be seen that the transistor is located inside. From this, "Cell-1" in the upper left column shown in FIG.
Can be recognized as "Cell-A" of the instance name "X1" described in the second line of the portion P4 in FIG. Similarly, “Cell-2” in the lower left of FIG.
It can be recognized that “Cell-B” of the instance name “X2” described in the third row of the part P4 of No. 3 is “Cell-1” in the upper row shown in FIG. "Cell-A" of instance name "X3" described in the fourth line of part P4
Can be recognized, and “Cell-
It can be recognized that "3" is "Cell-C" of the instance name "X4" described in the fifth line of the portion P4 in FIG.

When the search for the cell arrangement is completed,
In step S6, the cell arrangement information PL is restored. That is, the cell arrangement information on the hard block is restored as information on the cell corresponding to the instance on the hard block netlist NL. FIG. 19 is a diagram showing the cell arrangement information PL thus restored. "PLACEMENT" on the first line
Is a character string declaring that this information is cell arrangement information, and “X1 Cell-A Cell-1 (100,300) 1
The description “80 FLIP” indicates that the cell (Cell-A) having the instance name “X1” on the netlist NL is a cell (Cell-A) arranged at the coordinates and directions “(100,300) 180 FLIP” on the actual layout. 1). Similarly, the third to fifth lines describe the arrangement of the cells having the instance names “X2”, “X3”, and “X4” on the netlist NL, and “END” in the sixth line is , This cell arrangement information P
This is a description indicating the end of L. Eventually, the cell arrangement information PL shown in FIG. 19 indicates a method of arranging some of the cells prepared in the cell library CL at specific coordinates in a specific direction and hard-coding each of these cells. This is information that has a one-to-one correspondence with the instance name in the block netlist NL.

§4. L according to a specific embodiment of the present invention
SI Circuit Design Method Now, with reference to the flowchart of FIG. 5, the cell arrangement information is restored for a specific hard block, and FIG.
The specific method for obtaining the cell arrangement information PL as shown in FIG. The gist of the present invention is to mix an existing cell set provided as a hard block and a cell set in a soft block created based on a designer's intention by mixing LS.
In designing an I-circuit, the cell arrangement of a hard block is restored, and wiring is performed between the hard block and the soft block using a common power supply line. Normal,
The work of cell placement and wiring is performed using an automatic placement and routing tool. Therefore, even when implementing the present invention, it is practically preferable to perform cell placement and wiring using an automatic placement and routing tool. At this time, regarding the soft block portion, the cell library CL and the “net list NL (ALL) of all circuits including the soft block” created by the designer of the soft block (the net list NL inside the hard block is not included) ) Is given to the automatic placement and routing tool so that both the soft block cell placement and the routing are performed. However, since the cell placement has already been completed for the hard block part (the restored cell The placement is determined by the placement information PL), and the cell library CL and the hard block netlist NL are provided to the automatic placement and routing tool so that only the hard block cells are routed.

The automatic placement and routing process in step S7 in FIG. 5 is a placement and routing process using an automatic placement and routing tool. The automatic placement and routing tool includes a cell library CL shown in FIG. 5 (as described above, both hard blocks and soft blocks are designed using cells in the common cell library CL) and a hard block netlist NL. And the restored cell arrangement information PL and the "netlist NL (ALL) of all circuits including soft blocks" created by the designer of the target LSI circuit. Accordingly, the automatic placement and routing tool determines the cell arrangement based on the cell arrangement information PL for the hard block cells, performs the wiring based on the information of the cell library CL and the netlist NL, and performs the wiring for the soft block cells. And the wiring are performed based on the information of the cell library CL and the netlist NL (ALL). From the existing hard block, only the portion of the hard block cell is used, and the power supply line provided for the soft block is used. At this time, the wiring for the hard block cells is redone together with the wiring for the soft block cells, so that the same power supply line can be shared by both. In addition, since the chip wiring 300 can pass through both the soft block cell part and the hard block cell part, it is not necessary to bypass the chip wiring 300.

After all, when designing an LSI circuit using the hard block 100 having the internal structure shown in FIG. 1, conventionally, this is treated as a black box, and as shown in FIG. 100 had to be taken into the LSI circuit as it was. However, in the design method according to the present invention, the hard block 100 shown in FIG.
Is restored as the cell arrangement information PL,
As shown in FIG. 3, only the hard block cell 110 can be used for LSI circuit design. That is, the power supply line 120 originally incorporated in the hard block 100 and various wirings are not used. As shown in FIG. 3, when the circuit designer arranges the power supply line 220 at the stage of designing the soft block 200, the power supply wiring for both blocks can be performed using the power supply line 220 as a common power supply. Further, by performing inter-cell wiring for both blocks, as shown in FIG. 4, the chip wiring 300 can be arranged to pass over each block.

Note that each processing procedure shown in FIG. 5 is actually executed by a dedicated tool composed of a computer program. Therefore, in implementing the present invention, the work load of the circuit designer does not increase. First, the circuit designer obtains the cell library CL, the layout data LD and the netlist NL for the hard block to be used, and performs an operation of providing these to the dedicated tool. Then, with this special tool,
Are performed, and the cell arrangement information PL indicating the arrangement of the hard block cells 110 is automatically created (restored). As described above, the cell arrangement information PL indicates an arrangement of cells corresponding to an instance on the hard block netlist NL, for example, as shown in FIG. That is,
This means that the information indicating the arrangement of the hard block cells 110 has been obtained in a format compatible with the hard block netlist NL. The circuit designer incorporates the hard block cell 110 as a part and designs the entire LSI circuit including the soft block. Specifically, a netlist NL (ALL) of all the circuits including the soft blocks is created with reference to the cell library CL. When the cell library CL, the hard block netlist NL, the restored cell placement information PL, and the netlist NL (ALL) of all circuits including the soft blocks are given to the automatic placement and routing tool, the automatic placement of the soft block cells is performed. Is performed, and wiring for all cells is executed.

[0041]

As described above, according to the LSI circuit designing method using the hard block according to the present invention, the cell position information of the hard block is restored, and then the hard block cell and the soft block cell are reconnected. Since the power supply line can be shared and the chip wiring can be passed over the hard block, it is possible to increase the size of the hard block without increasing the LSI chip size. LSI using
It becomes possible to design a circuit.

[Brief description of the drawings]

FIG. 1 is a plan view showing an internal configuration of a general hard block 100. FIG.

FIG. 2 is a plan view of an LSI circuit designed using the hard block 100 shown in FIG.

FIG. 3 is an LSI designed based on the basic concept of the present invention.
It is a top view of a circuit.

4 is a chip wiring 30 in the LSI circuit shown in FIG.
It is a top view which shows arrangement | positioning of 0.

FIG. 5 is a flowchart showing a procedure according to a specific embodiment of the present invention.

FIG. 6 is a diagram showing a specific configuration example of a cell library CL.

FIG. 7 is a diagram showing an image of each cell in a cell library CL shown in FIG. 6;

FIG. 8 is a diagram showing a specific configuration example of hard block layout data LD.

FIG. 9 is a plan view showing a direction in which cells are arranged.

FIG. 10 is a plan view showing a layout pattern of a block “TOP” of the highest hierarchy in the layout data LD shown in FIG. 8;

11 is a circuit diagram of a block “TOP” shown in FIG.

12 is a plan view showing a layout pattern of a block “Cell-1” in a lower hierarchy of the block “TOP” shown in FIG. 11;

FIG. 13 is a diagram illustrating a specific configuration example of a hard block netlist NL.

14 is a diagram showing an example of data corresponding to the cell area determined in step S3 in the flowchart of FIG.

FIG. 15 is a plan view showing an image of a cell area corresponding to the data shown in FIG. 14;

16 is a plan view of a layout pattern of one cell for explaining the principle of the transistor coordinate extraction process in step S4 in the flowchart of FIG. 5;

FIG. 17 is a diagram showing a specific example of intra-cell transistor coordinates extracted based on the principle shown in FIG. 16;

FIG. 18 is a diagram showing a result of a cell arrangement search process in step S5 in the flowchart of FIG. 5;

19 is a diagram showing a specific configuration example of cell arrangement information PL obtained by the cell arrangement information restoring process in step S6 in the flowchart of FIG. 5;

[Explanation of symbols]

100 hard block 110 hard block cell 120 power line 200 soft block 210 soft block cell 220 power line 300 chip wiring C cell CL cell library Cell-1 to Cell-3, Cell-A to Cell -C: cell name L: conductive layer LD: hard block layout data M1 to M6: transistor instance name NL: hard block netlist NL (ALL): netlist of all circuits including soft blocks P1 to P4: netlist ... PL... Cell arrangement information S1 to S6... Each step of the flow chart X1 to X4.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/04 DU

Claims (6)

[Claims] 1. A method for designing an LSI circuit by mixing an existing cell set provided as a hard block and a cell set in a soft block created based on a designer's intention, comprising: Restoring cell arrangement information indicating an internal cell arrangement for a hard block used for hard block cells, a hard block cell specified by the restored cell arrangement information, and a soft block cell selected based on a designer's intention. And designing a target LSI circuit using: and arranging a common power supply line for the hard block cell and the soft block cell, and wiring between the cells and connecting each cell to the common power supply line. LS using a hard block, comprising the steps of:
I-circuit design method. 2. The LSI circuit design method according to claim 1, wherein for the hard block cells, the cell arrangement based on the restored cell arrangement information is used as it is, and wiring is performed using an automatic arrangement and wiring tool. An LSI circuit design method for a soft block cell, wherein the cell arrangement is determined and wired using an automatic placement and routing tool. 3. The LSI circuit design method according to claim 2, wherein a cell library indicating the contents of each cell used as a hard block cell and a soft block cell, and a net indicating a connection relationship between these cells. The list and the cell placement information restored for the hard block are provided to the automatic placement and routing tool. For the hard block cell, the cell placement is determined based on the placement information, and the information of the cell library and the netlist is determined. Based on the information of the cell library and the netlist, the soft placement and routing are performed by the automatic placement and routing tool. LSI circuit design method. 4. The LSI according to claim 1,
In the circuit design method, a cell library indicating the contents of each cell used as a hard block cell, hard block layout data indicating a geometric layout in the hard block, and each cell used as a hard block cell A hard block netlist indicating the connection relation of the cells, and restoring the cell arrangement information about the hard blocks based on these; and a cell for the cell corresponding to the instance on the hard block netlist. An LSI circuit design method using hard blocks, wherein placement information is obtained. 5. A method for restoring cell arrangement information indicating an internal cell arrangement for a hard block in which a plurality of cells, power supply lines, and wirings have already been incorporated, comprising: A cell library indicating the contents of the cell, hard block layout data indicating a geometric layout in the hard block,
A step of preparing a hard block netlist indicating a connection relation for each cell used in the hard block; and a step of determining individual cell areas based on the cell library and the hard block layout data. Extracting the coordinates of the transistor in the cell based on the hard block layout data and the hard block netlist; and searching for the cell arrangement by comparing the cell area with the transistor coordinates. Restoring cell arrangement information on a block as information on a cell corresponding to an instance on the hard block netlist; and restoring a cell arrangement information of an LSI hard block. 6. The cell arrangement information restoring method according to claim 5, wherein, when the step of determining individual cell areas is performed, a cell size is extracted from a cell library and a cell position is extracted from hard block layout data. And a cell arrangement information restoring method for an LSI hard block, wherein a cell area is determined based on the extracted cell size and cell position.