JPH0582640A - Forming method for layout data - Google Patents

Abstract

PURPOSE:To diminish a time to form layout data for a semiconductor integrated circuit. CONSTITUTION:A substrate-contact forming region 17 is formed in the following way. A well forming region 10 is diminished while each MOS transistor forming region 11 is enlarged, and then a primary most expected region 16 is formed by subtracting each MOS transistor forming region 11A from the diminished well forming region 10A. Then, a second most expected region 16A is formed by enlarging the primary expected region 16, and a tertiary most expected region 16B is figured out from a duplicated space of the secondary expected region 16A and a power supply wiring region 14. Lastly the substrate-contact forming region 17 can be formed by reducing the tertiary most expected region 16B to a size corresponding to a substrate contact hole.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of creating layout data of a semiconductor integrated circuit, and more particularly to a method of creating layout data of MOSLSI.

In recent years, with the diversification of MOSLSIs and the expansion of scale, efficient creation of layout data is important for achieving short-term delivery of products.

[0003]

2. Description of the Related Art Conventionally, in a MOS LSI, when creating layout data of a MOS transistor formed on a substrate, well data, diffusion data forming a transistor, and gate layer data of a gate layer are created and M
Create a layout of OS transistors. Then, based on the layout of this MOS transistor,
The contact data of the contact hole for the transistor, the substrate contact data of the substrate contact for the substrate for the back gate electrode, and the wiring / signal line data of the power supply wiring and the signal wiring are sequentially created.

[0004]

However, when creating the data for each layout, it is necessary to create the data while confirming the mutual design rules, which takes a very long time. Especially, in the layout creation work of the board contact data performed in the latter half, it is very troublesome and time consuming because it is necessary to search for an empty space for arranging the board contacts in a complicated state of each layout. It was

The present invention has been made to solve the above problems, and its purpose is to reduce the complexity of layout work of a MOS LSI and reduce the layout data creation time. It is to provide a method for creating layout data of a circuit device.

[0006]

In order to solve the above problems, the present invention designates a well forming region, a plurality of MOS transistor forming regions and a gate layer forming region formed in the well forming region, and designates a MOS transistor. Create layout data for. On the other hand, wiring layout data is created by designating a contact hole formation region, a signal wiring formation region, and a power supply wiring formation region passing over each MOS transistor formation region for the layout of the MOS transistors.

Next, the well forming region is reduced to obtain a reduced well forming region, and each MOS transistor forming region is enlarged to obtain an enlarged MOS transistor forming region. Then, after obtaining the remaining region after removing each enlarged MOS transistor formation region from the reduced well formation region, the region is enlarged, and a region where the enlarged region and the power supply wiring formation region overlap is obtained. Then, the overlapping region is reduced to a size that matches the size of the substrate contact hole and is determined as a substrate contact formation region for the back gate electrode.

[0008]

Therefore, according to the present invention, the substrate contact forming region for the back gate electrode can be obtained by using the layout data of the well forming region, each MOS transistor forming region and the power supply wiring forming region which have been designated previously. it can. As a result, it is not necessary to individually specify the substrate contact formation region to create layout data.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment embodying the present invention will now be described with reference to FIGS.
It will be described with reference to FIG. For convenience of explanation, the data creation of the layout of the completed MOSLSI shown in FIG. 1 will be described.

On the semiconductor substrate, as shown in FIG. 2, first, a region 10 (well forming region) of a P layer or an N layer is designated to create well data. Next, diffusion layer layout data is created by designating a plurality of MOS transistor formation regions 11 formed within the well formation region 10 defined by the well data. When the MOS transistor forming region 11 is formed by creating the diffusion layer data, the gate layer layout data is created by designating the gate layer forming region 12 formed of polysilicon.
At this point, the layout of each MOS transistor is created.

Next, contact data is created by designating the contact hole forming region 13 for each MOS transistor. Subsequently, signal line data for designating the power supply wiring formation region 14 passing over each MOS transistor formation region 11 is created, and at the same time, the signal wiring formation region 15 is formed.
Specify to create signal line data. The wiring layout of the contact hole formation area 13, the power supply wiring formation area 14, and the signal wiring formation area 15 is treated as a layout different from the layout of the MOS transistors and is created as separate data.

Next, a substrate contact data creation process for determining the substrate contact formation region 17 for the back gate electrode shown in FIG. 1 is performed. First, the well formation region 1
Using the well data of 0, the formation region 10 is reduced by a predetermined amount (micron order), and the data of the reduced well formation region 10A shown in FIG. 3 is created. Subsequently, the diffusion layer layout data of the MOS transistor formation region 11 is used to enlarge the formation region 11 by a predetermined amount (on the order of microns) to create data of the enlarged transistor formation region 11A shown in FIG. This reduction and enlargement is within the well formation region 10 and it is judged whether or not there is a space where the substrate contact formation region 17 for the back gate electrode can be formed between the MOS transistor formation regions 11, and the space that cannot be formed is eliminated. This is what you do to do it. Then, the amount of reducing the well formation region 10 is set in the well formation region 10 by the substrate contact formation region 1
7 is set to a value within a range for specifying the position where it can be formed. Further, the amount of enlargement of each MOS transistor formation region 11 is set to such a value that the spaces in which the substrate contact formation regions 17 cannot be arranged in the respective spaces between the MOS transistor formation regions 11 overlap each other by enlarging them. Then, in the layout formed by the reduced well formation region 10A and the enlarged transistor formation region 11A, a region obtained by removing the enlarged transistor formation region 11A from the reduced well formation region 10A is defined as a primary candidate region 16.

Next, as shown in FIG. 4, the primary candidate area 16 is enlarged by a predetermined amount to form a secondary candidate area 16A. That is, the width direction of the primary candidate region 16 is expanded so as to coincide with the interval between the MOS transistor formation regions 11, and the length direction is expanded so as to coincide with the longitudinal length of the well formation region 10. Subsequently, the secondary candidate area 16A and the power supply wiring formation area 14 are combined. Then, the overlapping portion is set as the tertiary candidate area 16B.

As shown in FIG. 5, this tertiary candidate area 16B
Is reduced by a predetermined amount (to match the size of the substrate contact hole), and the region obtained by the reduction is used as the substrate contact formation region 17 for the back gate electrode. Then, in order to make the substrate contact formation region 17 and the contact hole formation region 13 have the same dimensional layout data, the data designating the substrate contact formation region 17 is set to the contact hole formation region 13 for the MOS transistor previously created. Combine with specified contact data.

When the substrate contact forming area 17 and the contact hole forming area 13 are combined with the data for designating them, the creation of the MOS LSI layout data is completed. Then, a series of substrate contact data creation processing for determining the substrate contact formation region 17 for the back gate electrode can be automatically obtained and created by the CAD device.

As described above, according to the present embodiment, the substrate contact formation region 1 for the back gate electrode is formed only by processing the layout data of the well formation region 10, the MOS transistor formation region 11 and the power supply wiring formation region 14 which have been set previously.
Data specifying 7 can be created. Moreover,
Since this series of processes can be easily executed by the CAD device, the substrate contact forming region 1 as in the conventional case can be obtained.
There is no need to search for an empty space for arranging 7, and the labor for creating layout data can be reduced, and
Creation time can be shortened.

[0017]

As described above in detail, according to the present invention, M
There is an excellent effect that the complexity of the layout work of the OSLSI can be reduced and the layout data creation time can be shortened.

[Brief description of drawings]

FIG. 1 is a completed layout diagram of a MOS LSI showing an embodiment of the present invention.

FIG. 2 is a layout diagram of a MOS LSI excluding a substrate contact formation region.

FIG. 3 is a layout diagram of a reduced well formation region and an enlarged transistor formation region.

FIG. 4 is a layout diagram of a secondary candidate area and a power supply wiring forming area.

FIG. 5 is a layout diagram showing a relationship among a secondary candidate region, a power supply wiring formation region, and a substrate contact formation region.

[Explanation of symbols]

 10 Well Forming Region 10A Reduced Well Forming Region 11 MOS Transistor Region 12 Gate Layer Forming Region 13 Contact Hole Forming Region 15 Signal Wiring Forming Region 16 Remaining Forming Region 16A Enlarged Region 16B Overlapping Region 17 Substrate Contact Forming Region

Claims (1)

[Claims] 1. Layout data of a MOS transistor by designating a well formation region (10), a plurality of MOS transistor formation regions (11) and a gate layer formation region (12) formed in the well formation region (10). And a substrate contact formation region (17) for the back gate electrode, a contact hole formation region (13) for the MOS transistor, and a signal wiring formation region (1
5) and each MOS transistor formation region (11)
A layout data creating method for creating wiring layout data by designating a power supply wiring formation region (14) passing above, wherein the substrate contact formation region (17) is reduced in size and the well formation region (10) is reduced. Each MOS transistor formation region (11) is enlarged, and the remaining formation region (16) obtained by removing each enlargement MOS transistor formation region (11A) from the reduced well formation region (10A) is obtained, and then the region (16) is determined. The enlarged area (16A) and the power supply wiring formation area (1
4) A layout data creating method, characterized in that an area (16B) overlapping with (4) is obtained, and then the area (16B) overlapping is reduced to a size that matches the size of the substrate contact hole.