JPH06138643A - Glass mask for semiconductor device and its production - Google Patents
Glass mask for semiconductor device and its productionInfo
- Publication number
- JPH06138643A JPH06138643A JP29307492A JP29307492A JPH06138643A JP H06138643 A JPH06138643 A JP H06138643A JP 29307492 A JP29307492 A JP 29307492A JP 29307492 A JP29307492 A JP 29307492A JP H06138643 A JPH06138643 A JP H06138643A
- Authority
- JP
- Japan
- Prior art keywords
- mask
- pattern
- width
- chip
- glass
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 59
- 239000011521 glass Substances 0.000 title claims abstract description 51
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims description 23
- 238000005530 etching Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 4
- 238000001459 lithography Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 101100269850 Caenorhabditis elegans mask-1 gene Proteins 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 238000000638 solvent extraction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置用ガラスマス
クおよびその製造方法に係り、とりわけ半導体チップに
回路パターンを精度良く形成することができる半導体装
置用ガラスマスクおよびその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a glass mask for a semiconductor device and a method for manufacturing the same, and more particularly to a glass mask for a semiconductor device for forming a circuit pattern on a semiconductor chip with high accuracy and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】従来、リソグラフィー工程によって半導
体ウェハ上にレジストパターンを転写し、このレジスト
パターンを保護膜としてエッチング工程を行なうことに
よって半導体ウェハ上に回路パターンが形成される。そ
して、この半導体ウェハから半導体チップが作成され
る。リソグラフィ工程においては、半導体ウェハ上方に
半導体装置用ガラスマスクが配置され、必要な露光処理
が行なわれる。2. Description of the Related Art Conventionally, a circuit pattern is formed on a semiconductor wafer by transferring a resist pattern onto a semiconductor wafer by a lithography process and performing an etching process using the resist pattern as a protective film. Then, a semiconductor chip is created from this semiconductor wafer. In a lithography process, a glass mask for a semiconductor device is arranged above a semiconductor wafer and a necessary exposure process is performed.
【０００３】このようなガラスマスクは、一般にガラス
基板と、このガラス基板上に設けられたマスクパターン
とからなり、マスクパターンは回路パターンに対応した
形状となっている。すなわち、マスクパターンの幅等の
形状は、回路パターンの形状に合わせて形成される。Such a glass mask generally comprises a glass substrate and a mask pattern provided on the glass substrate, and the mask pattern has a shape corresponding to the circuit pattern. That is, the shape such as the width of the mask pattern is formed according to the shape of the circuit pattern.
【０００４】他方、大規模集積回路（ＬＳＩ）の半導体
チップは、一つのチップ内に大容量メモリ等のパターン
密度の大きい領域と、小さいロジック部等のパターン密
度の比較的小さい領域と、これらの領域を連結するきわ
めて密度の小さい領域とを有している。このように異な
る密度の複数の領域を有している半導体チップを作成す
る際も、マスクパターンの形状は、回路パターンの形状
に対応している。On the other hand, in a semiconductor chip of a large scale integrated circuit (LSI), an area having a large pattern density such as a large capacity memory and an area having a relatively small pattern density such as a small logic portion are formed in one chip. And regions of very low density that connect the regions. Even when a semiconductor chip having a plurality of regions having different densities is formed in this way, the shape of the mask pattern corresponds to the shape of the circuit pattern.
【０００５】[0005]
【発明が解決しようとする課題】上述のように、従来、
回路パターンの局所的密度（パターン占有率）を考慮せ
ずに、回路パターンの形状どおりにガラスマスクを作製
している。そして、このガラスマスクを用いてリソグラ
フィー工程を経て半導体ウェハ上にレジストパターンを
転写し、このレジストパターンを保護膜としてエッチン
グ工程を行なっているが、この場合次のような問題が生
じる。As described above, as described above,
The glass mask is manufactured according to the shape of the circuit pattern without considering the local density (pattern occupancy) of the circuit pattern. Then, a resist pattern is transferred onto a semiconductor wafer through a lithography process using this glass mask, and an etching process is performed using this resist pattern as a protective film, but in this case, the following problems occur.
【０００６】図４は、回路パターンのパターン密度と、
各密度における回路パターンの設計値と仕上り値の差で
ある。図４からわかるように、パターン密度により仕上
げ値と設計値との差が変化する。すなわち、パターン密
度が約２０％の領域では、設計値どおり回路パターンが
形成されるがパターン密度が約３％と低い領域では、設
計値よりも回路パターンの仕上り値が太くなる。FIG. 4 shows the pattern density of the circuit pattern,
It is the difference between the design value and the finished value of the circuit pattern at each density. As can be seen from FIG. 4, the difference between the finish value and the design value changes depending on the pattern density. That is, in the area where the pattern density is about 20%, the circuit pattern is formed according to the design value, but in the area where the pattern density is low, about 3%, the finished value of the circuit pattern becomes thicker than the designed value.
【０００７】これは、単位面積当り等量のエッチングガ
スが供給されても、その単位エッチングガス量当りのエ
ッチングすべき材料の量が異なるからである。例えばパ
ターン密度２０％の場合、エッチングすべき材料は８０
％となり、パターン密度３％の場合、エッチングすべき
材料は９７％となる。このためパターン密度３％の場
合、パターン密度２０％の場合と比べて単位エッチング
ガス量当りのエッチングすべき材料の量（エッチング効
率）が約２１％程度大きくなる。This is because even if an equal amount of etching gas is supplied per unit area, the amount of material to be etched per unit etching gas amount is different. For example, if the pattern density is 20%, the material to be etched is 80
%, The material to be etched is 97% when the pattern density is 3%. Therefore, when the pattern density is 3%, the amount of material to be etched per unit etching gas amount (etching efficiency) is increased by about 21% as compared with the case where the pattern density is 20%.
【０００８】このため、パターン密度３％の領域では、
アンダーエッチング（エッチング不足）状態となり易
く、実際の回路パターンが設計値より太ってしまう。パ
ターン密度が大きい領域では、逆にオーバーエッチング
となり、実際の回路パターンが設計値より細くなってし
まう。Therefore, in the area where the pattern density is 3%,
Under-etching (insufficient etching) is likely to occur, and the actual circuit pattern becomes thicker than the designed value. On the contrary, in a region where the pattern density is high, overetching occurs, and the actual circuit pattern becomes thinner than the design value.
【０００９】たとえばトランジスタのゲート電極の形成
でこのようなことがおこれば、ある領域のトランジスタ
のゲート長が異常に細まり、トランジスタ動作しなくな
ったり、逆にある領域のトラニンジスタのゲート長が太
くなって、予想したスピードを実現できなくなる。ま
た、Ａｌなどの配線の形成でこのようなことがおこって
も、配線抵抗や配線容量が予期したものと大きく異なっ
て、ＬＳＩの回路パターン全体としての性能が設計どお
りに出せないことになる。If such a phenomenon occurs in the formation of the gate electrode of the transistor, for example, the gate length of the transistor in a certain region becomes abnormally thin, and the transistor does not operate, or conversely, the gate length of the transistor transistor in a certain region becomes thick. Then, the expected speed cannot be achieved. Further, even if such a phenomenon occurs in the formation of wiring such as Al, the wiring resistance and the wiring capacitance are largely different from those expected, and the performance of the entire circuit pattern of the LSI cannot be achieved as designed.
【００１０】本発明はこのような点を考慮してなされた
ものであり、回路パターンを精度良く形成して高性能の
半導体装置を得ることができる半導体装置用ガラスマス
クおよびその製造方法を提供することを目的とする。The present invention has been made in consideration of the above points, and provides a glass mask for a semiconductor device and a method for manufacturing the same, in which a circuit pattern can be accurately formed to obtain a high-performance semiconductor device. The purpose is to
【００１１】[0011]
【課題を解決するための手段】本発明は、ガラス基板上
にマスクパターンを有し、回路パターンを形成して半導
体チップを作成するための半導体装置用ガラスマスクに
おいて、マスクパターンは複数のマスク領域内に配置さ
れ、各マスク領域内のマスクパターン幅は、対応する半
導体チップのチップ領域のパターン密度が所定値以下の
場合、回路パターンの設計値幅を狭く補正して定められ
ていることを特徴とする半導体装置用ガラスマスク、お
よびガラス基板上にマスクパターンを有し、回路パター
ンを形成して半導体チップを作成するための半導体装置
用ガラスマスクの製造方法において、半導体チップ内を
複数のチップ領域に区画し、各チップ領域のパターン密
度を求め、チップ領域のパターン密度に応じてパターン
密度が所定値以下の場合は、回路パターンの設計値幅を
狭く補正して、対応するマスク領域内マスクパターンの
幅を定め、このように幅が定められたマスクパターンを
ガラス基板上に形成することを特徴とする半導体装置用
ガラスマスクの製造方法である。The present invention provides a glass mask for a semiconductor device having a mask pattern on a glass substrate and forming a circuit pattern to form a semiconductor chip, wherein the mask pattern has a plurality of mask regions. When the pattern density of the chip region of the corresponding semiconductor chip is less than or equal to a predetermined value, the mask pattern width in each mask region is determined by narrowing the design value width of the circuit pattern. In a method for manufacturing a glass mask for a semiconductor device, which has a mask pattern on a glass substrate for a semiconductor device, and has a mask pattern on a glass substrate to form a circuit pattern to form a semiconductor chip, the inside of the semiconductor chip is divided into a plurality of chip regions. The pattern density of each chip area is divided, and the pattern density is below a predetermined value according to the pattern density of the chip area. In this case, the semiconductor device characterized by narrowing the design value width of the circuit pattern to determine the width of the corresponding mask pattern in the mask area and forming the mask pattern having the width thus determined on the glass substrate. It is a method for manufacturing a glass mask for use.
【００１２】[0012]
【作用】各マスク領域内に配置されたマスクパターン幅
は、対応するチップ領域のパターン密度が所定値以下の
場合、回路パターン設計値を狭く補正し定められている
ので、パターン密度が所定値以下であっても、得られる
半導体チップの回路パターンの幅を設計値に近い値とす
ることができる。The width of the mask pattern arranged in each mask area is determined by correcting the circuit pattern design value narrowly when the pattern density of the corresponding chip area is less than the predetermined value. Even in this case, the width of the circuit pattern of the obtained semiconductor chip can be set to a value close to the design value.
【００１３】[0013]
【実施例】以下、図面を参照して本発明の実施例につい
て説明する。図１乃至図３は本発明による半導体装置用
ガラスマスクおよびその製造方法の実施例を示す図であ
る。Embodiments of the present invention will be described below with reference to the drawings. 1 to 3 are views showing an embodiment of a glass mask for a semiconductor device and a method for manufacturing the same according to the present invention.
【００１４】このうち、図１（ａ）は本発明によるガラ
スマスクおよびこのガラスマスクによって得られる半導
体チップを示す側面図であり、図１（ｂ）は比較のため
に示す従来のガラスマスクと半導体チップを示す側面図
である。また図２は、ガラスマスク内のマスク領域と、
半導体チップ内のチップ領域を示す図である。図２は便
宜上ガラスマスクと半導体チップとを同一図面で示す。Of these, FIG. 1 (a) is a side view showing a glass mask according to the present invention and a semiconductor chip obtained by this glass mask, and FIG. 1 (b) is a conventional glass mask and semiconductor shown for comparison. It is a side view which shows a chip. Further, FIG. 2 shows a mask area in a glass mask,
It is a figure which shows the chip area | region in a semiconductor chip. FIG. 2 shows a glass mask and a semiconductor chip in the same drawing for convenience.
【００１５】図１（ａ）に示すように、ガラスマスク１
０は、ガラス基板１１と、ガラス基板１１上に設けられ
たマスクパターン１２ａ、１２ｂ、１２ｃとを備えてい
る。また図２に示すように、ガラスマスク１０は複数の
マスク領域Ａ、Ｂ、Ｃからなり、このマスク領域Ａ、
Ｂ、Ｃは半導体チップ２０のチップ領域Ａ、Ｂ、Ｃに対
応している。ガラスマスク１０のうち、マスクパターン
１２ａはマスク領域Ａ内に、マスクパターン１２ｂはマ
スク領域Ｂ内に、マスクパターン１２ｃはマスク領域Ｃ
内に各々配置されている。また、図１（ａ）に示すよう
に、半導体チップ２０は基板２１と、基板２１上に形成
された回路パターン２２ａ、２２ｂ、２２ｃとからな
り、このうち回路パターン２２ａはチップ領域Ａ内に、
回路パターン２２ｂはチップ領域Ｂ内に、回路パターン
２２ｃはチップ領域Ｃ内に各々配置されている。As shown in FIG. 1A, the glass mask 1
Reference numeral 0 includes a glass substrate 11 and mask patterns 12a, 12b, 12c provided on the glass substrate 11. Further, as shown in FIG. 2, the glass mask 10 is composed of a plurality of mask areas A, B and C.
B and C correspond to the chip areas A, B and C of the semiconductor chip 20. In the glass mask 10, the mask pattern 12a is in the mask region A, the mask pattern 12b is in the mask region B, and the mask pattern 12c is in the mask region C.
It is arranged inside each. Further, as shown in FIG. 1A, the semiconductor chip 20 is composed of a substrate 21 and circuit patterns 22a, 22b, 22c formed on the substrate 21, of which the circuit pattern 22a is in the chip area A,
The circuit pattern 22b is arranged in the chip area B, and the circuit pattern 22c is arranged in the chip area C.
【００１６】また、各マスク領域Ａ，Ｂ，Ｃ内のマスク
パターン１２ａ，１２ｂ，１２ｃの幅は、対応するチッ
プ領域Ａ，Ｂ，Ｃの回路パターンのパターン密度に応じ
て、回路パターンの設計値幅を補正して定められてい
る。Further, the widths of the mask patterns 12a, 12b, 12c in the mask areas A, B, C are the designed value widths of the circuit patterns in accordance with the pattern densities of the circuit patterns in the corresponding chip areas A, B, C. Is stipulated by amending.
【００１７】次に半導体装置用ガラスマスクの製造方法
について説明する。まず図２に示すように、基板２１と
回路パターン２２ａ，２２ｂ，２２ｃとからなるＬＳＩ
の１つの半導体チップを、複数のチップ領域Ａ，Ｂ，Ｃ
に区画する。この区画のやり方は、メモリや各種演算回
路などをマクロごとに１つのチップ領域とし、メモリや
各種演算回路間の配線領域をもう１つのチップ領域とし
て分ける。あるいは別の区画方法として、１つの半導体
チップを微小な単位矩形に分けるやり方もある。Next, a method of manufacturing a glass mask for a semiconductor device will be described. First, as shown in FIG. 2, an LSI including a substrate 21 and circuit patterns 22a, 22b, 22c.
One semiconductor chip of a plurality of chip areas A, B, C
Partition into In this partitioning method, the memory and various arithmetic circuits are divided into one chip area for each macro, and the wiring area between the memory and various arithmetic circuits is divided into another chip area. Alternatively, as another division method, there is also a method of dividing one semiconductor chip into minute unit rectangles.
【００１８】次に各チップ領域Ａ，Ｂ，Ｃの回路パター
ン２２ａ，２２ｂ，２２ｃのパターン密度（設計値）を
求める。この求め方として、例えばメモリーセルなどく
り返しパターンの多いところでは、容易に概算ができ
る。また他のマクロでも、複数の場所を任意抽出し、そ
れらに対してパターン密度を正確に求めることにより、
マクロ内のパターン密度を概算できる。マクロ間の配線
領域に対しても同一の手法を用いることができる。また
チップ領域Ａ，Ｂ，Ｃごとのパターン密度を求める方法
として、ＣＡＤでチップ領域Ａ，Ｂ，Ｃ内のパターン密
度を求める手法もとれる。Next, the pattern densities (design values) of the circuit patterns 22a, 22b, 22c of the chip areas A, B, C are obtained. As a method of obtaining this, approximate calculation can be easily performed in a place where there are many repeated patterns such as a memory cell. Also in other macros, by arbitrarily extracting multiple locations and accurately obtaining the pattern density for them,
The pattern density in the macro can be roughly estimated. The same method can be used for the wiring area between macros. As a method for obtaining the pattern density for each of the chip areas A, B, C, there is a method for obtaining the pattern density in the chip areas A, B, C by CAD.
【００１９】これらの手法で各チップ領域Ａ，Ｂ，Ｃご
とのパターン密度を求めた後、図４に示すような別途実
験で求められたパターン密度と、回路パターンの設計値
と加工後の仕上り値との差（パターン変換差）の関係の
データをもとに対応するマスク領域Ａ，Ｂ，Ｃ内のマス
クパターン１２ａ，１２ｂ，１２ｃの幅を定める。After the pattern densities of the respective chip areas A, B, and C are obtained by these methods, the pattern densities obtained by a separate experiment as shown in FIG. 4, the design values of the circuit patterns, and the finish after processing are obtained. The widths of the mask patterns 12a, 12b, 12c in the corresponding mask areas A, B, C are determined based on the data of the relationship with the value (pattern conversion difference).
【００２０】例えば、あるチップ領域のパターン密度が
３０％のときは、対応するマスク領域内のマスクパター
ンの幅を、回路パターンの設計値幅（図１（ａ）の破線
幅）と同一として定める。すなわち回路パターンの設計
値幅が１μｍのときはマスクパターンの幅を１μｍに、
回路パターンの設計値幅が０．５μｍのときはマスクパ
ターンの幅を０．５μｍとする。また、あるチップ領域
（破線領域）のパターン密度が２％の場合は、マスクパ
ターンの幅を回路パターンの設計値幅より一律０．１３
μｍ細く作成する。他方あるチップ領域のパターン密度
が３０％以上の場合は、マスクパターンの幅を、回路パ
ターンの設計値幅よりわずかに太く作成する。For example, when the pattern density of a certain chip area is 30%, the width of the mask pattern in the corresponding mask area is determined to be the same as the design value width of the circuit pattern (broken line width in FIG. 1A). That is, when the design value width of the circuit pattern is 1 μm, the width of the mask pattern is set to 1 μm,
When the design value width of the circuit pattern is 0.5 μm, the width of the mask pattern is 0.5 μm. Further, when the pattern density of a certain chip area (broken line area) is 2%, the width of the mask pattern is uniformly 0.13 from the design value width of the circuit pattern.
Make it as thin as μm. On the other hand, when the pattern density of a certain chip area is 30% or more, the width of the mask pattern is made slightly thicker than the design value width of the circuit pattern.
【００２１】このように幅が定められたマスクパターン
１２ａ，１２ｂ，１２ｃをガラス基板１１上に形成する
ことによってガラスマスク１０が得られる。The glass mask 10 is obtained by forming the mask patterns 12a, 12b and 12c having the widths thus defined on the glass substrate 11.
【００２２】次に、このようにして得られたガラスマス
ク１０を用いて半導体チップを作成した場合における半
導体チップの回路パターン幅について、従来との比較に
おいて説明する。説明上、例えば図２に示すチップ領域
Ａのパターン密度を２％、チップ領域Ｂのパターン密度
を２０％、チップ領域Ｃのパターン密度を３０％とす
る。この場合、図１（ａ）に示すように、ガラスマスク
１０のマスク領域Ａのマスクパターン１２ａの幅を、回
路パターンの設計値幅（破線幅）より小さくし、マスク
領域Ｂのマスクパターン１２ｂの幅を回路パターンの設
計値幅（破線幅）よりわずかに小さくし、マスク領域Ｃ
のマスクパターン１２Ｃの幅を回路パターンの設計値幅
（破線幅）と同一とする。このようなガラスマスク１０
を用いて得られる半導体チップ２０の回路パターン２２
ａ，２２ｂ，２２ｃの幅は、設計値幅に略一致する。Next, the circuit pattern width of the semiconductor chip when the semiconductor chip is produced using the glass mask 10 thus obtained will be described in comparison with the conventional one. For the sake of explanation, for example, the pattern density of the chip area A shown in FIG. 2 is 2%, the pattern density of the chip area B is 20%, and the pattern density of the chip area C is 30%. In this case, as shown in FIG. 1A, the width of the mask pattern 12a in the mask region A of the glass mask 10 is made smaller than the design value width (broken line width) of the circuit pattern, and the width of the mask pattern 12b in the mask region B is reduced. Is slightly smaller than the design value width (broken line width) of the circuit pattern, and the mask area C
The width of the mask pattern 12C is the same as the design value width (broken line width) of the circuit pattern. Such a glass mask 10
Circuit pattern 22 of semiconductor chip 20 obtained by using
The widths of a, 22b, and 22c substantially match the design value width.
【００２３】これに対して、図１（ｂ）に示すように、
ガラスマスク１０のマスクパターン３２ａ，３２ｂ，３
２ｃの幅を、回路パターンの設計値幅（破線幅）と同一
とした従来例の場合、ガラスマスク１０を用いて得られ
た半導体チップ２０の回路パターン４２ｃは設計値幅に
略一致する。しかしながら回路パターン４２ａ，４２ｂ
は設計値幅より太くなってしまう。なお、従来例におい
て、マスクパターン３２ａ，３２ｂ，３２ｃは、マスク
領域Ａ，Ｂ，Ｃに各々配置され、回路パターン４２ａ，
４２ｂ，４２ｃは、チップ領域Ａ，Ｂ，Ｃに各々配置さ
れている。 具体例 以下、本発明の具体例について、図３により説明する。
大容量のＳＲＡＭを混載した２０ＧＩＣデバイスでメモ
リセルのドライバートランジスタのゲート長０．５μを
リソグラフィ工程およびエッチング工程により仕上げ
た。この場合における半導体チップ内のゲート長のバラ
ツキの測定値を従来例と本発明を用いた場合で比較し、
図３に示した。図３からわかるように、従来例えば、
０．４７〜０．６４μｍにゲート長の仕上がり寸法がバ
ラついているのに対し、本発明の場合仕上がり寸法が
０．４８〜０．５４μｍになっており、本発明の効果が
実証された。On the other hand, as shown in FIG.
Mask patterns 32a, 32b, 3 of the glass mask 10
In the case of the conventional example in which the width of 2c is the same as the design value width (broken line width) of the circuit pattern, the circuit pattern 42c of the semiconductor chip 20 obtained by using the glass mask 10 substantially matches the design value width. However, the circuit patterns 42a, 42b
Is thicker than the design price range. In the conventional example, the mask patterns 32a, 32b, 32c are arranged in the mask areas A, B, C, respectively, and the circuit patterns 42a,
42b and 42c are arranged in the chip areas A, B and C, respectively. Specific Example Hereinafter, a specific example of the present invention will be described with reference to FIG.
The gate length of 0.5 μ of the driver transistor of the memory cell was finished by a lithography process and an etching process in a 20 GIC device in which a large capacity SRAM was mounted. In this case, the measured values of the variation in the gate length in the semiconductor chip are compared between the conventional example and the case of using the present invention,
It is shown in FIG. As can be seen from FIG. 3, for example,
While the finished size of the gate length varies from 0.47 to 0.64 μm, the finished size of the present invention is 0.48 to 0.54 μm, demonstrating the effect of the present invention.
【００２４】[0024]
【発明の効果】以上説明したように、本発明によれば、
半導体チップのチップ領域のパターン密度が所定値以下
であっても、得られる半導体チップの回路パターンの幅
を設計値に近い値とすることができる。このため、精度
良く半導体チップを得ることができる。As described above, according to the present invention,
Even if the pattern density of the chip region of the semiconductor chip is equal to or less than a predetermined value, the width of the obtained circuit pattern of the semiconductor chip can be set to a value close to the design value. Therefore, a semiconductor chip can be obtained with high accuracy.
【図１】本発明による半導体装置用ガラスマスクおよび
半導体チップを従来例と比較して示す図。FIG. 1 is a diagram showing a glass mask for a semiconductor device and a semiconductor chip according to the present invention in comparison with a conventional example.
【図２】ガラスマスクのマスク領域と半導体チップのチ
ップ領域とを示す図。FIG. 2 is a diagram showing a mask region of a glass mask and a chip region of a semiconductor chip.
【図３】本発明の具体例を従来例と比較して示す図。FIG. 3 is a diagram showing a specific example of the present invention in comparison with a conventional example.
【図４】パターン密度と、回路パターンの仕上がり値と
設計値との差を示す図。FIG. 4 is a diagram showing a pattern density and a difference between a finished value and a design value of a circuit pattern.
１０ ガラスマスク １１ ガラス基板 １２ａ，１２ｂ，１２ｃ マスクパターン ２０ 半導体チップ ２１ 基板 ２２ａ，２２ｂ，２２ｃ 回路パターン 10 glass mask 11 glass substrate 12a, 12b, 12c mask pattern 20 semiconductor chip 21 substrate 22a, 22b, 22c circuit pattern
Claims (3)
路パターンを形成して半導体チップを作成するための半
導体装置用ガラスマスクにおいて、 マスクパターンは複数のマスク領域内に配置され、各マ
スク領域内のマスクパターン幅は、対応する半導体チッ
プのチップ領域のパターン密度が所定値以下の場合、回
路パターンの設計値幅を狭く補正して定められているこ
とを特徴とする半導体装置用ガラスマスク。1. A glass mask for a semiconductor device, having a mask pattern on a glass substrate, for forming a circuit pattern to form a semiconductor chip, wherein the mask pattern is arranged in a plurality of mask regions, and each mask region is provided. The mask pattern width is defined by narrowing the design value width of the circuit pattern when the pattern density of the chip region of the corresponding semiconductor chip is less than or equal to a predetermined value.
路パターンを形成して半導体チップを作成するための半
導体装置用ガラスマスクにおいて、 マスクパターンは複数のマスク領域内に配置され、各マ
スク領域内のマスクパターン幅は、対応する半導体チッ
プのチップ領域のパターン密度が所定値以上の場合、回
路パターンの設計値幅を広く補正して定められているこ
とを特徴とする半導体装置用ガラスマスク。2. A glass mask for a semiconductor device, which has a mask pattern on a glass substrate and forms a circuit pattern to form a semiconductor chip, wherein the mask pattern is arranged in a plurality of mask regions, and each mask region is formed. The mask pattern width is defined by widely correcting the design value width of the circuit pattern when the pattern density of the chip area of the corresponding semiconductor chip is a predetermined value or more.
路パターンを形成して半導体チップを作成するための半
導体装置用ガラスマスクの製造方法において、 半導体チップ内を複数のチップ領域に区画し、各チップ
領域のパターン密度を求め、チップ領域のパターン密度
に応じてパターン密度が所定値以下の場合は、回路パタ
ーンの設計値幅を狭く補正して、対応するマスク領域内
マスクパターンの幅を定め、このように幅が定められた
マスクパターンをガラス基板上に形成することを特徴と
する半導体装置用ガラスマスクの製造方法。3. A method of manufacturing a glass mask for a semiconductor device, comprising a mask pattern on a glass substrate and forming a circuit pattern to form a semiconductor chip, wherein the inside of the semiconductor chip is divided into a plurality of chip regions. Obtaining the pattern density of each chip area, if the pattern density is less than a predetermined value according to the pattern density of the chip area, the design value width of the circuit pattern is corrected narrowly, the width of the mask pattern in the corresponding mask area is determined, A method for manufacturing a glass mask for a semiconductor device, which comprises forming a mask pattern having a width as described above on a glass substrate.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29307492A JPH06138643A (en) | 1992-10-30 | 1992-10-30 | Glass mask for semiconductor device and its production |
| KR1019930022460A KR0133269B1 (en) | 1992-10-30 | 1993-10-27 | Glass mask for semiconductor device and making method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29307492A JPH06138643A (en) | 1992-10-30 | 1992-10-30 | Glass mask for semiconductor device and its production |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06138643A true JPH06138643A (en) | 1994-05-20 |
Family
ID=17790115
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29307492A Pending JPH06138643A (en) | 1992-10-30 | 1992-10-30 | Glass mask for semiconductor device and its production |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH06138643A (en) |
| KR (1) | KR0133269B1 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100548534B1 (en) * | 1999-04-22 | 2006-02-02 | 주식회사 하이닉스반도체 | Cell projection mask |
| JP2007116144A (en) * | 2005-10-05 | 2007-05-10 | Asml Netherlands Bv | Method of patterning positive resist layer overlaying lithography substrate |
| JP2007249167A (en) * | 2006-02-14 | 2007-09-27 | Nuflare Technology Inc | Pattern generation method and charged particle beam-drawing apparatus |
| US7346882B2 (en) | 2001-07-30 | 2008-03-18 | Kabushiki Kaisha Toshiba | Pattern forming method, mask manufacturing method, and LSI manufacturing method |
| JP2012182506A (en) * | 2006-02-14 | 2012-09-20 | Nuflare Technology Inc | Pattern generation method and charged particle beam-drawing apparatus |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002296754A (en) * | 2001-03-29 | 2002-10-09 | Toshiba Corp | Production method for mask |
-
1992
- 1992-10-30 JP JP29307492A patent/JPH06138643A/en active Pending
-
1993
- 1993-10-27 KR KR1019930022460A patent/KR0133269B1/en not_active IP Right Cessation
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100548534B1 (en) * | 1999-04-22 | 2006-02-02 | 주식회사 하이닉스반도체 | Cell projection mask |
| US7346882B2 (en) | 2001-07-30 | 2008-03-18 | Kabushiki Kaisha Toshiba | Pattern forming method, mask manufacturing method, and LSI manufacturing method |
| JP2007116144A (en) * | 2005-10-05 | 2007-05-10 | Asml Netherlands Bv | Method of patterning positive resist layer overlaying lithography substrate |
| US7824842B2 (en) | 2005-10-05 | 2010-11-02 | Asml Netherlands B.V. | Method of patterning a positive tone resist layer overlaying a lithographic substrate |
| JP2007249167A (en) * | 2006-02-14 | 2007-09-27 | Nuflare Technology Inc | Pattern generation method and charged particle beam-drawing apparatus |
| JP2012182506A (en) * | 2006-02-14 | 2012-09-20 | Nuflare Technology Inc | Pattern generation method and charged particle beam-drawing apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| KR0133269B1 (en) | 1998-04-16 |
| KR940010236A (en) | 1994-05-24 |
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