JP2007088145A - Method for manufacturing semiconductor device, pattern correction method and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device capable of reducing a process conversion difference caused upon an etching process. <P>SOLUTION: The method for manufacturing the semiconductor device contains the steps of forming a resist pattern 2P containing a pattern on a film 1 to be processed, changing a size of the pattern, and etching the film 1 to be processed by using the resist pattern 2P in which the size of the pattern is changed as a mask. In the step of changing the size of the pattern, the change amount of the size of the pattern is decided so that the pattern which is composed of the film 1 to be processed corresponding to the pattern which is formed by the step of etching the film 1 to be processed has a desired dimension. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing method, a pattern correction method, and a program, and more particularly, to a semiconductor device manufacturing method, a pattern correction method, and a program including a process for reducing a processing conversion difference that occurs during an etching process.

  Conventionally, in a semiconductor process, an insulating film, a semiconductor film, or a conductive film is formed on a semiconductor substrate, and the insulating film, semiconductor film, or conductive film (hereinafter, these films are collectively referred to as a film to be processed). A semiconductor circuit is formed by repeating the process of processing into a desired shape.

  The process of processing the film to be processed into a desired shape includes a process of forming a resist pattern on the film to be processed (photolithography process), and a process of etching the film to be processed using the resist pattern as a mask (etching process). including.

  In recent years, the dimension of a pattern (processed film pattern) obtained by etching a film to be processed in this manner has become smaller and smaller with the miniaturization of semiconductor devices. In order to obtain a fine film pattern to be processed, it is necessary to form a resist pattern including a fine pattern.

  However, it is becoming difficult to form a resist pattern including a fine pattern because the wavelength of the exposure light source is not sufficiently short. Therefore, it has been proposed to reduce the pattern size of the resist pattern by post-processing after forming the resist pattern (Patent Document 1). Typically, there is a shrink process of reducing the size of holes in the resist pattern.

However, even if a resist pattern including a fine pattern can be formed by a shrink process or the like, a processed film pattern including a pattern corresponding to the fine pattern in the resist pattern is formed due to a processing conversion difference that occurs during the etching process. It is difficult to do.
JP 2003-234279 A

  An object of the present invention is to provide a semiconductor device manufacturing method, a pattern correction method, and a program capable of reducing a processing conversion difference that occurs during an etching process.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  That is, in order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a resist pattern including a pattern on a film to be processed, a step of changing the size of the pattern, Etching the film to be processed using the resist pattern whose size has been changed as a mask, and the step of changing the size of the pattern corresponds to the pattern formed by the step of etching the film to be processed The change amount of the pattern size is determined so that the pattern made of the processed film has a desired dimension.

  The pattern correction method according to the present invention includes a first process related to the manufacture of an exposure mask, a second process related to a change in the size of a pattern included in a resist pattern formed using the exposure mask, and A step of preparing a process group including a third process related to etching of the film to be processed, which is performed using the resist pattern whose pattern size is changed as a mask, and when the third process is changed. In order to obtain a processed film pattern having substantially the same dimensions as the processed film pattern made of the processed film obtained by the third process before the third process is changed, the first process is performed. Correcting the correction rule or the correction model of the second process without correcting the correction rule and the correction model of the process. The features.

  Another method of manufacturing a semiconductor device according to the present invention includes a step of dividing a chip including a film to be processed and a film serving as a hard mask formed on the film to be processed into a plurality of blocks, and the plurality of blocks For each of the above, a resist film is formed on the hard mask film, the resist film on the block is selectively exposed, the dyst film is developed, and a pattern is selectively present on the block. A resist pattern is formed, the dimensions of the pattern formed on the block are measured, and based on the measurement result, the processed film pattern having a desired dimension is formed in the block. A process for changing the size of the pattern according to claim 1 is performed on the pattern formed on the pattern, and the resist pattern including the pattern on which the process has been performed. Etching the film to be the hard mask using a mask as a mask, forming the hard mask film, and etching the film to be processed using the hard mask film as a mask. And a process for forming a film pattern to be processed.

  The program according to the present invention includes a step of forming a resist pattern including a pattern on a processing film, a step of changing the size of the pattern, and the processing using the resist pattern whose size of the pattern has been changed as a mask. A pattern of the film to be processed corresponding to the pattern formed by the process of etching the film to be processed has a desired dimension. So as to cause the computer to execute a procedure for determining the amount of change in the size of the pattern.

  According to the present invention, it is possible to realize a semiconductor device manufacturing method, a pattern correction method, and a program that can reduce a processing conversion difference that occurs during an etching process.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
First, a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described.

[Figure 1]
A resist film 2 is applied on the film 1 to be processed.

  The processed film 1 is an insulating film, a semiconductor film, or a conductive film. The film 1 to be processed may be a single layer film or a laminated film.

  The laminated film may be a laminated film of the same type of film (for example, a laminated film of a silicon oxide film and a silicon nitride film) or a laminated film of different types of films (for example, an insulating film and a semiconductor film). In some cases, a laminated film).

  The film 1 to be processed is formed on a substrate including a semiconductor substrate (not shown). The semiconductor substrate is, for example, a silicon substrate, a strained silicon substrate, an SOI substrate, or a substrate containing SiGe. The substrate may further include an insulating film pattern, a semiconductor film pattern, or a conductive film pattern formed on the semiconductor substrate.

[Figure 2]
The resist film 2 is exposed and further developed to form a resist pattern 2P. Resist pattern 2P includes patterns 2P1 and 2P2. The resist pattern 2P is formed under an exposure condition that is advantageous for forming the patterns 2P1 and 2P2, that is, an exposure condition that ensures a necessary lithography margin.

  Even if the film to be processed 1 is etched using the resist pattern 2P at this stage as a mask, a film pattern to be processed having a desired dimension (here, a design dimension) is not formed due to a processing conversion difference that occurs during the etching process. .

  Here, it is assumed that the pattern in the processed film pattern corresponding to the pattern 2P1 formed by etching the processed film 1 using the pattern 2P1 as a mask is a pattern larger than the design dimension (Ld1).

  On the other hand, the pattern in the processed film pattern corresponding to the pattern 2P2 formed by etching the processed film 1 using the pattern 2P2 as a mask is a pattern smaller than the design dimension (Ld2) of the pattern. . Here, Ld1 = Ld2 (= Ld).

[Fig. 3]
By applying an additional process (process for reducing the processing conversion difference) to the resist pattern 2P, the patterns 2P1 and 2P2 in the resist pattern 2P are converted into patterns 2P1 ′ and 2P2 ′, respectively. In FIG. 3, patterns 2P1 and 2P2 are indicated by broken lines.

  The dimension of the pattern 2P1 'is smaller than the dimension of the pattern 2P1. As an additional process for converting the pattern 2P1 into the pattern 2P1 ′, for example, there is a well-known resist slimming process.

  The size of the pattern 2P1 and the amount of change thereof are determined so as to satisfy | L2P1′−Ld | <| L2P1−Ld |, that is, the processing conversion difference becomes small.

  L2P1 ′: A dimension of a pattern in the processed film pattern corresponding to the pattern 2P1 ′ formed by etching the processed film 1 using the resist pattern 2P after the addition process as a mask.

  L2P1: A dimension of a pattern in the processed film pattern corresponding to the pattern 2P1 formed by etching the processed film 1 using the resist pattern 2P before the addition process as a mask.

  Here, L2P1-Ld is positive (> 0), but may be negative (<0) if the shape and dimensions of the pattern 2P1 change. When L2P1-Ld is positive (> 0), L2P1′-Ld may be positive (> 0) or negative (<0). Similarly, when L2P1-Ld is negative (<0), L2P1′-Ld may be negative (<0) or positive (> 0).

  | L2P1′−Ld | is preferably zero (the machining conversion difference is zero).

  On the other hand, the dimension of the pattern 2P2 'is larger than the dimension of the pattern 2P2. As an additional process for changing the pattern 2P2 to the pattern 2P2 ', for example, there is a known resist shrink process.

  The amount of change in the size of the pattern 2P2 is determined so as to satisfy | L2P2′−Ld | <| L2P2−Ld |, that is, the processing conversion difference is reduced.

  L2P2 ′: The dimension of the pattern in the processed film pattern corresponding to the pattern 2P2 ′ formed by etching the processed film 1 using the resist pattern 2P after the addition process as a mask.

  L2P2: The dimension of the pattern in the processed film pattern corresponding to the pattern 2P2 formed by etching the processed film 1 using the resist pattern 2P before the addition process as a mask.

  Here, L2P2-Ld is negative (<0), but may be positive (> 0) if the shape and dimensions of the pattern 2P2 change. When L2P2-Ld is negative (<0), L2P2′-Ld may be negative (<0) or positive (> 0). Similarly, when L2P2-Ld is positive (> 0), L2P2′-Ld may be positive (> 0) or negative (<0).

  | L2P2′−Ld | is preferably zero (the machining conversion difference is zero).

  In the case of line and space, for example, Ld = 140 nm, L2P1-Ld = 15 nm to 20 nm, and L2P2′−Ld = −15 nm to −20 nm.

  After FIG. 3, a well-known process, that is, a process of forming a film pattern to be processed by etching the film 1 to be processed using the resist pattern 2P as a mask continues. The film pattern to be processed is, for example, a pattern constituting a semiconductor device.

  4 to 9 show examples of film patterns to be processed.

  FIG. 4 is a cross-sectional view showing a state where an electrode or wiring made of the semiconductor film or conductive film is formed as the processed film pattern 1P when the processed film 1 is a semiconductor film or a conductive film.

  FIG. 5 is a cross-sectional view showing a state where wiring grooves are formed on the surface of the interlayer insulating film as the processed film pattern 1P when the processed film 1 is an interlayer insulating film. Wiring is formed by embedding a metal such as Cu in the wiring groove by the damascene process.

  FIG. 6 is a cross-sectional view showing a state in which a via hole is formed in the interlayer insulating film as the processed film pattern 1P when the processed film 1 is an interlayer insulating film. A plug is formed by embedding a metal such as Cu in the via hole.

  FIG. 7 shows a case where the processed film 1 is a semiconductor film or a laminated film of a conductive film and an insulating film, and the gate electrode 1P1 made of the semiconductor film or the conductive film and the gate made of the insulating film as the processed film pattern 1P. It is sectional drawing which shows a mode that the gate structure containing insulating film 1P2 was formed.

  FIG. 8 shows a gate made of the first insulating film as a processed film pattern 1P when the processed film 1 is a laminated film of a first insulating film and a semiconductor film or a conductive film and a second insulating film. FIG. 5 is a cross-sectional view showing a state in which a gate structure including an upper insulating film (etching mask film) 1P3, a gate electrode 1P1 made of the semiconductor film or conductive film, and a gate insulating film 1P2 made of the second insulating film is formed. .

  FIG. 9 shows that when the film to be processed 1 is a laminated film of a conductive film, a semiconductor film, and an insulating film, the first gate electrode 1P4 made of the conductive film and the first film made of the semiconductor film are formed as the processed film pattern 1P. It is sectional drawing which shows a mode that the gate structure (poly metal gate, polycide gate) containing 2 gate electrodes 1P1 and the gate insulating film 1P2 which consists of said insulating film was formed.

  When the resist pattern 2P is a resist pattern for forming a line and space (L / S) pattern, FIGS. 2, 3, and 4 are, for example, FIG. 10, FIG. 11, and FIG.

  By the way, when the L / S ratio is approximately 1: 1, a necessary lithography margin can be ensured without considering the processing conversion difference. However, when a fine L / S pattern is formed by a lithography process in consideration of a processing conversion difference without using an additional process, it is difficult to ensure a lithography margin.

  For example, in the case of a method (comparative example) in which the resist pattern 2P shown in FIG. 11 is formed by a lithography process without using an additional process, a usable dose amount and a focus range (allowable range) as shown in FIG. ) 10 is narrowed and the lithography margin is reduced.

  Since the dose amount is replaced with the exposure amount, in the case of the comparative example, it becomes difficult to obtain the exposure latitude and the focus tolerance (DOF) necessary for the process. In the case of a CMOS having a design dimension of 140 nm, the exposure tolerance required for the process is about 10%, and the focus tolerance (DOF) required for the process is about 0.3 μm.

  In consideration of the above, in the process of forming the resist pattern 2P before the addition process of FIG. 10, as shown in FIG. 14, the patterns 2P1 and 2P2 are formed under the condition of a large lithography margin, and then the process of FIG. The patterns 2P1 ′ and 2P2 ′ having dimensions in consideration of processing conversion differences are formed by the additional processing. In this way, by reducing the processing conversion difference by the additional processing, the exposure amount tolerance and the focus tolerance cut by the processing conversion difference can be expanded, so that the L / S ratio is approximately 1: 1. A pattern can be formed more easily.

  As described above, a necessary lithography margin can be ensured for an L / S pattern having an L / S ratio of approximately 1: 1 unless the processing conversion difference is taken into consideration. In other words, an L / S pattern having an L / S ratio of approximately 1: 1 is a pattern having a small lithography margin in consideration of a processing conversion difference.

  On the other hand, as shown in FIG. 15, a lithography margin such as a processed film pattern that requires a small lithography margin from the beginning without considering a processing conversion difference, or a processed film pattern that does not provide a required lithography margin from the beginning. There is also a resist pattern including a pattern 2P4 ′ corresponding to a film pattern to be processed (lithography margin rate-limiting pattern). As a lithography margin rate-limiting pattern, for example, there is a pattern (danger pattern) that is highly likely to cause an open defect or a short circuit.

  In FIG. 15, 2P3 'indicates a pattern corresponding to a pattern having a large lithography margin from the beginning.

  The present embodiment is also effective when forming a lithography margin rate limiting pattern.

  That is, when the resist pattern includes a pattern for forming a lithography margin rate-determining pattern, a pattern 2P4 is formed under a condition of a large lithography margin as shown in FIG. Then, as shown in FIG. 17, the lithography margin rate-limiting pattern can be easily formed by forming the pattern 2P4 ′ having a dimension considering the processing conversion difference by the additional processing.

  In FIG. 16, 2P3 indicates a pattern corresponding to the pattern 2P3 'before the addition processing. The lithography margin of the pattern 2P3 is larger than the lithography margin of the pattern 2P3 '. The patterns 2P3 and 2P4 before the additional processing are formed under exposure conditions that provide a necessary lithography margin.

  After the resist pattern including the patterns 2P3 ′ and 2P4 ′ is formed, a process of forming the processed film pattern by etching the processed film using the resist pattern as a mask continues.

  As a pattern in which it is difficult to ensure a necessary lithography margin from the beginning, there is a pattern called an application. The contact is an adjacent part of two two-dimensional patterns.

  18 and 19 are plan views showing an example of application.

  FIG. 18 shows an abutment 23 formed by the proximity of two line patterns 21 and 22 whose longitudinal directions are different by 90 degrees.

  FIG. 19 shows an abutment 26 formed by the proximity of two hole patterns 24 and 25 formed in an insulating film.

  There are a lot of assignments in the logic circuit compared to the memory circuit.

  Another specific example of the pattern to which this embodiment can be applied is a pattern for monitoring the dose (exposure amount reference pattern).

  When the resist pattern includes a pattern for forming an exposure amount reference pattern, a pattern 2P4 is formed under the conditions of a large lithography margin as shown in FIG. As shown in FIG. 21, the exposure amount reference pattern can be easily formed by converting the pattern 2 </ b> P <b> 4 ′ having a dimension in consideration of the processing conversion difference by the additional processing. In FIG. 21, the pattern drawn with a broken line shows the pattern before the addition process.

  After the resist pattern including the pattern 2P4 'is formed, a process of forming a film pattern to be processed (exposure amount reference pattern) by etching the film to be processed using the resist pattern as a mask continues.

(Second Embodiment)
FIG. 22 is a diagram schematically showing a flow of a pattern correction method according to the second embodiment of the present invention.

  The correction method according to the present embodiment is a pattern correction method (Japanese Patent Laid-Open No. 2002-318448) called so-called tandem OPC, which is an additional process (FIG. 22 is a shock absorber process).

  First, correction rules (rule-based correction) or correction models (model-based correction) are set in the order of wafer etching process, shock absorber process, lithography process (process related to exposure mask manufacturing), and proximity effect correction Etc. are corrected. The flow on the right side of FIG. 22 shows both the evaluation wafer and the product.

  Each of the above processes progresses with the times, and even after the correction rule / correction model is determined once, there is a high possibility that development will be advanced toward higher accuracy. That is, once the correction rule / correction model is determined, the process may change.

  Here, in the case of the prior art, when a change occurs in the lithography process, for example, the OPC rule / OPC model as the correction rule / correction model is corrected (reset) for the lithography process, and the proximity effect correction of the lithography process is performed. Done. Proximity effect correction in a lithography process is time consuming and expensive.

  Therefore, in the present embodiment, when a change occurs in the lithography process after the correction rule / correction model is once determined, a process consisting of a film to be processed obtained by a wafer etching process immediately before the change occurs. The correction rule / correction model of at least one of the wafer etching process and the shock absorber process is modified (reset) so that a processed film pattern having substantially the same dimensions as the film pattern is obtained. At this time, the correction rule / correction model of the lithography process is not corrected (reset).

  Therefore, according to the present embodiment, even if a change occurs in the lithography process after the correction rule / correction model is determined, relative correction is performed without correcting the correction rule / correction model of the lithography process, which takes time and cost. By correcting the correction rule / correction model of at least one of the wafer etching process and the shock absorber process that does not take time and cost, a new correction rule / correction model can be created relatively easily and in a short time.

  On the other hand, when a change occurs in a process other than the lithography process, the correction rule / correction model is corrected for the process in which the change has occurred, as in the prior art. The change of the correction rule / correction model of the shock absorber process is required when, for example, the machining conversion difference changes due to a change in the apparatus to be used.

  Depending on the process, there is a possibility that either the correction rule or the correction base is good, but the determination is based on, for example, the dependency of the OPC Design Space (abbreviated as Space in the figure) shown in FIG. I can judge. By selecting an appropriate OPC method (OPC rule base or OPC model base) in each process and optimizing the OPC model and rules, it is possible to improve the accuracy of OPC.

  When the process matures, the shock absorber process can be omitted finally.

(Third embodiment)
23 to 26 are plan views schematically showing the method for manufacturing the semiconductor device according to the third embodiment of the present invention.

  In the present embodiment, a method for manufacturing a semiconductor device will be described in the case where the processing conversion difference differs depending on the location in the chip.

[FIG. 23]
Reference numeral 31 indicates a chip including a film to be processed and a film (for example, a silicon nitride film) to be a hard mask formed on the film to be processed. The chip 31 is divided into a plurality of regions (first to Nth blocks). For example, the chip 31 is divided into N blocks for processing conversion discrimination.

[FIG. 24]
First, a first resist film is formed on a film serving as a hard mask (hereinafter referred to as a hard mask film).

  Next, the first resist film on the first block is selectively exposed, and further the first resist film is developed, whereby the first pattern in which the pattern is selectively present on the first block is obtained. A resist pattern is formed. The hard mask film in the second to Nth blocks is covered with the first resist pattern.

  Next, the dimension of the pattern formed on the first block is measured.

  Next, based on the measurement result, the pattern formed on the first block is formed so that a film pattern to be processed having a desired dimension (design dimension) is formed in the first block. The additional processing for reducing the processing conversion difference described in the first embodiment is performed.

  Next, the hard mask film is etched using the resist pattern including the pattern subjected to the additional process as a mask, thereby forming a first film pattern to be processed in the first block.

  Through the above steps, a first film pattern to be processed can be easily formed in the first block with a sufficiently small processing conversion difference.

[FIG. 25]
Next, a second resist film is formed on the hard mask film.

  Next, the second resist film on the second block is selectively exposed, and further, the second resist film is developed, whereby the second pattern film is selectively present on the second block. A resist pattern is formed. The hard mask film in the first and third to Nth blocks is covered with the second resist pattern.

  Next, the dimension of the pattern formed on the second block is measured.

  Next, based on the measurement result, the pattern formed on the second block is formed so that a film pattern to be processed having a desired dimension (design dimension) is formed in the second block. The additional processing for reducing the processing conversion difference described in the first embodiment is performed.

  Next, the hard mask film is etched using the resist pattern including the pattern subjected to the additional treatment as a mask, thereby forming a second film pattern to be processed in the second block.

  Through the above steps, a second film pattern to be processed can be easily formed in the second block with a sufficiently small processing conversion difference.

[FIG. 26]
Thereafter, similarly, the third to Nth film pattern to be processed is formed in the third to Nth blocks.

  FIG. 27 shows variations in pattern dimensions when the manufacturing method of the present embodiment is applied when the shapes and dimensions of the patterns in all the blocks are the same (for example, memory cells). From FIG. 27, it can be seen that the variation in pattern dimensions in the first to Nth blocks is sufficiently reduced. On the other hand, as shown in FIG. 28, the variation in pattern dimensions when the conventional manufacturing method (without the additional processing of the first embodiment) was applied was large.

(Fourth embodiment)
FIG. 29 is a flowchart showing a program according to the fourth embodiment of the present invention. Here, the program related to the semiconductor device manufacturing method of the first embodiment will be described. However, the program related to the semiconductor device manufacturing method of the third embodiment to which the semiconductor device manufacturing method of the first embodiment is applied. It can carry out similarly about.

  First, the dimensions 2L1 and 2L2 of the patterns 2P1 and 2P2 in the resist pattern 2P before the addition process formed in the process of FIG. 2 are acquired using a known measuring apparatus (step S1).

  Next, the dimensions 1L1 and 1L2 of two patterns in the processed film pattern corresponding to the patterns 2P1 and 2P2 formed by etching the processed film 1 using the resist pattern 2P before the addition process as a mask, Estimated based on the dimensions 2L1 and 2L2 (step S2). The estimation of the dimensions 1L1 and 1L2 is performed based on, for example, calculation or a previously created table.

  Finally, | 1L1′−Ld | <| 1L1−Ld | and | 1L2′−Ld | <| 1L2−Ld | are satisfied, and the amount of variation in the dimensions of the patterns 2P1 and 2P2 in the resist pattern 2P caused by the addition process Is determined (step S3).

  Here, 1L1 ′ and 1L2 ′ are formed in the processed film pattern corresponding to the patterns 2P1 ′ and 2P2 ′ formed by etching the processed film 1 using the resist pattern 2P after the addition process as a mask, respectively. Are the dimensions of the two patterns.

  Thereafter, the additional process described in the first embodiment is performed based on the dimensional variation determined in step S3.

  The program according to the present embodiment is implemented using hard wafer resources such as a CPU and a memory in a computer (an external memory may be used in combination). The CPU reads necessary data from the memory and performs the above steps (procedures) on the data. The result of each step (procedure) is temporarily stored in the memory as necessary, and is read when needed in another step (procedure).

  The embodiment described above can be summarized as follows.

(1) In a method of manufacturing a semiconductor device for forming a semiconductor device pattern on a substrate, a lithography process for forming a resist pattern on a resist film formed on a film to be processed, and a process to be formed by the lithography process Using the resist pattern on the film as a mask, processing the processed film to form a pattern, and between the lithography process and the etching process, so that the processed film pattern after the etching process has a desired dimension Includes a resist slimming process and a resist shrink process, which are additional processes for changing the shape of the resist pattern formed by the lithography process.

(2) In a method of manufacturing a semiconductor device for forming a semiconductor device pattern on a substrate, a lithography process for forming a line-and-space resist pattern on a resist film formed on a lithography work film, and the lithography process A resist line and space pattern after the lithography process is formed between the etching process for forming the pattern by processing the processed film using the resist pattern on the formed film as a mask, and the lithography process and the etching process. Then, an additional step for changing the shape of the resist pattern formed by the lithography step is performed so as to have the same dimension as the processed film line and space pattern after the etching step.

(3) In a method of manufacturing a semiconductor device for forming a semiconductor device pattern on a substrate, a lithography step of forming a substantially 1: 1 line and space resist pattern on a resist film formed on a film to be processed; Between an etching process for forming a pattern by processing a film to be processed using a resist pattern on the film to be processed formed by the lithography process as a mask, and approximately 1 after the lithography process. The resist pattern shape formed by the lithography process is changed so that the processed film line and space pattern after the etching process becomes a substantially 1: 1 line and space pattern. An additional process is performed.

(4) In a manufacturing method of a semiconductor device for forming a semiconductor device pattern on a substrate, a lithography process for forming a resist pattern on a resist film formed on a film to be processed, and a process to be formed by the lithography process An etching process for forming a pattern by processing a film to be processed using a resist pattern on the film as a mask, and an addition for changing the shape of the resist pattern formed by the lithography process between the lithography process and the etching process. In the process, when a dimensional difference between the resist pattern after the lithography process and the film pattern to be processed after the etching process is defined as a process conversion difference δ, a reverse addition process for canceling the process conversion difference δ is performed.

(5) In a method of manufacturing a semiconductor device for forming a semiconductor device pattern on a substrate, a lithography process for forming a resist pattern on a resist film formed on a film to be processed, and a process formed by the lithography process An etching process for forming a pattern by processing a film to be processed using a resist pattern on the film as a mask, and an addition for changing the shape of the resist pattern formed by the lithography process between the lithography process and the etching process. In the process, when the dimensional difference between the resist pattern after the lithography process and the processed film pattern after the etching process is defined as a process conversion difference δ, a process conversion difference is obtained so as to obtain a desired exposure margin and focus tolerance. A reverse addition process for canceling δ is performed.

(6) In a method of manufacturing a semiconductor device for forming a semiconductor device pattern on a substrate, a lithography process for forming a resist pattern on a resist film formed on a film to be processed, and a process to be formed by the lithography process An etching process for forming a pattern by processing a film to be processed using a resist pattern on the film as a mask, and an addition for changing the shape of the resist pattern formed by the lithography process between the lithography process and the etching process. In the process, when the dimensional difference between the resist pattern after the lithography process and the processed film pattern after the etching process is defined as a process conversion difference δ, a reverse addition process is performed to offset the process conversion difference δ, and the litho margin is reduced. Compensates for processing conversion differences in the pattern to be measured.

(7) In a method of manufacturing a semiconductor device for forming a semiconductor device pattern on a substrate, a lithography process for forming a resist pattern on a resist film formed on a film to be processed, and a substrate formed by the lithography process A resist pattern shape formed by the lithography process is changed between an etching process for forming a pattern by processing a film to be processed using a resist pattern on the processed film as a mask, and the lithography process and the etching process. In the additional step, when the dimensional difference between the resist pattern after the lithography step and the film pattern to be processed after the etching step is defined as a processing conversion difference δ, a reverse additional step is performed to offset the processing conversion difference δ, and exposure is performed. Compensates for pattern processing conversion differences that serve as a reference for quantity.

(8) The pattern correction method is a first method in which a measured machining process conversion difference or a value calculated based on the machining process conversion difference is used as a correction value for correcting a corresponding pattern in the design pattern. A correction process, a second process using a measured additional process conversion difference or a value calculated based on the additional process conversion difference as a correction value for correcting a corresponding pattern in the design pattern, and a measured lithography A mask data correction method comprising: a third step of using a conversion difference equivalent to a process or a value calculated based on a conversion difference equivalent to the lithography process as a correction value for correcting a corresponding pattern in a design pattern. When the conversion difference δ is changed, only the first correction process and the second correction process are corrected again without changing the third correction process. Thus, pattern formation equivalent to that before re-correction is realized.

(9) In a method of manufacturing a semiconductor device including a pattern having a different processing conversion difference depending on a location in the chip, after a hard mask is applied to the film to be processed, the chip is divided into N regions for processing conversion discrimination. The amount of the resist coating step, the first block exposure step, the first block dimension measurement step, and the first block addition step amount are calculated for each block divided into N blocks. A step of performing an additional step on the first block, a step of processing the hard mask of the first block, a step of applying a resist, a step of applying a resist, and a step of performing second block exposure A step of measuring the dimensions of the second block, a step of calculating the amount of the second block addition step, a step of applying the addition step to the second block, and a hard mask of the second block The process to be processed and the sequential process are repeated up to N blocks, the amount of additional process is controlled, the pattern size before processing of each block in the chip is controlled, and the dimensional variation after processing in the chip is controlled. The pattern formation method characterized by the above-mentioned.

(10) The program forms a resist on a film to be processed, forms a resist pattern on the resist by a lithography technique, and performs exposure under exposure conditions of a predetermined exposure margin in a pattern forming method for processing the film to be processed. A step, a step of measuring a pattern dimension after lithography, a step of calculating a process amount that cancels the processing conversion difference δ using the obtained dimension, a step of performing an additional process with the calculated process amount, The pattern size of the film to be processed is controlled by controlling the amount of this additional process.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the components without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

  In addition, various modifications can be made without departing from the scope of the present invention.

Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment following FIG. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment following FIG. Sectional drawing which shows a mode that the electrode or wiring which consists of a semiconductor film or a electrically conductive film was formed as a to-be-processed film pattern, when a to-be-processed film is a semiconductor film or an electrically conductive film. Sectional drawing which shows a mode that the wiring groove | channel was formed in the surface of an interlayer insulation film as a to-be-processed film pattern when a to-be-processed film is an interlayer insulation film. Sectional drawing which shows a mode that the via hole was formed in the interlayer insulation film as a to-be-processed film pattern when a to-be-processed film is an interlayer insulation film. When the film to be processed is a semiconductor film or a laminated film of a conductive film and an insulating film, a gate structure including a gate electrode made of a semiconductor film or a conductive film and a gate insulating film made of an insulating film is formed as a film pattern to be processed Sectional drawing which shows a state made. When the film to be processed is a laminated film of a first insulating film and a semiconductor film or a conductive film and a second insulating film, a gate upper insulating film and a semiconductor film or Sectional drawing which shows a mode that the gate structure containing the gate electrode which consists of a electrically conductive film, and the gate insulating film which consists of a 2nd insulating film was formed. When the film to be processed is a stacked film of a conductive film, a semiconductor film, and an insulating film, the processed film pattern includes a first gate electrode made of a conductive film, a second gate electrode made of a semiconductor film, and an insulating film. Sectional drawing which shows a mode that the gate structure containing a gate insulating film was formed. Sectional drawing which shows the formation method of the L / S pattern which concerns on embodiment. Sectional drawing which shows the formation method of the L / S pattern which concerns on embodiment following FIG. Sectional drawing which shows the formation method of the L / S pattern which concerns on embodiment following FIG. Sectional drawing of the resist pattern which is going to form, and the figure which shows the tolerance | permissible_range of the dose amount and focus range which can be used when forming this resist pattern by the method of a comparative example. FIG. 4 is a cross-sectional view of a resist pattern to be formed and a diagram showing an allowable range of a dose amount and a focus range that can be used when the resist pattern is formed by the method of the embodiment. The figure which shows the tolerance | permissible_range of the dose amount and focus range which can be used in the case of forming a lithography margin rate-limiting pattern and this lithography margin rate-limiting pattern. FIG. 4 is a cross-sectional view of a resist pattern of an embodiment for forming a lithography margin rate-limiting pattern and a diagram showing an allowable range of a dose amount and a focus range that can be used when the resist pattern is formed by the method of the embodiment. Sectional drawing which shows the resist pattern to which the addition process of embodiment for forming the lithography margin rate limiting pattern was performed. The top view which shows the example of attachment. The top view which shows the other example of attachment. FIG. 4 is a cross-sectional view of a resist pattern of an embodiment for forming an exposure amount reference pattern, and a diagram showing an allowable range of a dose amount and a focus range that can be used when the resist pattern is formed by the method of the embodiment. Sectional drawing which shows the resist pattern in which the addition process of embodiment for forming an exposure amount reference | standard pattern was performed. The figure which shows typically the flow of the pattern correction method which concerns on the 2nd Embodiment of this invention. FIG. 7 is a plan view schematically showing a method for manufacturing a semiconductor device according to a third embodiment of the present invention. FIG. 24 is a plan view schematically showing the method for manufacturing the semiconductor device according to the third embodiment following FIG. 23. The top view which shows typically the manufacturing method of the semiconductor device which concerns on 3rd Embodiment following FIG. The top view which shows typically the manufacturing method of the semiconductor device which concerns on 3rd Embodiment following FIG. When the shape and dimension of the pattern in all the blocks are the same, the variation of the pattern dimension when the manufacturing method of this embodiment is applied is shown. When the shapes and dimensions of the patterns in all the blocks are the same, variations in the pattern dimensions when the conventional manufacturing method is applied are shown. The flowchart which shows the program which concerns on the 4th Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Processed film, 1P ... Processed film pattern, 1P1 ... (2nd) gate electrode, 1P2 ... Gate insulating film, 1P3 ... Gate upper insulating film, 1P4 ... 1st gate electrode, 2 ... Resist film, 2P , 2P '... resist pattern, 2P1, 2P2, 2P3, 2P4, 2P1', 2P2 ', 2P3', 2P4 '... pattern, 10 ... usable dose and focus range, 21, 22 ... line pattern, 23 ... Attaching, 24, 25 ... hole pattern, 26 ... attaching, 31 ... chip.

Claims (5)

Forming a resist pattern including a pattern on the film to be processed;
Changing the size of the pattern;
Etching the film to be processed with the resist pattern having the pattern size changed as a mask,
The step of changing the size of the pattern is the size of the pattern so that the pattern made of the film to be processed corresponding to the pattern formed by the step of etching the film to be processed has a desired dimension. A method for manufacturing a semiconductor device, characterized in that a change amount is determined. The size of the pattern and the amount of change are as follows:
The lithography margin when the resist pattern before changing the size of the pattern is formed by a lithography process is larger than the lithography margin when the resist pattern after changing the size of the pattern is formed by a lithography process. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is selected to be large. A first process relating to the manufacture of an exposure mask; a second process relating to a change in the size of a pattern contained in a resist pattern formed using the exposure mask; and the resist in which the size of the pattern has been changed. Preparing a process group including a third process related to etching of the film to be processed performed using a pattern as a mask;
When a change occurs in the third process, the film to be processed has substantially the same dimensions as the film pattern to be processed that is obtained by the third process before the change occurs in the first process. Correcting the correction rule or the correction model of the second process without correcting the correction rule and the correction model of the first process so that a pattern can be obtained. . Dividing a chip including a film to be processed and a film serving as a hard mask formed on the film to be processed into a plurality of blocks;
For each of the plurality of blocks, a resist film is formed on the hard mask film, the resist film on the block is selectively exposed, the resist film is developed, and a pattern is selected on the block A resist pattern that is present on the block is measured, and the dimension of the pattern formed on the block is measured. Based on the measurement result, a film pattern to be processed having a desired dimension is formed in the block. A process of changing the size of the pattern according to claim 1 is performed on the pattern formed on the block, and the hard pattern is formed using the resist pattern including the pattern subjected to the process as a mask. Etching the film to be a mask to form the hard mask film;
Forming a processed film pattern made of the processed film by etching the processed film using the hard mask film as a mask. Forming a resist pattern including a pattern on the film to be processed;
Changing the size of the pattern;
Etching the film to be processed using the resist pattern whose pattern size has been changed as a mask, and a program relating to a method of manufacturing a semiconductor device,
The computer executes a procedure for determining the amount of change in the size of the pattern so that the pattern made of the processed film corresponding to the pattern formed by the step of etching the processed film has a desired dimension. Program to let you.

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