JP2007150166A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a pattern within limits of lithography by effectively using a side wall machining process even for various fine hole patterns having random patterns in addition to periodic patterns. <P>SOLUTION: The method of manufacturing a semiconductor device using the side wall machining process comprises a step of forming a first sacrificial film which has a period twice as long as that of a desired sacrificial film pattern, and whose line consists of a line and a space thinner than a space on a processed film 11; forming a second sacrificial film 15 on a flank part of the first sacrificial film, and then removing the first sacrificial film; then forming a resist pattern 16 for processed film on the processed film 11 and second sacrificial film 15; and selectively etching the processed film 11 by using the resist pattern 16 and second sacrificial film 15 as a mask to form a hole pattern. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor device for forming an integrated circuit pattern having a resolution smaller than a critical resolution dimension determined by lithography, and more particularly to a method of manufacturing a semiconductor device using a side wall processing process of a sacrificial film pattern.

  Recent progress in semiconductor manufacturing technology is very remarkable, and semiconductors with a minimum processing dimension of 0.1 μm are mass-produced. Such miniaturization is realized by dramatic progress in fine pattern formation technology such as mask process technology, lithography process technology, and etching process technology. In particular, flash memory devices that have undergone dramatic development are required to have dimension values that exceed the resolution limit of optical lithography in order to achieve a large-scale market demand. For this reason, it is no longer possible to follow the miniaturization by the conventional optical lithography technology, and it is essential to introduce a new miniaturization process.

  As a technique for reducing the pattern pitch, a method of dividing the pattern and performing multiple exposure has also been proposed. However, when considering the relationship between the upper and lower layers of the part with periodicity, in principle it is not possible to tolerate misalignment or extremely tight misalignment accuracy is required. Is difficult.

  As one of candidates for a new process for solving the above problem, there is a method called a sidewall processing process (for example, see Patent Document 1). The side wall processing process will be described in the case where the design pattern portion has a convex shape like the gate layer. This is because a resist pattern is formed in a pattern portion adjacent to a position where a convex pattern is to be formed (finally becomes a concave pattern), and the resist pattern is processed to have a sacrificial film pattern having a desired dimension in the concave portion. This is a process of forming a wiring pattern by processing only the lower side conductive film material using the remaining sidewall pattern as a mask.

  FIG. 28 shows a gate formation method using a sidewall processing process. In the figure, 50 is a semiconductor substrate, 51 is an STI (Shallow Trench Isolation) region, 52 is a gate insulating film, 53 is a gate electrode, 54 is a SiN film, 55 is a sacrificial film, and 56 is a sidewall film.

  First, the sacrificial film 55 is patterned by a lithography process. Next, a sidewall film 56 is formed on the sidewall of the patterned sacrificial film 55. When the sidewall material is formed to a desired thickness, the sidewall material formed on the portion other than the sidewall of the sacrificial film pattern is RIEed. Thereafter, the sacrificial film 55 is peeled off. As a result, a desired sidewall pattern can be formed on the hard mask (SiN film 54). Next, the pattern is transferred to the hard mask 54 using the sidewall pattern as a mask, and the hard mask 54 is slimmed to finally form a gate pattern of a desired size. The feature of the sidewall processing is that the gate dimension is determined only by the film thickness of the sidewall material (regardless of the dimension of lithography), so that dimensional controllability is high and low LWR (Line Wedge Raughness) can also be expected. is there.

However, this process is very effective for forming a line-and-space pattern having a fine and one-dimensional periodic structure, but for forming other patterns, particularly random fine hole patterns. Not applicable.
US patent (US 6,475,891)

  Thus, conventionally, there is a method of forming a pattern below the resolution limit by lithography using a sidewall processing process, but this type of method has a problem that it cannot be applied to formation of a random fine hole pattern or the like.

  The present invention has been made in view of the above circumstances, and its object is to effectively use the sidewall processing process for various fine hole patterns having random patterns in addition to the periodic patterns. Then, it is providing the manufacturing method of the semiconductor device which can form the pattern below the limit of lithography.

  In order to solve the above problems, the present invention adopts the following configuration.

  That is, one embodiment of the present invention is a method for manufacturing a semiconductor device, which has a cycle twice as long as a desired sacrificial film pattern on a film to be processed, and the line portion is narrower than the space portion. A step of forming a first sacrificial film of and space, a step of removing the first sacrificial film after forming a second sacrificial film on a side surface portion of the first sacrificial film, After removing the sacrificial film, a step of forming a resist pattern for the processed film on the processed film and the second sacrificial film, and selecting the processed film using the resist pattern and the second sacrificial film as a mask And etching to form a hole pattern.

  Another embodiment of the present invention is a method for manufacturing a semiconductor device, which has a cycle twice as long as a desired sacrificial film pattern on a film to be processed, and a line portion is larger than a space portion. Forming a thin line and space first sacrificial film, forming a second sacrificial film on a side surface of the first sacrificial film, and then removing the first sacrificial film; A step of forming a separation layer on the film to be processed and the second sacrifice film after the removal of the sacrificial film, and a period twice as long as a desired sacrifice film pattern on the separation layer; A step of forming a third sacrificial film having a direction different from the pattern of the first sacrificial film and having a line portion that is narrower than the space portion and a side portion of the third sacrificial film; Removing the third sacrificial film after forming the fourth sacrificial film; and After the sacrificial film is removed, a process film resist pattern is formed on the separation layer and the fourth sacrificial film, and the separation layer is selectively used with the resist pattern and the sacrificial film as a mask. And a step of selectively etching the film to be processed using the resist pattern and the sacrificial films of 2 and 4 as a mask to form a hole pattern.

  According to the present invention, it is possible to form a fine pattern below the resolution limit of an exposure apparatus, particularly a fine and highly random hole pattern, which has been difficult to realize by a conventional method. Therefore, the device pattern can be further miniaturized and the chip size can be reduced accordingly.

  The details of the present invention will be described below with reference to the illustrated embodiments.

(First embodiment)
1 to 8 are diagrams for explaining a manufacturing process of a semiconductor device according to the first embodiment of the present invention. In each figure, (a) is a plan view, and (b) is B in (a). -B 'sectional drawing, (c) is CC' sectional drawing of (a).

  This embodiment is an example applied to a contact layer of a via of a NAND flash memory as a technique for forming a hole pattern below the resolution limit by using a sidewall processing process. 1 to 8 show a cell part 1, a sense amplifier part 2, and a peripheral part 3 of a NAND flash memory having a hole pattern with a pitch less than the resolution limit.

  As patterns to be formed, it is necessary to form three kinds of pattern types when roughly classified. That is, the cell portion 1 has a periodic hole pattern that is less than the resolution limit of the exposure apparatus (half pitch F) in the one-dimensional direction, and an isolated hole pattern that has a size F that is less than the resolution limit in the sense amplifier portion 2. is there. The peripheral portion 3 is a hole pattern that is not less than the resolution limit but must be formed with a dense to sparse through pitch of about 2F.

  A method for forming the hole pattern will be described for each process according to FIGS.

  First, as shown in FIG. 1, a sacrificial film (first sacrificial film) 12 for processing the oxide film 11 is formed on a substrate on which an oxide film 11 as a film to be processed is formed in order to form a via contact. Form. Here, the sacrificial film 12 is polysilicon or amorphous silicon. Then, a 2F pitch resist pattern (sacrificial film resist pattern) 13 that is twice the desired half pitch F is formed on the sacrificial layer 12. At this time, by providing several or more dummy (shown by broken lines in the figure) adjacent to both sides of the isolated pattern of the sense amplifier unit 2, the isolated pattern of the sense amplifier unit 2 is made a part of the dense pattern. It is characteristic to form.

  Next, as shown in FIG. 2, resist slimming is performed on the resist pattern 13 until the pattern size becomes approximately half F. As this slimming step, for example, a dry process such as dry etching or ashing with ozone while irradiating UV light may be performed.

  Next, as shown in FIG. 3, the sacrificial film 12 is selectively etched using the resist pattern 13 as a mask, so that a desired side wall film thickness F is formed on the side wall portion of the sacrificial film 12 pattern. 2 sacrificial film) 15 is formed. Here, the sidewall film 15 is SiN, and the sacrificial film 12 is a material having a sufficient etching selectivity. Further, as a method for forming the sidewall film 15, the sidewall material may be left only on the sidewall portion of the sacrificial film 12 by performing etch back after depositing the sidewall material on the entire surface.

  Next, as shown in FIG. 4, the sacrificial film 12 is removed by etching. 4B and 4C, as can be seen from the BB ′ cross section and the CC ′ cross section, by performing the above steps, the sidewall film 15 reduces the resolution limit to a desired value or less. It is possible to form a basic portion of the pattern size F.

  Next, after a resist is applied on the substrate in order to select a desired hole portion, a resist pattern (resist pattern for processed film) 16 is formed as shown in FIG. That is, the cell portion 1 is formed with a slit pattern 16a for changing the major axis size of the hole into a desired pattern. With respect to the sense amplifier unit 2, an isolated hole pattern 16b is formed in which the minor axis direction has a size of about 2F and the major axis direction has a desired size. In the peripheral portion 3, a hole pattern 16 c having high randomness from dense to sparse is formed. It is important that these patterns have a dimension range in which a sufficient margin can be secured by the exposure apparatus used. When it is necessary to form a pattern with a sufficient margin, less than the resolution limit, or close to the resolution limit, it is classified as a pattern formed by the sidewall pattern or depending on the degree, as shown in FIG. As described above, various resist shrink processes (hole reduction processes) may be performed on the pattern shown in FIG.

  Next, as shown in FIG. 7, in the pitch direction (BB ′ and CC ′ direction) below the resolution limit of the exposure apparatus, the pattern of the sidewall film 15 is used as a mask material, and the other directions and the periphery. As for the pattern of the portion, the oxide film 11 is selectively etched using the resist pattern 16 as a mask material.

  By the above method, it is possible to form the hole patterns 21, 22, and 23 having a pitch below the resolution limit, which is difficult to form by the conventional method, as shown in FIG.

  As described above, according to the present embodiment, by utilizing the sidewall processing process effectively, the periodic hole pattern 21 having a size F equal to or smaller than the resolution limit of the cell unit 1 and the resolution limit of the sense amplifier unit 2 or less. An isolated hole pattern 22 having a size F and a hole pattern 23 having a size of about 2F in the peripheral portion 3 can be formed. That is, even for various fine hole patterns having a random pattern in addition to the periodic pattern, a pattern below the limit of lithography can be formed by effectively utilizing the sidewall processing process. Therefore, the device pattern can be further miniaturized and the chip size can be reduced accordingly.

(Second Embodiment)
9 to 14 are plan views showing manufacturing steps of the semiconductor device according to the second embodiment of the present invention. 1 to 8 are denoted by the same reference numerals, and detailed description thereof is omitted.

  This embodiment shows a modification of the first embodiment, and describes a case where there is a pattern below the resolution limit of the exposure apparatus in the peripheral portion.

  FIG. 9 corresponds to FIG. 1A, and a resist pattern 13 having a 2F pitch is formed on a part of the peripheral portion 3 in the same manner as the cell portion 1. FIG. 10 corresponds to FIG. 2A, and the resist pattern 13 is slimmed.

  FIG. 11 corresponds to FIG. 3A, and a side wall film 15 is formed on the side surface of the sacrificial film 12. Since the resist pattern 13 is also formed in the peripheral portion 3, the sidewall film 15 is also formed in the peripheral portion 3.

  FIG. 12 corresponds to FIG. 5A, and a resist pattern 16 is formed. The opening of the resist pattern 16 is the same as that of the first embodiment with respect to the cell portion 1 and the sense amplifier portion 2, but a hole pattern 16 c and a slit pattern 16 d are formed in the peripheral portion 3.

  FIG. 13 corresponds to FIG. 7A, and the oxide film 11 is selectively etched using the resist pattern 16 and the sidewall film 15 as a mask. FIG. 14 corresponds to FIG. 8A, in which the resist pattern 16 and the side wall film 15 are removed.

  In this manner, in addition to the hole pattern 21 in the cell portion 1 and the isolated hole pattern 22 in the sense amplifier portion 2, a dense hole pattern 24 and a rough hole pattern 25 can be formed in the peripheral portion 3.

  In the first and second embodiments, the isolated pattern of the cell part 1 and the sense amplifier part 2 is previously formed as a pattern below the resolution limit, and a part of the oxide film 11 is formed mainly with the side wall pattern. The other parts are formed only by the lithography process. However, the method of dividing the pattern is not limited to the above, and various modifications can be applied depending on the desired pattern layout.

  Although not described in detail in the above embodiment, the mask used in the lithography process is formed in advance by side wall processing according to a desired pattern size, and only in the lithography process. It is designed separately from the parts to be formed. As an example of a specific method, the pattern dimension is compared with the limit resolution dimension f of the exposure apparatus, and according to the dimension, grouping is performed on the group that mainly forms the sidewall pattern and the group that does not. To do.

  Then, based on the divided data, the one that mainly forms the sidewall pattern is derived, and further, a pattern after lithography and a mask pattern for forming the same are derived (specifically, as described in FIG. 1). Mask pattern data is created by performing processes such as generating dummy patterns at the periodic edges and generating dummy patterns at both ends if the pattern is a dense pattern to form a resist pattern. In addition, a pattern formed by lithography alone is manufactured in consideration of whether or not a shrink process is used.

(Third embodiment)
15 to 27 are plan views showing manufacturing steps of the semiconductor device according to the third embodiment of the present invention. 1 to 8 are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the present embodiment, a sidewall processing process is used as a method for forming a pattern below the resolution limit, and in particular, a random logic contact layer is created.

  FIG. 27 shows a final desired fine hole pattern. That is, many fine hole patterns 39 are formed in the oxide film 11. The hole pattern forming method will be described for each process according to FIGS.

  First, in order to form a pattern below the resolution limit in the vertical direction, as shown in FIG. 15, a sacrificial film 12 for processing the oxide film 11 is formed on the substrate on which the oxide film 11 as a film to be processed is formed. Form. Then, a vertical resist pattern 13 having a 2F pitch that is twice the desired half pitch F is formed on the sacrificial film 12.

  Next, as shown in FIG. 16, resist slimming is performed on the resist pattern 13 until the pattern size becomes approximately half F. Next, as shown in FIG. 17, the sacrificial film 12 is selectively etched using the resist pattern 13 as a mask to form a sidewall film 15 so that a desired sidewall film thickness F is formed on the pattern sidewall portion of the sacrificial film 12. To do. Thereafter, as shown in FIG. 18, the pattern of the sacrificial film 12 is removed by etching.

  By carrying out the above steps, it becomes possible to form a pattern of F below the desired resolution limit in the vertical direction.

  Next, as shown in FIG. 19, a side wall processed part for forming a pattern below the resolution limit in the vertical direction and a side wall processed part for forming a pattern below the resolution limit in the horizontal direction are separated. A separation film 31 is formed on the entire surface of the substrate.

  Next, as shown in FIGS. 20 to 24, in the horizontal direction as well as the vertical direction, a pattern of F below the desired resolution limit is formed. That is, after forming a sacrificial film (third sacrificial film) 32 on the separation film 31 as shown in FIG. 20, a resist pattern (resist pattern for sacrificial film) 33 is formed as shown in FIG. As shown in FIG. 22, the resist pattern 33 is slimmed. Next, after selectively etching the sacrificial film 32 using the resist pattern 33 as a mask as shown in FIG. 23, a side wall film (fourth sacrificial film) 35 is formed on the side wall of the sacrificial film 32, and further as shown in FIG. Then, the sacrificial film 32 is removed by etching.

  Next, as shown in FIG. 25, a resist is applied on the substrate in order to select a desired hole portion, and only a hole portion to be formed is selectively formed into a resist pattern (covered with a size of about 2F or larger). A processed film resist pattern) 36 is formed.

  Next, as shown in FIG. 26, for the holes selected in the lithography process, the isolation film 31 and the oxide film 11 are etched using the vertical side wall pattern and the horizontal side wall pattern as a mask.

  Thereafter, the vertical and horizontal side wall patterns and the resist pattern 36 are peeled off to form a hole pattern 39 having a pitch below the resolution limit, which is difficult to form by the conventional method, as shown in FIG. It becomes.

  As described above, according to the present embodiment, the hole pattern 39 having a size F equal to or less than the resolution limit in both the vertical direction and the horizontal direction can be formed by effectively using the sidewall processing process. Therefore, the device pattern can be further miniaturized and the chip size can be reduced accordingly.

(Modification)
In addition, this invention is not limited to each embodiment mentioned above. In the embodiment, as a process of forming the first sacrificial film of line and space, resist pattern formation, resist pattern slimming, and selective etching using the resist pattern as a mask are performed. However, the process is not necessarily limited to these processes. Absent. Any method can be used as long as the first sacrificial film has a period twice as long as a desired sacrificial film pattern and the line part can be formed into a line-and-space pattern thinner than the space part.

  The present invention is not limited to a NAND flash memory, but can be applied to the formation of hole patterns in system LSI circuits and other various semiconductor devices. Furthermore, the material of the film to be processed and the material of the sacrificial film can be appropriately changed according to the specifications. However, the first and second sacrificial films need to be made of a material having a sufficient etching selectivity, and similarly, the third and fourth sacrificial films need to be made of a material having a sufficient etching selectivity.

  In addition, various modifications can be made without departing from the scope of the present invention.

The top view and sectional drawing which show the semiconductor manufacturing process concerning 1st Embodiment. The top view and sectional drawing which show the semiconductor manufacturing process concerning 1st Embodiment. The top view and sectional drawing which show the semiconductor manufacturing process concerning 1st Embodiment. The top view and sectional drawing which show the semiconductor manufacturing process concerning 1st Embodiment. The top view and sectional drawing which show the semiconductor manufacturing process concerning 1st Embodiment. The top view and sectional drawing which show the semiconductor manufacturing process concerning 1st Embodiment. The top view and sectional drawing which show the semiconductor manufacturing process concerning 1st Embodiment. The top view and sectional drawing which show the semiconductor manufacturing process concerning 1st Embodiment. The top view which shows the semiconductor manufacturing process concerning 2nd Embodiment. The top view which shows the semiconductor manufacturing process concerning 2nd Embodiment. The top view which shows the semiconductor manufacturing process concerning 2nd Embodiment. The top view which shows the semiconductor manufacturing process concerning 2nd Embodiment. The top view which shows the semiconductor manufacturing process concerning 2nd Embodiment. The top view which shows the semiconductor manufacturing process concerning 2nd Embodiment. The top view which shows the semiconductor manufacturing process concerning 3rd Embodiment. The top view which shows the semiconductor manufacturing process concerning 3rd Embodiment. The top view which shows the semiconductor manufacturing process concerning 3rd Embodiment. The top view which shows the semiconductor manufacturing process concerning 3rd Embodiment. The top view which shows the semiconductor manufacturing process concerning 3rd Embodiment. The top view which shows the semiconductor manufacturing process concerning 3rd Embodiment. The top view which shows the semiconductor manufacturing process concerning 3rd Embodiment. The top view which shows the semiconductor manufacturing process concerning 3rd Embodiment. The top view which shows the semiconductor manufacturing process concerning 3rd Embodiment. The top view which shows the semiconductor manufacturing process concerning 3rd Embodiment. The top view which shows the semiconductor manufacturing process concerning 3rd Embodiment. The top view which shows the semiconductor manufacturing process concerning 3rd Embodiment. The top view which shows the semiconductor manufacturing process concerning 3rd Embodiment. Sectional drawing for demonstrating the conventional side wall processing process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Cell part 2 ... Sense amplifier part 3 ... Peripheral part 11 ... Oxide film (film to be processed)
12. Sacrificial film (first sacrificial film)
13. Resist pattern (resist pattern for sacrificial film)
15 ... sidewall film (second sacrificial film)
16 ... Resist pattern (resist pattern for film to be processed)
16a ... cell part slit pattern 16b ... sense amplifier part isolated hole pattern 16c ... peripheral hole pattern 16d ... peripheral slit pattern 21 ... periodic hole pattern 22 ... isolated hole pattern 23 ... peripheral hole pattern 31 ... separation film 32 ... sacrificial film (Third sacrificial film)
33 ... Resist pattern (resist pattern for sacrificial film)
35 ... sidewall film (fourth sacrificial film)
36 ... Resist pattern (resist pattern for film to be processed)
39 ... Fine hole pattern

Claims (5)

Forming a first sacrificial film having a cycle twice as long as a desired sacrificial film pattern and having a line portion narrower than the space portion on the work film;
Removing the first sacrificial film after forming the second sacrificial film on the side surface of the first sacrificial film;
Forming a resist pattern for a processed film on the processed film and the second sacrificial film after removing the first sacrificial film;
Forming a hole pattern by selectively etching the film to be processed using the resist pattern and the second sacrificial film as a mask;
A method for manufacturing a semiconductor device, comprising: Forming a first sacrificial film having a cycle twice as long as a desired sacrificial film pattern and having a line portion narrower than the space portion on the work film;
Removing the first sacrificial film after forming the second sacrificial film on the side surface of the first sacrificial film;
Forming a separation layer on the workpiece film and on the second sacrificial film after removing the first sacrificial film;
On the separation layer, the first sacrificial film pattern has a period twice that of the desired sacrificial film pattern, the direction is different from that of the first sacrificial film pattern, and the line portion is narrower than the space portion. Forming a sacrificial film of 3;
Removing the third sacrificial film after forming the fourth sacrificial film on the side surface of the third sacrificial film;
Forming a resist pattern for a film to be processed on the separation layer and the fourth sacrificial film after removing the third sacrificial film;
The isolation layer is selectively etched using the resist pattern and the 4 sacrificial film as a mask, and then the film to be processed is selectively etched using the resist pattern and the 2 and 4 sacrificial films as a mask. Forming a pattern;
A method for manufacturing a semiconductor device, comprising: As a step of forming the line and space first sacrificial film,
After forming the first sacrificial film on the processed film, a line and space sacrificial film resist pattern having a period twice as long as the desired sacrificial film pattern is formed on the first sacrificial film, and then sacrificial 3. The method of manufacturing a semiconductor device according to claim 1, wherein the film resist pattern is subjected to slimming processing, and then the first sacrificial film is selectively etched using the sacrificial film resist pattern as a mask.   3. The method of manufacturing a semiconductor device according to claim 1, wherein a resist shrink process is performed on the resist pattern for a film to be processed.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the film to be processed is a non-conductive film, and the hole pattern is provided in a cell portion of a NAND flash memory.

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