JPH10171855A - Device for extracting circuit parameter and method for calculating delay - Google Patents

Abstract

PROBLEM TO BE SOLVED: To extract and correct circuit parameters for the purpose of correcting the difference between the design values of circuit constants generating finish values of a pattern and the finish values. SOLUTION: A circuit parameter extracting device is provided with a step 112B being a means for judging whether or not a design value DD3 of an extracted distance between gate electrode writings is larger than a normal value (h), a step 114B being a means for judging the presence of the influence of the reflection and interference of an exposed light when the DD3 <=(h), and for calculating a finish value LP3 for a design value LD3 (=g) of gate electrode writing width as Lp3 =g-δg by a preliminarily decided coefficient δ3 (0<δ3 <1), and a step 113B being a means for deciding a finish value L3 of the width of a gate electrode wiring 1, that is, gate width being a circuit parameter as L3 =Lp3 when DD3 <=(h), and for deciding it as L3 =LD3 when DD3 >(h).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit parameter extracting device and a delay calculating method for calculating a signal delay in an integrated circuit formed by a fine pattern with high accuracy.

[0002]

2. Description of the Related Art In recent years, as the demand for higher integration of integrated circuits has increased, patterns have become finer. When the pattern is miniaturized, the pattern dimensions such as the gate width, the gate distance, the metal wiring width, and the metal wiring distance in the integrated circuit and the wavelength of the exposure light in the photolithography process become the same length. Therefore, under the influence of exposure light reflection, interference, and the like, pattern processing accuracy largely depends on circuit parameters representing layout data of the integrated circuit, such as pattern dimensions and pattern shapes. In each photolithography step of forming a pattern, the remaining region of the resist determines, for example, the opening of the field oxide film. The opening serves as an effective pattern of the diffusion layer. Alternatively, the remaining region of the resist becomes an effective pattern of the gate electrode wiring and the metal wiring. In the case of a resist pattern having a pattern very close to the periphery, the size of the diffusion layer is reduced in the diffusion layer due to the proximity effect in which the resist pattern becomes thinner due to the reflection and interference of exposure light, and the gate electrode wiring In addition, in metal wiring, the wiring width is reduced. On the other hand, in the case of an isolated pattern having no other pattern in the periphery, the resist is excessively removed by the over-etching in the etching step, so that the size and shape of the pattern are difficult to appear.

FIGS. 9 to 11 show the influence of peripheral patterns and pattern dimensions on a MOSFET having a gate electrode wiring 1, a metal wiring 2, and a diffusion layer 3. FIG. FIG.
FIGS. 10A and 10B show series MOSFETs.
(B) shows the difference between the design value of the gate electrode wiring width and the finished value of the isolated MOSFET. FIG. 11 (a),
(B) Narrow channel MOSFET with small channel width
2 shows the deformation (rounding) of the diffusion layer region and the difference between the design dimension and the finished dimension.

A multi-input NAN shown in FIGS. 9 (a) and 9 (b)
D-gate nMOSFET, multi-input NOR gate pM
In a series MOSFET such as an OSFET, since the distance between the gate electrode wirings 1 is small, the wiring width of the design value L _D1 is reduced by ΔL ₁ on both sides to the finished value L _P1 due to the proximity effect. Further, since the influence of the proximity effect depends on the distance between the wirings, if the distance between the wirings is different, the width of the gate electrode wiring varies. In the isolated MOSFETs such as the inverters shown in FIGS. 10A and 10B, the gate electrode wiring 1 is an isolated pattern. _Therefore , the wiring width of the design value L _D2 is reduced by ΔL _{2 on} both sides due to over-etching. To the finished value L _P2 . Since the proximity effect and the overetching have different degrees of influence, the finished value of the gate electrode wiring width differs depending on the presence or absence of the adjacent gate electrode wiring pattern. That is, the finished value of the gate electrode wiring width, which is the gate length, varies depending on the distance from the adjacent gate electrode wiring, and differs depending on the presence or absence of the adjacent gate electrode wiring. Variations in the finished values and differences from the design values occur. Similarly, also in the metal wiring, a variation occurs in the finished value and a difference from the designed value occurs. Further, in the narrow channel MOSFET shown in FIGS. 11A and 11B, the concave portion of the pattern of the diffusion layer 3 that is the remaining portion of the resist is deformed (rounded) due to non-uniform etching, and the diffusion corresponding to the gate width is obtained. The design value W _D1 of the layer width is widened to the finish value W _P1 , and the gate width affecting the circuit constant changes.

[0005] Variations in gate length and metal wiring width and variations in gate width cause differences in electrical characteristics between the designed device and the finished device. That is, a characteristic error or a characteristic variation with respect to the design value occurs. In particular, in a submicron device having a gate length of 0.5 μm or less, the short-channel effect in which the threshold voltage decreases and the drain saturation current increases as the gate length becomes shorter becomes significant. It is a major source of delay fluctuations. If a circuit constant is set without reflecting an actual finished value, a characteristic error increases. Therefore, an excessive design margin must be set at the time of circuit design in order to absorb variations and variations in the finished value. In the past, in order to avoid this, when creating mask data for photomask production from layout data, the dimensions and shape of the pattern were changed in consideration of the distance between patterns and avoidance of pattern deformation, and Had been created.

[0006]

By the way, when mask data is created by changing a pattern, that is, data correction at the time of creating a photomask has been performed on full chip data. In this case, a large amount of layout data is read, the pattern arrangement is analyzed, and the dimension and shape of the pattern are corrected to generate large-scale mask data, so that a long time is required for the correction processing. For example,
It takes about several tens of hours to correct the dimensions of the gate electrode in an integrated circuit having one million transistors.
Further, when the dependence of the circuit constant on the pattern shape is considered in detail, the correction must be performed in accordance with various pattern shapes, so that the time required for the correction becomes longer. In addition, since the development and manufacturing period of the photomask, and hence the integrated circuit, is prolonged for the above-described reason, the dimension correction is actually performed only on a limited specific pattern shape. For this reason, for a pattern other than a specific pattern shape, the circuit constant at the time of design and the finished circuit constant are different, and it is not possible to accurately calculate a characteristic variation such as a delay. Further, in order to avoid the influence of the delay or the like, an excessive design margin was eventually required.

An object of the present invention is to provide a circuit parameter extracting apparatus and a delay calculating method capable of extracting a circuit parameter reflecting a finished pattern dimension and calculating a delay.

[0008]

In order to achieve the above object, the present invention provides a circuit parameter extracting device and a delay calculating method based on design values of circuit parameters extracted from layout data representing pattern dimensions. In this configuration, a predicted finish value is calculated and used as a new circuit parameter, and a delay value is calculated using the circuit parameter.

Specifically, the invention of claim 1 is at least one of extraction means for extracting and correcting a diffusion layer parameter, a gate electrode wiring parameter, and a metal wiring parameter which are circuit parameters. A circuit parameter extracting device including an extracting unit, a determining unit for determining whether a design value of the circuit parameter satisfies a predetermined standard, and a new circuit that corrects a design value that does not satisfy the standard. The configuration includes a determination unit for determining as a parameter, and a unit for creating and outputting circuit connection information using a new circuit parameter.

According to the configuration of the first aspect, since the corrected circuit parameters are used, the finished pattern size can be accurately reflected on the circuit connection information.

A second aspect of the present invention is a circuit parameter extracting device comprising an extracting unit for extracting and correcting a gate electrode wiring parameter among circuit parameters in a standard cell constituting an integrated circuit. First determining means for determining whether a design value of a distance between gate wiring electrodes of a standard cell satisfies a predetermined standard,
Second determining means for determining whether a design value of a distance between a gate wiring electrode at an end of a standard cell and a gate wiring electrode at an end of an adjacent standard cell satisfies a predetermined standard; Determining means for determining, as a new circuit parameter, a value obtained by correcting a gate wiring electrode width or a distance between gate wiring electrodes corresponding to a design value which does not satisfy a standard as a result of the determination by the first and second determining means; Means for creating and outputting circuit connection information using new circuit parameters.

According to the configuration of the second aspect, since the circuit parameters corrected in the standard cell are used, the finished pattern size can be accurately reflected on the circuit connection information of the standard cell.

A fourth aspect of the present invention is a delay calculating method for calculating a signal delay of a circuit using a standard cell forming an integrated circuit by using a gate electrode wiring parameter which is a circuit parameter. Is the design value of the distance between the gate wiring electrodes on the first and second ends of the standard cell and the second and first end gate wiring electrodes on the standard cell adjacent to each side. Deciding whether or not satisfies a predetermined standard, and a value obtained by correcting the gate wiring electrode width or the distance between gate wiring electrodes corresponding to a design value that does not satisfy the standard is determined as a new circuit parameter. A step of generating and outputting circuit connection information using new circuit parameters; a step of extracting a desired delay parameter from the circuit connection information; It is an arrangement that includes a step of calculating the delay of that signal.

According to the fourth aspect of the present invention, in the delay calculation in the circuit using the standard cell, the delay parameter is extracted from the circuit connection information generated using the corrected circuit parameter, so that the finished pattern size is accurately reflected. The delay can be calculated using the calculated delay parameter.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. The first embodiment relates to a circuit parameter extracting device for correcting the influence of a proximity effect, an isolated pattern, and etching non-uniformity.

FIG. 1 shows a processing flow of the circuit parameter extracting device. Data 101 is layout data of a circuit from which circuit connection information is to be extracted. Processing flow 10
According to (12), the circuit parameters are extracted and corrected as necessary from the circuit parameters representing the layout data.

The processing flow 10 includes a narrow channel MOSFE
This is a means for correcting the channel width of T. Step 102 is an extracting means for extracting a diffusion layer parameter including a diffusion layer distance, which is a distance between another diffusion layer region of the diffusion layer forming the MOSFET, and a diffusion layer width. Step 103A is a determination unit for determining whether the extracted diffusion layer parameter satisfies the standard. If the parameter satisfies the standard, the process proceeds to step 104A. Step 104A is determining means for determining the extracted value as it is as the diffusion layer parameter. On the other hand, if the standard is not satisfied, the process proceeds to step 105A. Step 105A is a correction means for calculating and correcting the finish value corresponding to the extracted value of the diffusion interlayer distance or diffusion layer width that did not satisfy the standard. The correction is performed, and the process proceeds to Step 104A. Step 104A, which is a determining means, determines the finish value as a new diffusion layer parameter.

The processing flow 11 is a means for correcting the distance between the gate electrode wirings, which is the distance between adjacent gate electrode wirings, or the width of the gate electrode wiring. Step 1
Reference numeral 11 denotes an extraction unit for extracting a gate electrode wiring parameter including a gate electrode wiring width and a distance between gate electrode wirings. Step 112A is a determination means for determining whether or not the extracted gate electrode wiring parameter satisfies the standard. If the standard is satisfied, the process proceeds to step 113A. Step 113A is a determining means for determining the extracted value as it is as the gate electrode wiring parameter. On the other hand, if the standard is not satisfied, the process proceeds to step 114A. Step 114A is a correction means for calculating and correcting a finish value corresponding to the extracted value of the gate electrode wiring width or the distance between the gate electrode wirings which does not satisfy the standard. Step 1 which is the determining means
13A determines the finish value as a new gate electrode wiring parameter.

The processing flow 12 is a means for correcting a distance between metal wirings, which is a distance between adjacent metal wirings, or a metal wiring width. Step 121 is an extracting means for extracting a metal wiring parameter including a metal wiring width and a distance between metal wirings. Step 12
2A is determination means for determining whether or not the extracted metal wiring parameter satisfies the standard. If the metal wiring parameter satisfies the standard, the process proceeds to step 123A. Step 123A is a determining means for determining the extracted value as it is as the metal wiring parameter. On the other hand, if the standard is not satisfied, step 1
Proceed to 24A. Step 124A is a correction means for calculating and correcting the finish value corresponding to the extracted value of the metal wiring width or the distance between the metal wirings that does not satisfy the standard, and corrects and proceeds to step 123A. Step 123A, which is a determining means, determines the finish value as a new metal wiring parameter.

Step 131 is a generating means for generating and outputting circuit connection information, and uses the determined diffusion layer parameters, gate electrode wiring parameters, and metal wiring parameters to determine the gate length of the MOSFET, the gate electrode wiring, Calculate the resistance and capacitance of the metal wiring and calculate the SPI
It generates and outputs circuit connection information such as a CE netlist. The data 132 is a library for storing the generated circuit connection information and outputting it as needed.

FIGS. 2A and 2B are part of a pattern diagram and a flowchart showing a specific example of correction for the diffusion layer width. In FIG. 2A, the pattern is deformed (rounded) due to uneven etching in the concave portion of the diffusion layer 3 corresponding to the remaining portion of the resist. As a result, the pattern width of the diffusion layer 3 becomes the design value W _D2 (= c). ) Is the finished value W _P2 (> W _D2 ). In FIG. 2B, step 103B is a determination unit for determining whether the design value W _D2 (= c) is greater than a specified value d (μm). The processing flow is as follows: W _D2 > d. If so, proceed to step 104B,
If W _D2 ≦ d, the process proceeds to step 105B. Step 1
In the case of 05B, the finish value is determined to be large due to the influence of the non-uniformity of the etching, and the predetermined coefficient δ ₁ (0 <δ ₁ )
Is a calculating means for calculating the finished value W _P2 = c + δ ₁ c (μm) using Step 104B determines that W _D2 > d
, The diffusion layer width W = _WD2 (= c) and the design value W
The _D2, W _D2 ≦ if d diffusion layer width _{W = W P2 (= c +} δ 1
This is a determining means for determining the finished value W _P2 as an effective diffusion layer parameter as c).

FIGS. 3A and 3B are a part of a pattern diagram and a flowchart showing another specific example of correction for the diffusion layer width. In FIG. 3A, the width of the diffusion layer 3 is a design value X _D (= e), and the distance between adjacent diffusion layers is a design value D _D1 . Rectangular portion corresponding to the design value X _D becomes the remaining portion of the resist. In FIG. 3B,
Step 103C is a judgment means for design value D _D1 to determine the specified value f ([mu] m) or less, the process flow proceeds to step 104C, if D _D1 <f,
If D _D1 ≧ f, the process proceeds to step 105C. Step 1
05C is due to the effect of the isolated pattern is remaining portion of the resist is reduced is determined that the finish value of the diffusion layer pattern becomes smaller, the coefficient predetermined [delta] ₂ finish with a (0 <δ ₂ <1) value X _P = It is a calculating means for calculating e-δ ₂ e (μm). In Step 104C, if D _D1 <f, the design value X _D is set as the diffusion layer width X = X _D (= e), and D ₁
The ≧ If f diffusion layer width _{X = X P (= e-} δ 2 e) as a finished value X _P, a determining means for determining the effective diffusion layer parameters. In the above description, FIG.
Although the horizontal direction is shown in (a) and (b), it is of course possible to correct the vertical width of the diffusion layer in consideration of the vertical diffusion layer distance. Also, in step 103C, if the design value D _D1 is smaller than another specified value of the diffusion layer distance, the determination means for determining that the proximity effect is exerted. In step 105C, the proximity to the diffusion layer width is determined. It is also possible to provide a configuration including a calculation unit for calculating a finished value of a small diffusion layer width in consideration of the effect of the effect. With this configuration, the influence of the proximity effect on the diffusion layer width can be corrected.

FIGS. 4A and 4B are a part of a pattern diagram and a flowchart showing a specific example of correction for the gate electrode wiring width. In FIG. 4A, MOSFE
The width of the gate electrode wiring 1 of T is the design value L _D3 (= g), and the distance between adjacent gate electrode wirings is the design value D _D3.
It is. In FIG. 4 (b), step 112B is a judgment means for judging whether or not the designed value D _D3 is greater than the prescribed value h ([mu] m), the processing flow, step 113B if D _D3> h The process proceeds to step 114B if D _D3 ≦ h. In step 114B, it is determined that the finish value becomes small due to the influence of the proximity effect, and the finish value L _P3 = g−δ using a predetermined coefficient δ ₃ (0 <δ ₃ <1).
It is a calculation means for calculating ₃ g (μm). In step 113B, if D _D3 > h, the gate length L ₃ = L
_The design value L _D3 is set as D ₃ (= g), and the finished value L is set as the gate length L ₃ = L _P3 (= g−δ ₃ g) if D _D3 ≦ h.
_P3 is a determining means for determining an effective gate electrode wiring parameter. In the above description, the case where the design value L _D3 of the gate electrode wiring width is corrected has been described, but the design value D _{D3 of the} distance between the gate electrode wirings may be corrected.

FIGS. 5A and 5B are a pattern diagram and a part of a flowchart showing a specific example of correction for the metal wiring width. In FIG. 5A, the width of the metal wiring 2 of the MOSFET is a design value L _D4 (= i), and the distance between adjacent metal wirings is the design value D _D4 . FIG.
(B), the step 122B is a judgment means for judging whether or not the designed value D _D4 is greater than the prescribed value j ([mu] m), the processing flow proceeds to step 123B if D _D4> j , D _D4 ≦ j, the process proceeds to step 124B. Step 124B determines that the finish value is reduced by the influence of the proximity effect, and determines a predetermined coefficient δ ₄ (0 <
Using δ ₄ <1), the finished value L _P4 = i−δ ₄ i (μm)
Is a calculating means for calculating. Step 123B
Is, if D _D4 > j, the metal wiring width L ₄ = L _D4 (= i)
As the design values L _D4, if D _D4 ≦ j metal wire width L
₄ = L _P4 (= i−δ ₄ i) and is a determining means for determining the finished value L _P4 as an effective metal wiring parameter. In the above description, the design value L of the metal wiring width
_Although the case where _D4 is corrected has been described, the design value _{DD4 of the} distance between metal wires may be corrected.

In addition to the above-described configuration, for example, step 112 in FIG. 4B or FIG.
B or 122B, a determination unit for determining that the pattern is an isolated pattern if the design value is equal to or greater than another specified value of the inter-wiring distance, and FIG. 4B or 5B.
In step 114B or 124B in the above, a configuration may be provided that includes a calculation unit for calculating a finish value of a small wiring width in consideration of the influence of the isolated pattern on the wiring. With this configuration, the influence of the isolated pattern on the wiring width can be corrected.

In the first embodiment, the processing is performed in the order of the processing flow 10 for correcting the diffusion layer, the processing flow 11 for correcting the gate electrode wiring, and the processing flow 12 for correcting the metal wiring in FIG. It has become.
The configuration may be such that processing is performed in a sequence other than this order, or one or two flows may be processed according to the content to be corrected.

According to the first embodiment, by extracting and correcting circuit parameters, circuit connection information can be generated using circuit parameters that accurately reflect the finished pattern dimensions. Therefore, circuit connection information that can reduce the difference between the designed circuit characteristics and the finished circuit characteristics can be obtained,
The required design margin can be reduced.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. Second
The present invention relates to an apparatus and a delay calculation method for extracting a delay parameter by reflecting the influence of a proximity effect and an isolated pattern on a gate electrode wiring width in a standard cell used for designing a building block integrated circuit. It is.

FIGS. 6 (a) and 6 (b) show examples of layout data of a cell arrangement to be used when extracting delay parameters. In FIG. 6A, the layout data of the first standard cell 201 to be extracted includes the layout data of the second standard cell 202 and the third standard cell 203 assumed at the time of the layout design on the left and right sides. Have. The direction of the mark “F” located at the upper corner of each standard cell is arrangement information indicating the direction of cell arrangement. In the first standard cell 201, pMOSFET2
11 and nMOSFET 212 are at the left end, pMOSFE
T213 and nMOSFET 214 are located at the right end, respectively.

In the first standard cell 201, the pMOS
FETs 211 and 213 and nMOSFETs 212 and 21
In the case of a gate electrode wiring of a MOSFET other than 4
Can be corrected to the gate electrode wiring width in consideration of the proximity effect and the influence of the isolated pattern based on the wiring width and the distance between the wirings in the standard cell 201. on the other hand,
Leftmost MOSFETs 211 and 212 and rightmost MOSF
In the case of the gate electrode wirings of the ETs 213 and 214, the gate electrode wirings of the adjacent second and third standard cells 202 and 203 are affected. Since various cells can be considered as adjacent standard cells, the leftmost and rightmost MOSFETs in the standard cell from which delay parameters are to be extracted.
Distance between the gate electrode wiring and the outer periphery of the standard cell,
The distance is calculated for each type of standard cell and classified into several representative distances. In FIG. 6A, the distance calculated for the first standard cell 201 having the first outer circumference is D _lp0 : the gate electrode wiring of the pMOSFET 211 and the first distance.
D _ln0 : the gate electrode wiring of the nMOSFET 212 and the first
D _rp0 : the gate electrode wiring of the pMOSFET 213 and the first
D _rn0 : the gate electrode wiring of the nMOSFET 214 and the first
The distance from the outer circumference of the four.

The representative value of the distance between the gate electrode wiring of the MOSFETs of the second and third standard cells 202 and 203 adjacent to the right and left and the first outer periphery is D _lpi : the third standard. representative value D _lni the distance between the gate electrode wiring and a first outer periphery of the left end pMOSFET cell 203: the representative value of the distance between the third gate electrode wiring and a first outer periphery of the left nMOSFET of the standard cell 203 D _rpi: Representative value of the distance between the gate electrode wiring of the rightmost pMOSFET of the second standard cell 202 and the first outer periphery _Drni : Representative value of the distance between the gate electrode wiring of the rightmost nMOSFET of the second standard cell 202 and the first outer periphery It is represented by the value Note that i is a code for classifying the representative value of the distance.

In the example shown in FIG. 6A, the distance between the wirings is calculated in order to correct the gate electrode wiring of each MOSFET at both ends of the first standard cell 201, and D _lp = D _lp0 + D _rpi (1): pMOSFET211 correction _{D ln = D ln0 + D rni} (2): correction _{D rp = D rp0 + D lpi} (3) of NMOSFET212: correction _{D rn = D rn0 + D lni} (4) of pMOSFET213: nMOSFET214 correction of Get results. Equations (1) to (4), which are the distances between the gate electrode wirings at both ends of the first standard cell 201 and the gate electrode wirings in the second and third standard cells 202 and 203.
Based on the result, the width of the gate electrode wiring at both ends of the first standard cell 201 is corrected.

The standard cells can also be arranged mirror-inverted. For example, FIG.
Second and third standard cells 202 and 203 shown in FIG.
Are mirror-symmetrically inverted, and the layout data of the gate electrode wiring when the fourth standard cell 204 and the fifth standard cell 205 are arranged on the right and left sides of the first standard cell 201 are shown. In this case, the distance between the wirings is calculated to correct the gate electrode wirings of the MOSFETs at both ends of the first standard cell 201. D ′ _lp = D _lp0 + D _lpi (5): Correction of pMOSFET 211 D ' _Ln = _Dln0 + _Dlni (6): Correction of nMOSFET 212 D' _rp = _Drp0 + _Drpi (7): Correction of pMOSFET 213 D' _rn = _Drn0 + _Drni (8): The result of correction of nMOSFET 214 is obtained. Equations (5) to (8), which are the distances between the gate electrode wirings at both ends of the first standard cell 201 and the gate electrode wirings in the fourth and fifth standard cells 204 and 205.
Based on the result, the width of the gate electrode wiring at both ends of the first standard cell 201 is corrected.

FIG. 7 shows a flow of extracting the circuit connection information of the first standard cell 201 based on the arrangement of the standard cells shown in FIGS. 6 (a) and 6 (b). The same reference numerals are given to the same processing steps as those in FIG. 1, and description thereof will be omitted. Data 301 and 302 are distance information. The data 301 includes the leftmost MOSFETs 211 and 212 and the rightmost MOSF in the first standard cell 201 from which circuit information is to be extracted.
The distances D _lp0 , D _ln0 , D _rp0, and D _rn0 between the gate electrode wirings of the _{ETs 213} and ₂₁₄ and the first outer circumference.
The data 302 is the M at the right end of the second standard cell 202.
Gate electrode wiring of OSFET and third standard cell 20
3 and the gate electrode wiring of the leftmost MOSFET.
_Are representative values D _rpi , D _rni , D _lpi, and D _lni of the distances from the outer circumference. Step 303 is a process in which data 301 and 3
02, the distance between the gate electrode wires at both ends of the first standard cell 201 and the gate electrode wires in the adjacent standard cells is calculated according to the formulas (1) to (4). It is a calculation means for performing. Step 304
Are the gate electrode wirings at both ends of the first standard cell 201 in accordance with the equations (5) to (8) based on the data 301 and 302 when the mirror-inverted cells are arranged adjacently on the left and right. And a calculating means for calculating the distance between the gate electrode wirings between the mirror electrode and the gate electrode wirings in the adjacent standard cell which is mirror-inverted. Steps 303 and 3
04, the MO of standard cells adjacent to the left and right
For each representative value of the distance between the SFET and the first outer periphery, that is, for each index indicated by i in equations (1) to (8), it is determined in step 112A whether the distance between the gate electrode wirings satisfies the standard. judge. According to the determination, if necessary, the gate electrode wiring width or the distance between the gate electrode wirings of the MOSFET is corrected to an effective value in step 114A, and the gate electrode wiring parameter which is a circuit parameter is determined in step 113A. Data 305 is
This is a library that stores the circuit connection information generated in step 131 and outputs it as needed. Step 306
It is an extracting means for extracting a delay parameter for describing a delay of a desired signal from the circuit connection information in the data 305 as necessary. The data 307 is a library that stores extracted delay parameters as a plurality of delay parameter sets corresponding to adjacent cells and outputs the extracted delay parameters as needed. Therefore, the processing flow 308 including the step 306 and the data 307 can determine a plurality of delay parameter sets corresponding to adjacent cells from the circuit connection information. In another step (not shown), the delay parameter set is used to calculate the signal delay in the standard cell.

In the second embodiment, at step 112A in FIG. 7, a determination means for determining based on an appropriate standard corresponding to each of the influence of the proximity effect and the influence of the isolated pattern is provided. , Both effects can be corrected.

According to the second embodiment, by extracting and correcting the circuit parameters of the standard cells, circuit connection information can be generated using circuit parameters that accurately reflect the finished pattern dimensions. Therefore, from the circuit connection information that can reduce the difference between the designed circuit characteristics and the finished circuit characteristics, a delay parameter that represents the delay in the standard cell with high accuracy can be obtained. Signal delay can be calculated with high accuracy.

(Third Embodiment) Hereinafter, a third embodiment of the present invention will be described with reference to the drawings. Third
The second embodiment relates to another delay calculation method in a circuit block using standard cells in a building block system, in which the influence of a proximity effect and an isolated pattern is considered.

FIG. 8A shows another example of the layout data of the cell arrangement, which is targeted when extracting the delay parameter. FIG. 8B shows a delay parameter selection flow corresponding to the processing flow 308 in FIG. 7 for selecting a delay parameter according to the arrangement information of the standard cells. 8, the elements having the same contents as those in FIGS. 1, 6, and 7 are denoted by the same reference numerals, and description thereof will be omitted.

The standard cell 401 to be subjected to the delay calculation has standard cells 402 and 403 adjacent to the left and right sides. The layout data 101 has the arrangement information of each standard cell indicated by the direction of the mark “F” located at the upper corner of each standard cell. Data 301 is distance information of each standard cell, the distance between the gate electrode wiring of the MOSFET at both ends of each standard cell and the outer periphery of the standard cell,
D _lp0 , D _ln0 , D _rp0 and D _rn0 . Step 4
Reference numeral 11 denotes a standard cell 4 based on the layout information of the layout data 101 and the distance information between the standard cell 401 to be subjected to the delay calculation and the adjacent cells 402 and 403 of the data 301.
The distance between the gate electrode wiring of No. 01 and the gate electrode wirings of the adjacent cells 402 and 403 is calculated. Step 41
Reference numeral 2 denotes a delay parameter selected from the data 307, which is a delay parameter library, according to the calculation result of step 411, which is a circuit parameter and is a distance between gate electrode wirings. In another step (not shown), the delay in the circuit block is calculated using the selected delay parameter data 413.

According to the third embodiment, in the delay calculation of the circuit block using the standard cell, the delay parameter is selected from the circuit connection information generated using the circuit parameter accurately reflecting the finished pattern size. it can. Therefore, the delay of the signal in the circuit block can be calculated with high accuracy by using the delay parameter in consideration of the circuit characteristics after finishing.

In each of the embodiments described above, the MO
Although an example of the SFET has been described, the present invention can be applied to other types of devices having at least a gate electrode, for example, a junction FET, a GaAs FET, a HEMT, and the like, instead of the MOSFET.

[0042]

According to the circuit parameter extracting device of the present invention, circuit connection information and standard cell connection information can be generated using circuit parameters that accurately reflect the finished pattern dimensions. Therefore, it is possible to obtain circuit connection information and standard cell connection information in which the error between the circuit characteristics at the time of design and the measured circuit characteristics is small, thereby reducing variations in finished circuit characteristics with respect to design values and reducing design margins. Becomes possible. Further, according to the delay calculation method according to the present invention, it is possible to obtain a delay parameter of a standard cell having a high delay time accuracy by using a circuit parameter that accurately reflects a finished pattern dimension. The delay of the signal in the used circuit block can be calculated with high accuracy.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a processing flow of a circuit parameter extraction device according to the present invention.

FIG. 2A is a pattern diagram showing a specific example of correction for a diffusion layer width, and FIG. 2B is a part of a flowchart of the correction.

FIG. 3A is a pattern diagram showing another specific example of correction for a diffusion layer width, and FIG. 3B is a part of a flowchart of the correction.

FIG. 4A is a pattern diagram showing a specific example of correction for a gate electrode wiring width, and FIG. 4B is a part of a flowchart of the correction.

FIG. 5A is a pattern diagram showing a specific example of correction for a metal wiring width, and FIG. 5B is a part of a flowchart of the correction.

FIGS. 6A and 6B are layout layout diagrams including standard cells from which delay parameters are extracted.

FIG. 7 is a flowchart showing a processing flow of another circuit parameter extracting device according to the present invention.

8A is another layout diagram including a standard cell from which a delay parameter is extracted, and FIG. 8B is a flowchart illustrating a processing flow for determining a delay parameter.

FIGS. 9A and 9B are explanatory diagrams of an influence of a proximity effect on a gate electrode wiring.

FIGS. 10A and 10B are diagrams illustrating the influence of an isolated pattern on a gate electrode wiring.

FIGS. 11A and 11B are diagrams illustrating the influence of uneven etching on a diffusion layer pattern.

[Explanation of symbols]

1 Gate electrode wiring 2 Metal wiring 3 Diffusion layer D _D1 Design value of distance between diffusion layers D _D3 Design value of distance between gate electrode wiring D _D4 Design value of distance between metal wiring L _D3 Design value of gate electrode wiring width L _P3 Gate electrode Finished value of wiring width L _D4 Designed value of metal wiring width L _P4 Finished value of metal wiring width W _D2 Designed value of diffusion layer width W _P2 Finished value of diffusion layer width X _D Designed value of diffusion layer width X _P Diffusion layer width Finished value of

Claims (5)

[Claims] 1. A first method for extracting and correcting a diffusion layer parameter, a gate electrode wiring parameter, and a metal wiring parameter from layout data including circuit parameters representing a pattern position, a pattern width, and a distance between patterns in an integrated circuit. , A circuit parameter extracting apparatus comprising at least one of a second and a third extracting means, wherein the first extracting means extracts a design value of a diffusion layer width and a diffusion layer distance. Means for determining whether or not the design values of the diffusion layer width and the diffusion layer distance each satisfy a predetermined standard; and a diffusion layer corresponding to a design value that does not satisfy the standard. A first value for determining a value obtained by correcting the width or the distance between the diffusion layers as the diffusion layer parameter;
Determining means for extracting a design value of a gate electrode wiring width and a distance between gate electrode wirings, and a design value of the distance between the gate electrode wirings is predetermined. Second determining means for determining whether or not the standard is satisfied, and determining a value obtained by correcting a gate electrode wiring width or a distance between gate electrode wirings corresponding to a design value not satisfying the standard as the gate electrode wiring parameter. And a third determining means for extracting a design value of a metal wiring width and a distance between metal wirings, and a design value of the metal wiring distance. A third determining means for determining whether or not a predetermined standard is satisfied; and a value obtained by correcting a metal wiring width or a distance between metal wirings corresponding to a design value not satisfying the standard is determined as the metal wiring parameter. Using the determined diffusion layer parameters, gate electrode wiring parameters, and metal wiring parameters to determine circuit connection information, which is connection information of elements and wiring constituting the integrated circuit. A circuit parameter extracting device further comprising means for creating and outputting. 2. A circuit parameter comprising extraction means for extracting and correcting gate electrode wiring parameters from layout data comprising circuit parameters representing a pattern position, a pattern width and a distance between patterns in a standard cell forming an integrated circuit. An extracting device, wherein the extracting means is configured to extract a design value of a gate electrode wiring width and a distance between gate electrode wirings of the standard cell, and that the design value of the gate electrode wiring distance is a predetermined standard. First determining means for determining whether or not the above condition is satisfied; and determining a value obtained by correcting a gate electrode wiring width or a distance between gate electrode wirings corresponding to a design value not satisfying the standard as the gate electrode wiring parameter. First determining means for determining a first gate electrode wiring at a first side end in the standard cell and a first gate electrode wiring at a first side in the standard cell. A first design value that is a design value of a distance between the first gate electrode wire and the gate electrode wire facing the first adjacent cell in a contacting first adjacent cell; Design of a distance between a second gate electrode wiring at an end on a certain second side and a gate electrode wiring facing the second gate electrode wiring in a second adjacent cell adjacent to the second side Second determining means for determining whether the second design value, which is a value, satisfies a predetermined standard, and a gate corresponding to the first or second design value not satisfying the standard Second determining means for determining, as the gate electrode wiring parameter, a value corrected for the electrode wiring width or the distance between the gate electrode wirings, wherein the standard cell is configured using the determined gate electrode wiring parameter. Connection information of elements and wiring Circuit parameter extracting device characterized by further comprising means for creating and outputting a circuit connection information is. 3. The circuit parameter extracting device according to claim 1, wherein the corrected value in each of the determining means is a predicted finish value corresponding to each design value. apparatus. 4. A gate electrode wiring parameter extracted from a layout data consisting of circuit parameters representing a pattern position, a pattern width, and a distance between patterns in a circuit using a standard cell constituting an integrated circuit. A first distance information indicating a design value of a distance between a gate electrode wiring at an end on a first side and an outer periphery of a standard cell, and an opposite side of the first side. Supplying second distance information indicating a design value of the distance between the gate electrode wiring at the end on the second side and the outer periphery, and a first adjacency adjacent to the first side of the standard cell. In the cell, the second
Supplying first adjacent distance information indicating a design value of the distance between the gate electrode wiring at the end on the side of the side and the outer periphery; and adding the first distance information and the first adjacent distance information to form a gate. Calculating a first design value of the distance between the electrode wirings; and, in a second adjacent cell adjacent to the second side of the standard cell, a first design value based on layout information indicating a layout layout direction.
Supplying second adjacent distance information indicating a design value of the distance between the gate electrode wiring at the end on the side of the side and the outer periphery; adding the second distance information and the second adjacent distance information to form a gate Calculating a second design value of the distance between the electrode wirings; determining whether the first and second design values each satisfy a predetermined standard; Determining a value obtained by correcting a gate electrode wiring width or a distance between gate electrode wirings corresponding to a second design value as the gate electrode wiring parameter; and configuring the standard cell using the determined gate electrode wiring parameter. Creating circuit connection information, which is connection information of elements and wirings to be performed; extracting a delay parameter necessary for calculating a desired delay from the circuit connection information; Delay calculation method characterized by comprising the step of calculating the delay of the signal in. 5. The delay calculation method according to claim 4, wherein
A delay calculation method, wherein a value after correction in each determination step is a predicted finish value corresponding to each design value.