JP2012014489A - Method, device and program for verifying layout of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for allowing verification of design based on the optimal design standard in quantitative consideration of a feature fluctuation amount of a transistor in order to prevent an influence of Diffusion rounding.SOLUTION: In a diffusion layer 1, the shape of the Diffusion rounding 5 to be formed at a corner part to be fixed by a first side 3 and a second side 4 is expressed by a mathematical expression, regarding the transistor Tr with gate width W adjacent to the corner part, an interval between the second side and a gate is considered as X1, an error of the gate width by the Diffusion rounding is considered as ΔW, a design reference value of the interval X1 between the second side and a gate is derived from relation between a shape parameter of the Diffusion rounding, ΔW and X1, and relation between feature variation and variation of the gate width of the transistor Tr, an interval between the gate of the transistor to be arranged adjacent to the corner part and the second side is extracted from layout information, and whether or not the extracted interval between the gate and the second side satisfies the reference value is determined.

Description

  The present invention relates to a design verification technique for a semiconductor device, and more particularly to a layout verification method and apparatus.

  As semiconductor manufacturing becomes finer, the effects of lithography and etching cannot be ignored. In some cases, L (gate length) and W (gate width), which determine transistor characteristics under the influence of lithography and etching, cannot be in accordance with the layout dimensions. Corners are rounded due to the influence of lithography and etching.

  For example, as described in Patent Document 1 and the like, as the pattern becomes finer, it is difficult to faithfully form the pattern in each process, and the final finished size does not match the design pattern. Has occurred. In order to solve these problems, it is important to perform mask data processing that creates a mask pattern different from the design pattern so that the final finished dimension becomes equal to the design pattern dimension in consideration of the conversion difference in each process. . In Patent Document 1, in response to the problem that the misalignment margin of a silicon completed structure (for example, polysilicon and contact) composed of different layers cannot be set appropriately, a lithography simulation is executed for each different layer. Then, different plane figures are calculated and overlaid, and a margin check is performed using DRC (Design Rule Checker). Note that Patent Document 1 does not deal with diffusion rounding (hereinafter referred to as diffusion rounding) handled in the present invention.

JP 2005-181523 A

  The analysis of related technology is given below.

  As pattern miniaturization progresses, L (gate length) and W (gate width) cannot follow the layout dimensions, and there is a feature that the corners are rounded due to the influence of lithography and etching, and an error between circuit simulation and silicon characteristics become. In order to prevent the influence of the diffusion rounding, it is necessary to quantitatively consider the characteristic variation amount of the transistor and to set the optimum design standard and to perform layout verification.

  Accordingly, an object of the present invention is to make it possible to set an optimum design standard that quantitatively considers the characteristic variation of a transistor in order to prevent the influence of Diffusion rounding, and to enable verification of the design based on the design standard. It is to provide a device and a program.

According to one aspect of the present invention, the first side in a planar diffusion layer having a second side that intersects with a first side on one side of an area having a predetermined width W at an end. And expressing the shape of the rounding formed at the corner defined by the second side by a mathematical expression,
For a transistor having a gate width W disposed adjacent to the corner portion, an interval between the second side and the gate is X1, a gate width variation amount caused by the rounding is ΔW,
From the geometrical parameters of the rounding and the plane geometric relationship between ΔW and X1, and the relationship between the characteristic variation rate of the transistor and the variation rate ΔW / W of the gate width,
Using a calculation formula defined by the rounding shape parameter, the characteristic variation rate of the transistor, and the gate width W, a reference value of the distance X1 between the second side and the gate is derived.
Extracting the distance between the gate of the transistor disposed adjacent to the corner portion and the second side from the layout graphic information of the semiconductor device;
There is provided a layout verification method for determining whether or not a distance between the extracted gate and the second side satisfies a reference value of X1 corresponding to a given transistor characteristic variation rate.

にて、導出する。 In the present invention, the rounding shape is approximated by an arc, and the rounding shape parameter is the radius r of the arc,
The design reference value X1 is calculated from the radius r of the arc, the characteristic variation rate ΔP / P of the transistor, and the gate width W as follows:

To derive.

  According to the present invention, an apparatus, a computer program, and a computer-readable recording medium for executing the above method are provided.

  According to the present invention, it is possible to set an optimum design standard that prevents the influence of diffusion rounding by quantitatively considering the amount of characteristic variation of the transistor, and it is possible to verify the design based on the design standard.

It is a layout diagram for explaining one embodiment of the present invention. It is a figure explaining Diffusing rounding. It is a figure explaining the rounding shape model in one Embodiment of this invention. It is a figure which shows the calculation result of the design reference value in one Embodiment of this invention. It is a flowchart which shows the layout verification procedure in one Embodiment of this invention. It is a figure which shows one Embodiment and a comparative example of this invention.

  One aspect of the present invention will be described. In one aspect of the present invention, ΔW of the Diffusing round shape is modeled, and an equation of W and transistor characteristic variation ΔIon / Ion is created using a model equation. When the characteristic variation rate ΔIon / Ion of the transistor, an X1 minimum design reference value is calculated for each W.

  FIG. 1 is a diagram for explaining the present invention, and schematically shows a design layout. As shown in FIG. 1, the diffusion layer 1 on the surface of the substrate has a second side 4 that intersects with a side (first side) 3 on one side of a region having a predetermined width W at a right angle at the end. The first side 3 and the second side 4 constitute a corner portion. As a gate electrode of the transistor Tr disposed adjacent to the corner portion, a length W (= gate width) is formed on the substrate surface through a gate oxide film (not shown) in a direction perpendicular to the first side 3. ), A polysilicon (Poly) 2 having a length L (= gate length) is provided in a direction parallel to the first side 3. A diffusion layer is not formed on the substrate surface immediately below the gate electrode (polysilicon gate) 2, and a channel is formed by a voltage applied to the gate electrode. The center line of the gate electrode (polysilicon gate) 2 is parallel to the second side 4 and is separated from the second side 4 by X1. The gate width of the transistor Tr is W, and one of the diffusion layers disposed on both sides of the polysilicon gate 2 is a drain diffusion layer and the other is a source diffusion layer. The length of the second side 4 intersecting the first side 3 at a right angle is Y1, and the width of the diffusion layer on the left side of the second side 4 is W + Y1. In FIG. 1, only one transistor Tr is shown for simplicity, but depending on the configuration of the realization circuit, one or more transistors (not shown) with a gate width of W + Y1 are diffused with a width W + Y1. Corresponding to the layer, it is arranged on the left side of FIG. 1 in parallel with the transistor Tr having a gate width of W. In some cases, one or more transistors (not shown) having a gate width W are further provided on the right side of the transistor Tr in FIG. 1 in parallel with the transistor Tr.

  2 shows a rounding (rounding of the diffusion layer 1, referred to as “Diffusion rounding”) 5 formed at the corners of the first side 3 and the second side 4 of the diffusion layer 1 in the layout of FIG. It is a figure which shows a planar shape typically. As shown in FIG. 2, since the rounding of the diffusion layer is formed, the gate width of the transistor is shifted by ΔW. In FIG. 2, ΔW is approximated by the distance from the first side 3 of the intersection of the center line of the gate electrode (polysilicon gate) 2 and the arc of the diffusion rounding 5.

  Modeling of the Diffusing round shape in the present embodiment will be described. In the present embodiment, the diffusion rounding shape is approximated by a circular arc and is mathematically expressed. It should be noted that the approximation of the diffusion rounding shape is not limited to the circular arc, and it is needless to say that any approximation or mathematical formula may be used as long as the diffusion rounding shape can be expressed by a mathematical expression.

  When the Diffusion rounding shape is approximated by an arc, the following equation (1) is established from the three-square theorem based on the three-square theorem, with a radius r and a triangle consisting of r-X1 and the other side as a. In FIG. 3, the center of the polysilicon gate 2 corresponds to the first side 3 in FIG. 2, the Y axis corresponds to the second side 4, and the center of the polysilicon gate 2 is located at a distance X1 from the Y axis (second side). The line is located.

（１）

(1)

よって、

（２） Where a is

Therefore,

(2)

（３） Substituting equation (2) into equation (1),

(3)

（４） Solving for ΔW yields equation (4).

(4)

（５） In equation (4), the solution, r + √, is a solution representing the upper part of the circle and is not necessary for the model equation. Therefore,

(5)

  When X1> r, the diffusion rounding 5 does not reach the gate electrode (polysilicon gate) 2 and therefore the gate width W does not vary and ΔW = 0.

（６） Also,

(6)

  That is, when the radius r of the Diffusing rounding is R or less (where Y1 <R), the length Y1 of the second side (corresponding to the height of the rounding in the Y-axis direction) is set to the radius r of the arc. To do. If r> R, r = R. However, R is a constant determined by process conditions and OPC (Optical Proximity Correction).

  Equation (5) is a model equation representing the Diffusing rounding shape. Using this model equation (5), an equation for the gate width W and the transistor characteristic variation is created. The characteristic fluctuation amount of the transistor Tr adjacent to the rounding is expressed by using the difference rounding ΔW obtained by the equation (4). At this time, the fact that the transistor characteristics (for example, drain current) and the gate width W are in a proportional relationship is used. For example, the drain current of the MOS transistor is proportional to W / L (that is, proportional to W), and the gate width variation rate ΔW / W = + 3% is equal to the drain current ΔIon / Ion = + 3%.

  Here, when the characteristic variation rate of the transistor to be limited is ΔIon / Ion, the following equation (7) is established.

（７）

(7)

（８） Substituting Equation (5) into ΔW in Equation (6),

(8)

（９） Solving the quadratic equation (7) for X1,

(9)

  Here, the solution r + √ is unnecessary because it is a solution when X1> r. Therefore, X1 is given by the following equation (10).

（１０）

(10)

  Expression (10) is obtained by calculating the reference value (design reference value) of X1 with respect to the size (gate width W) of the transistor (Tr) adjacent to the diffusion rounding 5 and the characteristic variation rate ΔIon / Ion of the transistor (Tr). It is a calculation formula for deriving. According to the present embodiment, when W and ΔIon / Ion are determined in this way, the reference value of X1 can be calculated from the radius r of the Diffusing rounding.

  In the present embodiment, the reference value of X1 is calculated for each value with different gate width W with respect to the characteristic variation rate ΔIon / Ion. That is, the reference value of X1 up to ΔIon / Ion = 0.1% to 10%, for example, is calculated using Expression (10). At this time, since the influence on the transistor characteristics is different for each value of the gate width W, the reference value of X1 is different.

  FIG. 4 is a graphical representation of the X1 reference value calculated according to the equation (10). In FIG. 4, the vertical axis represents the reference value [um] of X1, and the horizontal axis represents the gate width W [um] of the transistor Tr adjacent to the rounding. When the allowable characteristic fluctuation rate ΔIon / Ion is 0.1%, 0.2%, 0.4%, 1.0%, 2.0%, 4.0%, 10.0%, respectively On the other hand, the reference value of X1 is indicated by solid lines a to g. The solid lines a to g give the minimum reference value of X1 (the lower limit value of X1 allowed for the characteristic variation rate required in the design) at each gate width W of the characteristic variation rate ΔIon / Ion to be limited. In order to design the characteristic variation rate ΔIon / Ion to be limited to 0.2%, for example, for a given gate width W, the distance X1 between the second side 4 and the gate center is represented by a solid line (graph) b. It is necessary to design the layout as a value greater than or equal to the intersection with the corresponding gate width W. On the other hand, when X1 is smaller than the intersection with the corresponding gate width W of the solid line (graph) b, the characteristic variation rate ΔIon / Ion = 0.2% is not guaranteed.

  Next, a method of performing layout verification (DRC: Design Rule Check (inspecting whether the layout pattern does not violate the design rule of the process)) will be described.

  For the layout verification, an EDA (Electronic Design Automation) tool that operates on a data processing apparatus such as Calibr DRC manufactured by Mentor Graphics is used. FIG. 5 is a diagram showing a layout verification flow of the present embodiment. Each step in FIG. 5 is realized by a program executed on a computer (data processing apparatus) on which the EDA tool operates.

  Estimated characteristic variation rate (characteristic error) ΔIon / Ion of the transistor allowed in the circuit design is determined (step S101).

  By substituting the characteristic variation rate ΔIon / Ion and the radius r into the equation (9), the design standard between the center of the gate electrode of the transistor closest to the corner portion and the second side for each different gate width W A value X1 is determined (step S102). In step S102, for example, a reference value of X1 (graph b in FIG. 4) is obtained for each gate width when the characteristic variation rate is 0.2% (or another value).

  The layout design is performed (step S103), and the transistor Tr arranged closest to the corner where the diffusion rounding is formed and the dimension X1 are extracted from the layout graphic data using the EDA tool (step S104). X1 is a distance from the second side 4 of the gate disposed closest to the second side 4 in FIG. In step S104, the dimension Y1 corresponding to the length of the second side 4 in FIG. 1 may be extracted. Y1 is also a parameter representing the Diffusing rounding shape.

  It is determined whether X1 extracted in step S104 satisfies the reference value of X1 corresponding to the characteristic variation rate required in the design obtained in step S102 (step S105). If not, the process returns to the layout design S103. When X1 calculated in step S104 is smaller than the design reference value X1, the allowable estimated characteristic variation rate ΔIon / Ion of the transistor is not satisfied due to the influence of the diffusion rounding. Therefore, the layout is performed again.

  If the determination in step S105 is OK, the layout verification ends (step S106).

  When creating a design standard that takes into account characteristic variations other than Ion, the X1 design standard value is calculated in the following procedure.

  Examples of characteristic fluctuations caused by diffusion rounding other than Ion include fluctuations ΔVth in the threshold voltage Vth of the transistor and fluctuations ΔCg in the gate capacitance of the transistor. The determination of the X1 design reference value for the transistor threshold voltage variation ΔVth is as follows.

The characteristic of the threshold voltage Vth of the transistor has a strong correlation with the Ion characteristic (for example, Ion is proportional to (VGS−Vth) ² in the saturation region). The correlation coefficient between the threshold voltage Vth and Ion varies depending on the dimension of the gate length L. A correlation coefficient α between Ion and Vth is calculated in advance for each L dimension (ΔIon = α × Vth).

（１１） For example, when creating a reference value of X1 to suppress the characteristic fluctuation of ± 20 mV,

(11)

  By substituting ΔIon obtained by Expression (11) into Expression (10), the calculated X1 becomes the design reference value.

  Next, the determination of the X1 design reference value for the variation ΔCg of the gate capacitance of the transistor will be described. Since the variation ΔCg of the gate capacitance is determined by the variation amount of the gate area of the transistor, ΔW = ΔC. The equation (6) is modified as follows, and X1 calculated in the same procedure becomes the reference value.

（１２）

(12)

  Since the design standard X1 can be set for each W based on the characteristic variation of the transistor, it is possible to apply an optimum limit without excessive or insufficient. In addition, since the design standard X1 can be set based on the transistor characteristic variation allowable in the circuit design, it is possible to apply an optimum limit (FIG. 4).

  As described above, according to the present embodiment, since the X1 design reference value is calculated after converting the effect of Diffusion rounding into the characteristic fluctuation of the transistor, it is optimal for each of W and ΔIon / Ion. A design standard X1 can be set.

  Next, a comparative example not according to the present invention will be described. In the comparative example, the X1 design reference value is defined as a constant value regardless of W and ΔIon / Ion. In FIG. 6, as shown by the solid line h in the graph, X1 required when ΔIon / Ion is the minimum with the gate width W of the transistor as a design standard of a constant value (in FIG. 6, X1 reference value = 0.035 um). Yes. When the gate width W of the transistor is large and ΔIon / Ion is large, the design standard of X1 is an over margin setting. In the comparative example, since the X1 design reference value is set in the worst case, for example, when the gate width W of the transistor is large and the required value of the characteristic variation rate ΔIon / Ion is large, X1 reference value = 0.035 um The value is too strict.

  It should be noted that the disclosures of the above patent documents are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

1 Diffusion layer (Diffusion)
2 Polysilicon gate (gate electrode)
3 1st side (1st side of a corner part)
4 Second side (second side of the corner)
5 Diffusion rounding

Claims (20)

In a planar diffusion layer having a second side intersecting at one end with a first side on one side of a predetermined width W region, the first side and the second side are determined. Expressing the shape of the rounding formed at the corner with mathematical formulas,
For a transistor having a gate width W disposed adjacent to the corner portion, an interval between the second side and the gate is X1, a gate width variation amount caused by the rounding is ΔW,
From the shape parameter of the rounding, the plane geometric relationship between the ΔW and the X1, the relationship between the characteristic variation rate of the transistor and the variation rate ΔW / W of the gate width,
Using a calculation formula defined by the rounding shape parameter, the characteristic variation rate of the transistor, and the gate width W, a reference value of the distance X1 between the second side and the gate is derived.
Extracting the distance between the gate of the transistor disposed adjacent to the corner portion and the second side from the layout graphic information of the semiconductor device;
A semiconductor device layout verification method for determining whether or not a distance between the extracted gate and the second side satisfies a reference value of X1 corresponding to a given characteristic variation rate of a transistor. The rounding shape is approximated by a circular arc, the rounding shape parameter is the radius r of the circular arc, the characteristic variation rate of the transistor is ΔP / P,
The reference value of X1 is calculated from the radius r of the arc, the characteristic variation rate ΔP / P of the transistor, and the gate width W as follows:

The method of verifying a layout of a semiconductor device according to claim 1, wherein the method is derived.   The layout verification method for a semiconductor device according to claim 2, wherein the characteristic variation rate ΔP / P of the transistor is a variation rate ΔIon / Ion of a current flowing through the transistor Ion.   3. The semiconductor device layout verification method according to claim 2, wherein the transistor characteristic variation rate [Delta] P / P is a variation rate [Delta] Cg / Cg of the gate capacitance Cg of the transistor.   3. The semiconductor device layout verification method according to claim 2, wherein the transistor characteristic variation rate ΔP / P is a threshold voltage variation rate ΔVth / Vth of the transistor. The threshold voltage fluctuation amount ΔVth of the transistor is given by α × ΔIon by the correlation coefficient α between the threshold voltage Vth and the fluctuation amount Ion of the current flowing through the transistor,
6. The semiconductor device layout verification method according to claim 5, wherein [Delta] Vth / Vth is [alpha] * [Delta] Ion / Ion. ΔW is a distance from the first side of an intersection of the arc that approximates the rounding shape and a center line corresponding to a half position in the gate length direction of the gate of the transistor;
The layout verification method for a semiconductor device according to claim 2, wherein the radius r of the arc satisfies a relationship of (r−X1) ² + (r−ΔW) ² = r ² . When the radius r is equal to or smaller than a predetermined value, the radius is the length of the second side,
The layout verification method for a semiconductor device according to claim 7, wherein when the value is larger than the predetermined value, the predetermined value is set. In a planar diffusion layer having a second side intersecting at one end with a first side on one side of a predetermined width W region, the first side and the second side are determined. Expressing the shape of the rounding formed at the corner with mathematical formulas,
For a transistor having a gate width W disposed adjacent to the corner portion, an interval between the second side and the gate is X1, a gate width variation amount caused by the rounding is ΔW,
From the shape parameter of the rounding, the plane geometric relationship between the ΔW and the X1, the relationship between the characteristic variation rate of the transistor and the variation rate ΔW / W of the gate width,
Using a calculation formula defined by the rounding shape parameter, the characteristic variation rate of the transistor, and the gate width W, a reference value of the distance X1 between the second side and the gate is derived.
Extracting the distance between the gate of the transistor disposed adjacent to the corner portion and the second side from the layout graphic information of the semiconductor device;
A layout verification apparatus that determines whether or not a distance between the extracted gate and the second side satisfies a reference value of X1 corresponding to a given transistor characteristic variation rate. The rounding shape is approximated by a circular arc, the rounding shape parameter is the radius r of the circular arc, the characteristic variation rate of the transistor is ΔP / P,
The reference value of X1 is calculated from the radius r of the arc, the characteristic variation rate ΔP / P of the transistor, and the gate width W as follows:

10. The layout verification device according to claim 9, wherein the layout verification device is derived.   The layout verification apparatus according to claim 10, wherein the characteristic variation rate ΔP / P of the transistor is a variation rate ΔIon / Ion of a current flowing through the transistor.   The layout verification apparatus according to claim 10, wherein the transistor characteristic variation rate ΔP / P is a gate capacitance variation rate ΔCg / Cg of the transistor.   The layout verification apparatus according to claim 10, wherein the transistor characteristic variation rate ΔP / P is a threshold voltage variation rate ΔVth / Vth of the transistor. The threshold voltage fluctuation amount ΔVth of the transistor is given by α × ΔIon by the correlation coefficient α between the threshold voltage Vth and the fluctuation amount Ion of the current flowing through the transistor,
The layout verification apparatus according to claim 13, wherein ΔVth / Vth is α × ΔIon / Ion. ΔW is the distance from the first side of the intersection of the arc that approximates the rounding shape and the center line corresponding to half the gate length direction of the gate electrode;
The layout verification device according to claim 10, wherein the radius r of the arc satisfies a relationship of (r−X1) ² + (r−ΔW) ² = r ² . In a planar diffusion layer having a second side intersecting at one end with a first side on one side of a predetermined width W region, the first side and the second side are determined. Expressing the shape of the rounding formed at the corner with mathematical formulas,
For a transistor having a gate width W disposed adjacent to the corner portion, an interval between the second side and the gate is X1, a gate width variation amount caused by the rounding is ΔW,
From the shape parameter of the rounding, the plane geometric relationship between ΔW and X1, and the relationship between the characteristic variation rate of the transistor and the variation rate ΔW / W of the gate width,
Using a calculation formula defined by the rounding shape parameter, the characteristic variation rate of the transistor, and the gate width W, a reference value of the distance X1 between the second side and the gate is derived.
The reference of X1 extracted from the layout graphic information of the semiconductor device, and the distance between the gate of the transistor disposed adjacent to the corner portion and the second side corresponds to the given characteristic variation rate of the transistor Processing to determine whether the value is satisfied,
A program that causes a computer to execute. The rounding shape is approximated by a circular arc, the rounding shape parameter is the radius r of the circular arc, the characteristic variation rate of the transistor is ΔP / P,
The reference value of X1 is calculated from the radius r of the arc, the characteristic variation rate ΔP / P of the transistor, and the gate width W as follows:

The program according to claim 16, wherein the program is derived.   18. The program according to claim 17, wherein the characteristic variation rate ΔP / P of the transistor is a variation rate ΔIon / Ion of a current flowing through the transistor.   The program according to claim 17, wherein the transistor characteristic variation rate ΔP / P is a gate capacitance variation rate ΔCg / Cg of the transistor.   The program according to claim 17, wherein the transistor characteristic variation rate ΔP / P is a threshold voltage variation rate ΔVth / Vth of the transistor.

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