WO2009157058A1

WO2009157058A1 - Method for designing photomask, equipment for designing photomask, program, recording medium, and method for manufacturing semiconductor device

Info

Publication number: WO2009157058A1
Application number: PCT/JP2008/061463
Authority: WO
Inventors: 一弥須川; 雅彦峯村; 武敏小俣; 秀二片瀬; 典正永瀬
Original assignee: 富士通マイクロエレクトロニクス株式会社
Priority date: 2008-06-24
Filing date: 2008-06-24
Publication date: 2009-12-30

Abstract

Information on a plurality of functional blocks is recognized from design data on a mask pattern of a photomask to give first accuracy information on the OPC which is predefined on per-functional block basis for each of the functional blocks, while giving second accuracy information on the OPC which is predefined on per-layer basis for each of the layers. Subsequently, the OPC is executed for the functional blocks in accordance with the first and second accuracy information. With such a configuration, in correction processing operation by the OPC, the OPC processing operation is performed at a correction accuracy required for each functional block correspondingly to a wide variety of device patterns to reduce (optimize) the output data size, resulting in the time required for correction processing operation being significantly reduced.

Description

Photomask design method and apparatus, program, recording medium, and semiconductor device manufacturing method

The present invention relates to a photomask design method and program using optical proximity effect correction, and a semiconductor device manufacturing method.

In recent years, miniaturization and high integration of semiconductor devices have progressed, and therefore a highly accurate device pattern forming technique is required.
In order to form a highly accurate device pattern, in order to accurately transfer a fine resist pattern during exposure transfer of the mask pattern to the resist, in addition to optimizing the wavelength of the exposure light and the reticle structure, the pattern of the adjacent pattern Calculate and calculate the impact and make corrections. This correction is called optical proximity correction (OPC). The OPC correction process takes into account the exposure conditions (NA, Sigma), exposure conditions (resist material, exposure wavelength), etc., and calculates the correction amount by calculating the effect of the optical proximity effect or by experiment. This is a technique for correcting the pattern dimensions for the design data.

In conventional OPC correction processing, photomask data is created by correcting the relationship between its own pattern data and adjacent pattern data based on a condition file including specified intervals, pattern widths, and optical conditions. ing. Regarding the OPC correction processing, since interference of pattern data must be taken into consideration, if the pattern data outside the adjacent area is different even if there is a repeated pattern, the correction processing is performed on each pattern data. ing.

Here, for example, Patent Document 1 discloses a method of registering each basic cell that has been subjected to OPC correction processing in advance in the creation stage of mask pattern design data and performing layout design using the basic cell. Yes.
Japanese Patent Application Laid-Open No. 2004-228561 discloses a method of determining an allowable value of a model fitting residue from a test pattern in an OPC correction process based on a model, and providing an allowable value for fitting while maintaining OPC correction accuracy.
In Patent Document 3, a circuit pattern is converted into a DB (library), and when it is determined that the pattern is the same as a pattern registered in the DB, a correction value is obtained from the DB, thereby correcting the OPC based on the model. A technique for minimizing time simulation is disclosed.

JP 2007-199234 A JP 2004-163472 A JP 2004-109453 A

In conventional OPC, the mask pattern design data is corrected based on a condition file. For this reason, OPC correction processing is executed with a high convergence rate even for mask patterns that do not require high-accuracy correction. OPC processing time and output after OPC are accompanied by the recent miniaturization of device patterns. There is a serious problem that the data size becomes enormous.

Further, the technique of Patent Document 1 has a problem that the design data size of the photomask becomes enormous.
In the technique of Patent Document 2, there is a problem that an enormous number of test patterns must be prepared.
The technique of Patent Document 3 has a problem that it is difficult to sufficiently cope with various device patterns in recent years.

This case has been made in view of the above-mentioned problems. In the correction processing by OPC, the OPC processing is performed with the correction accuracy required for each functional block corresponding to a wide variety of device patterns, and the output data size is reduced. It is an object of the present invention to provide a photomask design method and program, and a semiconductor device manufacturing method capable of reducing (optimizing) and realizing a significant reduction in time required for correction processing.

The photomask design method of the present case includes a first step of recognizing information of a plurality of functional blocks from photomask data, and first accuracy information of optical proximity effect correction defined in advance for each functional block. A second step for each functional block, and a third step for performing optical proximity effect correction on the functional block based on the first accuracy information.

The photomask design device of the present invention is a photomask design device using optical proximity effect correction, and includes a data storage unit that stores data of the photomask, and a plurality of data according to the data read from the data storage unit. A functional block recognizing unit for recognizing information of the functional block, a first accuracy information storing unit for storing first accuracy information of optical proximity effect correction defined in advance for each functional block, and the first accuracy An accuracy information providing unit that provides the first accuracy information read from the information storage unit for each functional block; and a correction unit that performs optical proximity effect correction on the functional block based on the first accuracy information; including.

The method of manufacturing a semiconductor device according to the present invention includes a step of designing a photomask using optical proximity effect correction, a step of manufacturing a photomask based on the designed mask pattern data, and a semiconductor device using the photomask. Forming a device pattern, wherein the step of designing the photomask includes a first step of recognizing information of a plurality of functional blocks from the data of the photomask, and light pre-defined for each functional block. A second step of providing first accuracy information of proximity effect correction for each functional block; and a third step of performing optical proximity effect correction on the functional block based on the first accuracy information. Including.

The photomask design program of the present case includes a first step of recognizing information of a plurality of functional blocks from photomask data, and first accuracy information of optical proximity effect correction defined in advance for each functional block, It is a program for causing a computer to execute a second step given to each functional block and a third step of performing optical proximity effect correction on the functional block based on the first accuracy information.

According to the present case, in the correction processing by OPC, the OPC processing is performed with the correction accuracy required for each functional block corresponding to various device patterns, the output data size is reduced (optimized), and the correction processing is performed. A significant reduction in the time required can be realized.

FIG. 1 is a block diagram showing a schematic configuration of a photomask designing apparatus according to the first embodiment. FIG. 2 is a flowchart showing the photomask design method according to the first embodiment in the order of steps. FIG. 3 is a flowchart showing a comparative example (prior art) of the first embodiment in the order of steps. FIG. 4 is a schematic diagram showing various types of information recognized by the functional block recognition unit. FIG. 5 is a diagram illustrating an example of the OPC correction map. FIG. 6 is a diagram illustrating an example of functional block rank definition information. FIG. 7 is a diagram illustrating an example of OPC rank information. FIG. 8 is a diagram illustrating an example of a mask set correction map. FIG. 9 is a schematic diagram showing the positional relationship between the photomasks constituting the mask set corresponding to the mask set correction map. FIG. 10 is a schematic diagram illustrating an internal configuration of the personal user terminal device. FIG. 11 is a flowchart showing the MOS transistor manufacturing method according to the third embodiment in the order of steps. FIG. 12 is a schematic cross-sectional view showing a MOS transistor manufactured by the semiconductor device manufacturing method according to the third embodiment.

As described above, the conventional technique has a problem that various data such as an OPC processing time and an output data size after OPC become enormous. In this case, in order to solve this problem, attention was paid to the OPC correction accuracy, and consideration was given to increasing or decreasing the OPC correction accuracy as necessary.

Here, for example, the line width and interval of the mask pattern of the photomask can be considered as targets of the OPC correction accuracy. In this case, high-precision OPC is required if the line width or interval is narrow, and OPC does not require much precision if it is relatively wide. However, the required OPC correction accuracy does not necessarily depend on the line width / interval of the mask pattern. If attention is paid only to the line width / interval of the mask pattern, it becomes difficult to maintain the required OPC correction accuracy due to layout design dependence.

Therefore, in this case, attention is paid to functional blocks (for example, RAM, ROM, PLL, analog circuit (Analog), input / output interface (I / O), etc.) arranged in the design data. As the object of OPC correction accuracy, for example, even if the same line width and interval are used for RAM and I / O, the functional block is used as a reference because the dimensional accuracy of RAM is more important. It is considered the most appropriate to do this. For this reason, it is preferable to provide a strength of OPC correction accuracy as required for each functional block.

In this case, information of a plurality of functional blocks is recognized from the mask pattern design data of the photomask, and OPC first accuracy information defined in advance for each functional block is given to each functional block. Then, OPC is performed on the functional block based on the first accuracy information.

Here, the functional block includes a plurality of layers (photomasks corresponding to element isolation structures, gates, contact holes, wirings, via holes, etc.) according to the constituent elements. In this case, together with the first accuracy information corresponding to each functional block, OPC second accuracy information defined in advance for each layer is given for each layer.
In this case, by using the second accuracy information in addition to the first accuracy information, the OPC correction accuracy is finely defined for each functional block and further for each layer constituting each functional block. As a result, it is possible to perform OPC corresponding to the user's request in a short time with an optimized output data size or the like.

Specifically, first, each functional block arranged in the design data is recognized. As a method for recognizing, an OPC correction map indicating the recognized functional block area is created by using the connection information of the design data and cell naming rules.
Here, the cell naming rule is a cell name rule to prevent child cells (parts) in a functional block from having the same cell name when combining multiple functional blocks on one design data. It is a naming convention to be converted. If this naming convention does not exist, there is a problem that child cells of the functional block are replaced (deformed) when the functional block is synthesized. In this case, this naming convention is expressed as a cell naming rule.
Subsequently, in the created OPC correction map, second accuracy information (OPC rank information) that defines a rank for each layer and first accuracy information (function block rank definition) that defines a rank for each functional block Information) and a mask set correction map that defines the correction accuracy of the OPC process is created.
Then, based on the information of this mask set correction map, OPC processing is performed using a condition file.

In this way, in this case, OPC processing is performed while maintaining the connection accuracy of the upper and lower layers while maintaining the necessary minimum accuracy for each functional block for each layer. That is, each functional block and each layer constituting the functional block are ranked based on the required correction accuracy, and OPC accuracy (for example, convergence rate) given in the calculation is assigned to each rank. As a result, the calculation time can be reduced while sufficiently maintaining the correction accuracy required for the OPC process.

That is, by applying this case, it is possible to avoid excessive OPC correction more than necessary while maintaining the correction accuracy for each functional block. In addition, since the correction accuracy can be maintained for each layer, a target pattern shape can be obtained. Further, by using the connection information of the design data, it is possible to cope with a cell (such as a dummy) that is not on the connection information by reducing the OPC correction accuracy. As a result, the OPC correction process is optimized to avoid an unnecessary OPC process, and effects such as shortening the OPC correction process time and reducing the output data size are expected. Further, by incorporating the OPC correction map, the functional block correction is optimized between the layers, which is extremely effective for forming a device pattern. By applying this case, for example, the OPC correction processing time is expected to be reduced by about 30%, and the output data size is expected to be reduced by about 20% with respect to the prior art.

-Preferred embodiments to which this case is applied-
Hereinafter, specific embodiments to which the present application is applied will be described in detail with reference to the drawings.

[First Embodiment]
In the present embodiment, a photomask design apparatus and a design method using the same are disclosed.
FIG. 1 is a block diagram showing a schematic configuration of a photomask designing apparatus according to the first embodiment. FIG. 2 is a flowchart showing the photomask design method according to the first embodiment in the order of steps, and FIG. 3 is a flowchart showing the comparative example (prior art) of the first embodiment in the order of steps.

(Photomask design equipment)
In FIG. 1, reference numeral 10 denotes a data storage unit for storing various data of the photomask. The data storage unit 10 stores a design data storage unit 11 that stores design data of a mask pattern of a photomask, and connection information (information indicating a connection state such as between wirings and between wirings and vias) in each functional block. It has the connection information storage part 12 to memorize | store, and the cell name information memory | storage part 13 which memorize | stores the name information (cell naming rule) of each cell which comprises each functional block.

Reference numeral 14 denotes a first accuracy information storage unit that stores first accuracy information (functional block rank definition information) of optical proximity effect correction (OPC) defined in advance for each functional block.
Reference numeral 15 denotes a second accuracy information storage unit that stores second accuracy information (OPC rank information) of OPC defined in advance for each layer constituting each functional block.

Specifically, as the design data storage unit 11, the connection information storage unit 12, the cell name information storage unit 13, the first accuracy information storage unit 14, and the second accuracy information storage unit 15, respectively, a database, a computer Various recording media such as a RAM, a ROM, a CD-ROM, a flexible disk, a hard disk, a magnetic tape, a magneto-optical disk, and a nonvolatile memory card can be applied.

Reference numeral 1 denotes a functional block recognition unit for recognizing information on a plurality of functional blocks based on various data read from the data storage unit 10 (mask pattern design data, connection information, cell naming rules, and the like).
Reference numeral 2 denotes a first map creation unit that creates a first map (OPC correction map) representing the area of each functional block based on the information on the functional block recognized by the functional block recognition unit 1.
3 assigns the functional block rank definition information read from the first accuracy information storage unit 14 for each functional block, and assigns the OPC rank information read from the second accuracy information storage unit 15 for each layer. It is the 2nd map creation part which creates 2 maps (mask set correction map).
The second map creation unit 3 calculates the OPC convergence rate for each layer of each functional block based on the functional block rank definition information and the OPC rank information, and posts it on the mask set correction map. This convergence rate is defined as the following formula (1).
OPC convergence rate (%) = {(a + b) / (A + B)} × 100 (1)
Here, a: coefficient of each functional block (correction accuracy), b: coefficient of each layer, A: maximum value of coefficient of functional block, B: maximum value of coefficient of layer.

Reference numeral 4 denotes a correction unit that performs OPC for each layer of each functional block based on the mask set correction map created by the second map creation unit 3.
Reference numeral 16 denotes a photomask data storage unit that stores data of a photomask having a mask pattern subjected to OPC by the correction unit 4.
Specifically, the photomask data storage unit 16 includes various recording media such as databases, computer RAM and ROM, CD-ROM, flexible disk, hard disk, magnetic tape, magneto-optical disk, and nonvolatile memory card. Applicable.

(Photomask design method)
Hereinafter, a photomask design method using the above-described design apparatus will be described with reference to FIG.
First, the functional block recognition unit 1 receives the design data of the photomask mask pattern from the design data storage unit 11 of the data storage unit 10, the connection information in each functional block from the connection information storage unit 12, and the cell name information storage unit 13. The cell naming rule of each cell constituting each functional block is read out from and the information of each functional block is recognized (step S1).
In step S1, for example, as shown in FIG. 4, the functional block recognition unit 1 associates the functional block with the cell name based on the design data, the connection information indicating the functional block and the cell name, the cell naming rule, and the like. Each function block is recognized using the information extracted in the form.

Subsequently, the first map creation unit 2 creates a first map (OPC correction map) representing the area of each functional block based on the information on the functional block recognized by the functional block recognition unit 1 (step S2). ).
An example of the OPC correction map is shown in FIG. The OPC correction map can be created as a recognition area (frame) using different layer numbers for areas of each functional block (here, RAM, ROM, PLL, Analog, I / O), Two-point coordinate notation on the lower left and upper right can also be indicated.

Subsequently, the second map creation unit 3 assigns the functional block rank definition information read from the first accuracy information storage unit 14 for each functional block, and also reads the OPC rank read from the second accuracy information storage unit 15. Information is assigned to each layer, and a second map (mask set correction map) is created (step S3).
In step S3, the second map creation unit 3 calculates the OPC convergence rate for each layer of each functional block based on the functional block rank definition information and the OPC rank information.

An example of functional block rank definition information is shown in FIG. 6, and an example of OPC rank information is shown in FIG. An example of the mask set correction map is shown in FIG.
The functional block rank definition information is information that defines the correction accuracy of each functional block as a coefficient. The OPC rank information is information that defines the accuracy of each layer with a coefficient. The value of the coefficient in each piece of information is appropriately determined by a designer, a user, or the like. Here, as each layer, element separation, gate (electrode, wiring), contact hole, wiring-1 (first layer wiring), via hole-1 (first layer via hole), wiring-2 and subsequent ( Examples of wiring after the second layer) and via holes −1 and later (via holes after the second layer) are illustrated.

The mask set correction map is calculated from the coefficients of each functional block and the coefficients of each layer, and the convergence rate of the OPC process is determined by the above equation (1). Although not shown, the convergence rate of the OPC process includes correction iteration (correction / calculation count).
FIG. 9 schematically shows the positional relationship between the photomasks constituting the mask set corresponding to the mask set correction map. Here, photomasks M1 to M4 are determined for each layer, and function blocks A to E (A: RAM, B: ROM, C: PLL, D) are respectively located in the same area (position) in the photomasks M1 to M4. : Analog, E: I / O).

Subsequently, the correction unit 4 performs OPC for each layer of each functional block based on the mask set correction map created by the second map creation unit 3 (step S4).
Then, photomask data having a mask pattern subjected to OPC by the correction unit 4 is stored in the photomask data storage unit 16 (step S5).

As described above, according to the present embodiment, it is possible to avoid excessively performing OPC with a convergence rate (including iteration) more than necessary while maintaining OPC correction accuracy in units of functional blocks. Become. Further, by using the connection information of the design data, it is possible to lower the OPC correction rank for cells (dummy etc.) that are not in the connection information. In addition, when functional blocks that require the same accuracy are sparsely and densely divided, it is possible to prevent the OPC correction accuracy of the functional blocks arranged in the sparse part from being deteriorated.
By optimizing the OPC correction process by the above method, it is possible to reduce the OPC correction processing time, the output data size, and the like. Further, by incorporating the OPC correction map, the OPC correction processing of the functional block between the layers is optimized, which is extremely effective for device formation.

A comparative example of this embodiment is shown in FIG.
In the OPC correction processing of this comparative example, after the design data of the photomask mask pattern is read, the OPC correction processing is performed based on the OPC correction processing condition file (interval, pattern width, optical conditions, etc.). (Step S101). After step S101, pattern data for creating a photomask is stored (step S102).

Thus, in the comparative example, the OPC correction processing is not provided with a strength, so that the OPC processing time, the output data size after OPC, and the like become enormous.

[Second Embodiment]
Functions of the constituent elements of the photomask design apparatus according to the first embodiment described above (the functional block recognition unit 1, the first map creation unit 2, the second map creation unit 3, the correction unit 4 in FIG. 1), etc. Can be realized by operating a program stored in a RAM or ROM of a computer. Similarly, each step of the photomask design method (steps S1 to S5 in FIG. 2, etc.) can be realized by operating a program stored in a RAM or ROM of a computer. This program and a computer-readable storage medium storing the program are included in the present invention.

Specifically, the program is recorded on a recording medium such as a CD-ROM or provided to a computer via various transmission media. As a recording medium for recording the program, besides a CD-ROM, a flexible disk, a hard disk, a magnetic tape, a magneto-optical disk, a nonvolatile memory card, or the like can be used. On the other hand, as the program transmission medium, a communication medium in a computer network system for propagating and supplying program information as a carrier wave can be used. Here, the computer network is a WAN such as a LAN or the Internet, a wireless communication network, or the like, and the communication medium is a wired line such as an optical fiber or a wireless line.

Further, the program included in the present invention is not limited to the one in which the functions of the above-described embodiments are realized by the computer executing the supplied program. For example, such a program is also included in the present invention when the function of the above-described embodiment is realized in cooperation with an OS (operating system) or other application software running on the computer. Further, when all or part of the processing of the supplied program is performed by the function expansion board or function expansion unit of the computer and the functions of the above-described embodiment are realized, the program is also included in the present invention.

For example, FIG. 10 is a schematic diagram showing an internal configuration of a personal user terminal device. In FIG. 10, reference numeral 1200 denotes a personal computer (PC) having a CPU 1201. The PC 1200 executes device control software stored in the ROM 1202 or the hard disk (HD) 1211 or supplied from the flexible disk drive (FD) 1212. The PC 1200 generally controls each device connected to the system bus 1204.

The program stored in the CPU 1201, the ROM 1202, or the hard disk (HD) 1211 of the PC 1200 implements the procedures of steps S1 to S5 in FIG.

1203 is a RAM that functions as a main memory, work area, and the like of the CPU 1201. A keyboard controller (KBC) 1205 controls instruction input from a keyboard (KB) 1209, a device (not shown), or the like.

1206 is a CRT controller (CRTC), which controls display on a CRT display (CRT) 1210. Reference numeral 1207 denotes a disk controller (DKC). The DKC 1207 controls access to a hard disk (HD) 1211 and a flexible disk (FD) 1212 that store a boot program, a plurality of applications, an editing file, a user file, a network management program, and the like. Here, the boot program is a startup program: a program for starting execution (operation) of hardware and software of a personal computer.

1208 is a network interface card (NIC) that exchanges data bidirectionally with a network printer, another network device, or another PC via the LAN 1220.

[Third Embodiment]
In the present embodiment, a semiconductor device manufacturing method using the photomask design method according to the first embodiment is disclosed. Here, a MOS transistor which is a component of a functional block (for example, RAM) is illustrated as a semiconductor device. Of course, the semiconductor device can be applied to a semiconductor memory other than a MOS transistor (for example, a constituent element of a ROM that is a functional block) and various semiconductor devices that are constituent elements of another functional block.
FIG. 11 is a flowchart showing the MOS transistor manufacturing method according to the third embodiment in the order of steps. FIG. 12 is a schematic cross-sectional view showing a MOS transistor manufactured by the semiconductor device manufacturing method according to the third embodiment.

The semiconductor device manufacturing method of the present embodiment includes a step S21 of designing a photomask using OPC, and a step S22 of manufacturing a photomask using, for example, an electron beam drawing apparatus based on the designed mask pattern data. And step S23 of forming various device patterns of the semiconductor device using the manufactured photomask (here, a mask set including a plurality of photomasks).
Here, step S21 includes steps S1 to S5 described in the first embodiment.

In step S23, first, a resist pattern for element isolation is formed in the element isolation region of the silicon substrate 21 by lithography using a photomask corresponding to the element isolation layer. Using this resist pattern as a mask, the semiconductor substrate is dry etched to form element isolation grooves. The resist pattern is removed by ashing or the like.
Then, an insulating film for embedding the element isolation trench, such as a silicon oxide film, is deposited by CVD or the like, and planarized by a chemical mechanical polishing (CMP) method or the like, and the inside of the element isolation trench is silicon oxide. Then, an STI (Shallow Trench Isolation) element isolation structure 22 is formed.

Subsequently, after a thin insulating film, here a silicon oxide film, is formed on the silicon substrate 21 by a thermal oxidation method or the like, a polycrystalline silicon film is deposited by a CVD method or the like.
Then, a resist pattern for the gate is formed on the polycrystalline silicon film by lithography using a photomask corresponding to the gate layer. Using this resist pattern as a mask, the polycrystalline silicon film and the silicon oxide film are dry-etched to pattern the gate electrode 24 on the silicon substrate 21 with the gate insulating film 23 interposed therebetween. The resist pattern is removed by ashing or the like.

Subsequently, using the gate electrode 24 as a mask, impurities (boron (B ⁺ ) or the like for P-type, phosphorus (P ⁺ ) or arsenic (As ⁺ ) or the like for N-type) are predetermined on the surface layer of the silicon substrate 1. The ion implantation is performed with the dose amount and the acceleration energy. As a result, extension regions 25 are formed on both sides of the gate electrode 24.

Subsequently, an insulating film, here a silicon oxide film, is deposited on the entire surface of the silicon substrate 21 including the gate electrode 24 by CVD or the like.
Then, the entire surface of the silicon oxide film is anisotropically dry etched (etched back) to leave the silicon oxide only on both sides of the gate electrode 24 and the gate insulating film 23, thereby forming the sidewall insulating film 26.

Subsequently, using the gate electrode 24 and the sidewall insulating film 26 as a mask, impurities (such as boron (B ⁺ ) in the case of P type) or phosphorus (P ⁺ ) or arsenic (As in the case of N type) are formed on the surface layer of the silicon substrate 1. ⁺ ) Etc.) is ion-implanted with a predetermined dose and acceleration energy. As a result, source / drain regions 27 partially overlapping with the extension regions 25 are formed on both sides of the sidewall insulating film 26.

Subsequently, an insulating film, here, a silicon oxide film is deposited on the entire surface of the silicon substrate 21 so as to have a film thickness for embedding the gate electrode 24 by a CVD method or the like, thereby forming an interlayer insulating film 28.

Subsequently, a resist pattern for contact holes is formed on the interlayer insulating film 28 by lithography using a photomask corresponding to the contact hole layer. Using this resist pattern as a mask, the interlayer insulating film 28 is dry-etched to form a contact hole exposing a part of the surface of the source / drain region 27. The resist pattern is removed by ashing or the like.
Then, a conductive material, here tungsten (W) or the like is deposited on the interlayer insulating film 28 by a CVD method or the like so as to embed the contact hole via a predetermined glue film or the like, and is flattened by a CMP method or the like. A contact plug 29 filling the inside with W is formed.

Subsequently, a wiring material, here, an Al alloy or the like is deposited on the interlayer insulating film 28 by sputtering or the like.
Then, a resist pattern for contact holes is formed on the wiring material by lithography using a photomask corresponding to the first wiring layer. Using this resist pattern as a mask, the wiring material is dry-etched to form a wiring 31 connected to the contact plug 29. The resist pattern is removed by ashing or the like.

Subsequently, an insulating film, here a silicon oxide film, is deposited on the entire surface of the interlayer insulating film 28 so as to have a film thickness for embedding the wiring 31 by a CVD method or the like, thereby forming an interlayer insulating film 32.

Note that the first-layer wiring may be formed by a so-called damascene method.
Specifically, for example, after forming the interlayer insulating film 32 (the lower layer portion thereof), the wiring groove is formed on the interlayer insulating film 32 by lithography using a photomask corresponding to the wiring groove layer of the first layer wiring. A resist pattern is formed. Using this resist pattern as a mask, the interlayer insulating film 32 is dry-etched to form a wiring groove exposing a part of the surface of the contact plug 29. The resist pattern is removed by ashing or the like.
Then, a conductive material, here copper (Cu) or Cu alloy or the like is deposited by a plating method or the like so as to fill the wiring groove, is flattened by a CMP method or the like, and the wiring filling the wiring groove with Cu or Cu alloy is formed. Form.
Thereafter, an interlayer insulating film 32 (upper layer portion) is formed so as to embed the wiring.

Subsequently, a resist pattern for via holes is formed on the interlayer insulating film 32 by lithography using a photomask corresponding to the via hole layer. Using this resist pattern as a mask, the interlayer insulating film 32 is dry-etched to form a via hole exposing a part of the surface of the wiring 31. The resist pattern is removed by ashing or the like.
Then, a conductive material, here tungsten (W) or the like is deposited on the interlayer insulating film 32 by a CVD method or the like so as to embed the via hole via a predetermined glue film or the like, and is planarized by a CMP method or the like. A via plug 33 for filling the inside with W is formed.

Subsequently, a wiring material, here, an Al alloy or the like is deposited on the interlayer insulating film 32 by a sputtering method or the like.
Then, a resist pattern for contact holes is formed on the wiring material by lithography using a photomask corresponding to the second wiring layer. Using this resist pattern as a mask, the wiring material is dry-etched to form a wiring 34 connected to the via plug 33. The resist pattern is removed by ashing or the like.
Note that the second-layer wiring may be formed by a damascene method as in the first-layer wiring.

Subsequently, an insulating film, here, a silicon oxide film is deposited on the entire surface of the interlayer insulating film 32 so as to have a film thickness for embedding the wiring 34 by CVD or the like, and an interlayer insulating film 35 is formed.
Thereafter, a further upper layer wiring and an interlayer insulating film are formed to complete the MOS transistor.

As described above, according to this embodiment, a photomask is designed by the design method according to the first embodiment, and a MOS transistor is manufactured using a photomask (mask set) produced based on this design. . Therefore, each device pattern constituting the MOS transistor is accurately formed in the desired shape and size, and a highly reliable MOS transistor that can sufficiently meet the demand for further miniaturization and higher integration is realized.

Claims

A first step of recognizing information of a plurality of functional blocks from photomask data;
A second step of providing, for each functional block, first accuracy information of optical proximity effect correction that is defined in advance for each functional block;
And a third step of performing optical proximity effect correction on the functional block based on the first accuracy information.
The functional block is composed of a plurality of layers,
The said 2nd process WHEREIN: The 2nd precision information of the optical proximity effect correction prescribed | regulated previously for every said layer with the said 1st precision information is provided for every said layer, It is characterized by the above-mentioned. The photomask design method described.
The optical proximity effect correction convergence rate is calculated for each of the layers of the functional blocks based on the first accuracy information and the second accuracy information in the second step. 3. A method for designing a photomask according to 2.
In the first step, the photomask mask pattern design data, connection information in each functional block, and name information of each cell constituting each functional block are recognized as the photomask data. The method of designing a photomask according to claim 1, wherein:
A photomask design apparatus using optical proximity correction,
A data storage unit for storing the photomask data;
A functional block recognition unit that recognizes information of a plurality of functional blocks based on the data read from the data storage unit;
A first accuracy information storage unit that stores first accuracy information of optical proximity effect correction defined in advance for each functional block;
An accuracy information giving unit that gives the first accuracy information read from the first accuracy information storage unit for each functional block;
And a correction unit that performs optical proximity correction on the functional block based on the first accuracy information.
The functional block is composed of a plurality of layers,
A second accuracy information storage unit for storing second accuracy information of optical proximity effect correction pre-defined for each layer;
6. The photomask design apparatus according to claim 5, wherein the accuracy information providing unit provides the second accuracy information read from the second accuracy information storage unit for each layer.
The accuracy information giving unit calculates a convergence rate of optical proximity effect correction for each layer of the functional blocks based on the first accuracy information and the second accuracy information. 7. The photomask design apparatus according to 6.
The data storage unit stores, as the photomask data, design data of the mask pattern of the photomask, connection information in each functional block, and name information of each cell constituting each functional block. The photomask design apparatus according to claim 5.
Designing a photomask using optical proximity correction;
Manufacturing a photomask based on the designed mask pattern data;
Forming a device pattern of a semiconductor device using the photomask, and
The step of designing the photomask includes
A first step of recognizing information of a plurality of functional blocks from the photomask data;
A second step of providing, for each functional block, first accuracy information of optical proximity effect correction that is defined in advance for each functional block;
And a third step of performing optical proximity correction on the functional block based on the first accuracy information. A method for manufacturing a semiconductor device, comprising:
The functional block is composed of a plurality of layers,
10. The second step, wherein, in addition to the first accuracy information, second accuracy information for optical proximity effect correction that is defined in advance for each layer is provided for each layer. The manufacturing method of the semiconductor device of description.
The optical proximity effect correction convergence rate is calculated for each of the layers of the functional blocks based on the first accuracy information and the second accuracy information in the second step. 10. A method for manufacturing a semiconductor device according to 10.
In the first step, the photomask mask pattern design data, the connection information of each functional block, and the name information of the cells constituting each functional block are recognized as the photomask data. A method for manufacturing a semiconductor device according to claim 9.
A first step of recognizing information of a plurality of functional blocks from photomask data;
A second step of providing, for each functional block, first accuracy information of optical proximity effect correction that is defined in advance for each functional block;
A photomask design program for causing a computer to execute a third step of performing optical proximity correction on the functional block based on the first accuracy information.
The functional block is composed of a plurality of layers,
14. In the second step, together with the first accuracy information, second accuracy information for optical proximity effect correction defined in advance for each layer is provided for each layer. The photomask design program described.
The optical proximity effect correction convergence rate is calculated for each of the layers of the functional blocks based on the first accuracy information and the second accuracy information in the second step. 14. A photomask design program according to 14.
In the first step, the photomask mask pattern design data, the connection information of each functional block, and the name information of the cells constituting each functional block are recognized as the photomask data. The photomask design program according to claim 13.
A first step of recognizing information of a plurality of functional blocks from photomask data;
A second step of providing, for each functional block, first accuracy information of optical proximity effect correction that is defined in advance for each functional block;
A computer-readable recording medium recording a program for causing a computer to execute a third step of performing optical proximity effect correction on the functional block based on the first accuracy information.
The functional block is composed of a plurality of layers,
18. In the second step, the second accuracy information of the optical proximity effect correction defined in advance for each layer is provided for each layer together with the first accuracy information. The recording medium described.
The optical proximity effect correction convergence rate is calculated for each of the layers of the functional blocks based on the first accuracy information and the second accuracy information in the second step. 18. The recording medium according to 18.
In the first step, the photomask mask pattern design data, the connection information of each functional block, and the name information of the cells constituting each functional block are recognized as the photomask data. The recording medium according to claim 17.