JP2005284272A - Method for correcting mask pattern, method for verifying mask pattern, method for manufacturing photomask, and method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve correction efficiency for correcting deviation in a pattern dimension and to reduce the process time for correcting a mask pattern. <P>SOLUTION: The method for correcting a pattern for correcting a design pattern so as to form a desired pattern on a wafer includes steps of: specifying a allowable dimensional deviation in each design pattern; specifying conditions for pattern correction for each design pattern based on the above allowable dimensional deviation specified to each pattern; and correcting each design pattern based on the conditions for pattern correction specified for each design pattern. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a mask pattern correction method, a mask pattern verification method, a photomask manufacturing method, and a semiconductor device manufacturing method.

  Recent progress in semiconductor manufacturing technology is very remarkable, and semiconductor devices having a minimum processing dimension of 0.13 μm are mass-produced. Such miniaturization is realized by dramatic progress in fine pattern formation techniques such as a mask process technique, an optical lithography technique, and an etching technique.

  In an era when the pattern size is sufficiently large, the shape of the pattern to be formed on the semiconductor wafer is directly drawn as a design pattern, a mask pattern that is faithful to the design pattern is created, and the mask pattern is applied to the resist film on the wafer by a projection optical system. Then, the resist film to which the mask pattern is transferred is etched to form a resist pattern, and the resist pattern is used as a mask to etch the underlying layer of the resist pattern. Could be formed. However, as pattern miniaturization progresses, it has become difficult to faithfully form patterns in each process, and the final pattern (finished pattern) dimensions (finished dimensions) on the wafer are the design patterns. The problem of deviating from the dimensions has arisen. In other words, there has been a problem that the dimensions of the finished pattern deviate from the dimensions of the mask pattern. In particular, in the lithography process and the etching process, which are the most important for achieving microfabrication, the periphery of the pattern to be formed greatly affects the dimensional accuracy of the finished pattern.

  Optical proximity effect correction in which an auxiliary pattern is added to the design pattern in advance so that the dimension of the pattern to be formed by correcting the deviation between the dimensions of the finished pattern and the mask pattern is formed to the desired pattern dimension ( An OPC (Optical Proximity Correction) or a process proximity effect correction (PPC) technique has been reported, and these correction techniques are indispensable techniques for pattern formation (for example, Patent Document 1 or non-patent document). Reference 1).

  In order to realize high-speed circuit operation, particularly in recent years, miniaturization of transistor gate dimensions has progressed at a speed higher than the speed of progress that has been shown so far. The allowable variation is small. When the allowable dimension variation amount is small, the following problem occurs in the pattern correction processing using OPC or PPC.

  First, it is necessary to make the minimum target region for pattern correction, that is, the unit grid finer, and the mask data amount increases accordingly.

  Further, in the rule-based OPC, the correction rule is inevitably complicated, and the processing time and verification time increase.

  Furthermore, in the model-based OPC, it is important to improve the accuracy of predicting the dimensions (finished dimensions) of the pattern (finished pattern) on the wafer. Therefore, the time required for the simulation for improving the prediction accuracy increases.

  These problems are the same not only in gate miniaturization but also in wiring pattern miniaturization.

Conventionally, circuit design is a simulation using a circuit model under the condition that the gate dimension of a transistor has a uniform dimensional variation (for example, ± 10%) or a dimensional variation of a certain length (for example, ± 15 nm). Has been done by. Therefore, in order to guarantee the circuit operation of the circuit designed by simulation, the dimensional deviation between the gate size of the transistor and the design pattern size (in other words, the mask pattern size) of each circuit unit of the circuit is all circuit units. In other words, it is required to fall within the above-mentioned uniform amount of dimensional variation or a certain amount of dimensional variation. The dimensional variation amount of a uniform ratio or the dimensional variation amount of a certain length is set to the allowable dimensional variation amount of the transistor for which the strictest allowable dimensional variation amount of the transistors in all circuit units is required. That is, in order to guarantee the circuit operation, it is necessary to correct the dimensional deviation so as to be within the strictest allowable dimensional variation amount for the transistors in all circuit units. For this reason, the time required for correction becomes longer, and the processing efficiency of correction is reduced.
Japanese Patent Laid-Open No. 9-139067 (page 11, FIG. 1) Photomask Technology and Management.SPIE Vol. 2322, p374-386 (1994) (Large Area Optical Proximity Correction using Pattern Based Corrections, DM Newmark, et al.)

  As described above, in the creation of a mask pattern, when gates and wirings are miniaturized due to demands for increasing the speed of a semiconductor device, the allowable dimensional variation is reduced and the processing time is increased. Furthermore, it is essential to improve the accuracy of prediction of the finished dimensions on the wafer, and the time required for simulation for realizing high accuracy increases. Further, in the circuit design, if the circuit condition is determined with a uniform allowable fluctuation amount that has the strictest dimensional allowable fluctuation, there is a problem that it takes a lot of time to create the mask pattern.

  The present invention has been made in order to solve the above-described problems. A mask pattern correction method, a corrected mask pattern verification method, a corrected and verified photo, which improve the correction processing efficiency of pattern dimension deviation correction. An object of the present invention is to provide a mask manufacturing method and a semiconductor device manufacturing method using the manufactured photomask.

  In order to solve the above problems, a pattern correction method for correcting a design pattern so that a desired pattern is formed on a wafer according to a first aspect of the present invention includes an allowable dimension variation amount for each design pattern. A step of defining, a step of defining a pattern correction condition for each of the design patterns based on the allowable dimensional variation amount respectively defined for each of the design patterns, and the step of defining each of the design patterns And a step of correcting each of the design patterns based on a pattern correction condition.

  A photomask manufacturing method according to a second aspect of the present invention is characterized in that a photomask is manufactured using pattern data of a design pattern corrected by the pattern correction method according to the first aspect.

  A semiconductor device manufacturing method according to a third aspect of the present invention is characterized in that a semiconductor device is manufactured using a photomask manufactured by the photomask manufacturing method according to the second aspect.

  According to a fourth aspect of the present invention, a pattern verification method for verifying a design pattern corrected by the pattern correction method according to the first aspect described above is an allowable dimension variation defined for each corrected design pattern at the time of correction. Defining a pattern verification condition for each of the corrected design patterns based on a quantity; verifying each design pattern based on the pattern verification conditions defined for each of the corrected design patterns; It is characterized by having.

  A photomask manufacturing method according to a fifth aspect of the present invention is characterized in that a photomask is manufactured using pattern data of a design pattern verified by the pattern verification method according to the fourth aspect.

  A semiconductor device manufacturing method according to a sixth aspect of the present invention is characterized in that a semiconductor device is manufactured using a photomask manufactured by the photomask manufacturing method according to the fifth aspect.

  According to the present invention, a mask pattern correcting method, a corrected mask pattern verification method, a corrected and verified photomask manufacturing method, and a manufactured photomask that improve the correction processing efficiency of turn dimension deviation correction It is possible to provide a method of manufacturing a semiconductor device using

  In a semiconductor circuit, generally, it is rather less necessary to set a uniform allowable dimensional variation amount for circuit patterns (for example, gate patterns) of individual circuit units, and to an allowable dimensional variation amount that is set between circuit units. Vary.

  In one embodiment of the present invention, in correction of a mask pattern, a plurality of circuit models having different allowable dimensional variation amounts are prepared for circuit patterns (for example, gate patterns), and individual circuits are selected from the prepared circuit models. Dimensional deviation from the circuit pattern (mask pattern) of each circuit unit by simulating circuit operation using a circuit model with a desired allowable dimensional variation for each unit and correcting the required correction amount pattern according to the simulation result Is within a desired allowable dimensional variation. In this way, pattern correction is performed for each individual circuit unit based on a desired allowable dimension variation, so that a conventional correction method for performing pattern correction based on the most severe allowable dimension variation for all individual circuit units. Compared with the correction efficiency.

  Further, a correction condition is set for each circuit unit based on the determined dimension allowable variation, and correction is performed according to the set correction condition. As described above, the correction efficiency is further improved by setting the correction condition for each circuit unit on the basis of the determined dimensional allowable variation amount and performing the correction according to the set correction condition.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  A mask pattern correction method according to the first embodiment of the present invention will be described with reference to FIGS.

  1 and 2 show pattern layouts of the circuit unit A and the circuit unit B each including a gate pattern (circuit pattern) of a MOS transistor. 3 to 5 are flowcharts of the correction method.

  The gate pattern of the circuit unit A in FIG. 1 has an allowable dimension variation within ± 10%, and the gate pattern of the circuit unit B in FIG. 2 has an allowable dimension variation within ± 12%.

  Prior to the start of the correction flow, a plurality of circuit models having different allowable dimension fluctuation amounts are prepared for circuit patterns (for example, gate patterns).

  Here, the case of correcting the pattern (gate electrode pattern) of the circuit unit A will be described with reference to FIG.

  First, the circuit unit A is selected (step S11).

  Assuming that the allowable dimension fluctuation amount required for the circuit unit A is ± 10%, the MOS having the allowable dimension fluctuation amount set to ± 10% from the plurality of MOS models (circuit models) prepared in advance. A model is selected (step S12).

  Correction conditions are defined for the circuit unit A (step S13). That is, a corner condition (limit condition) that determines the fastest operation / latest operation of the MOS model for the circuit unit A is determined. The corner condition is a condition determined in consideration of the gate dimension allowable variation amount, the device parameter allowable dimension variation amount, the process variation amount, and the like. Furthermore, the best / worst conditions for external factors such as external factor power supply fluctuation and temperature fluctuation are set.

  The circuit operation of the circuit unit A is simulated using the selected MOS model (step S14), and it is determined whether or not the circuit operation is desired from the viewpoint of circuit performance such as operation speed and timing margin (step S15). . That is, it is determined whether or not the dimensional deviation of the gate pattern of the circuit unit A from the mask pattern is within the allowable dimensional variation.

  As a result of this simulation, when it is determined that the circuit unit A does not perform a desired circuit operation, the circuit configuration of the circuit unit A is corrected (step S16). That is, the correction of the circuit unit A is applied.

  After the circuit configuration of the circuit unit A is corrected, the circuit operation of the circuit unit A is simulated again using the selected MOS model to determine whether or not a desired circuit operation is performed.

  As a result of this simulation, when it is determined that the circuit unit A still does not perform the desired circuit operation, the circuit configuration of the circuit unit A is further corrected. In other words, the circuit unit A is further corrected.

  After the circuit configuration of the circuit unit A is corrected, the circuit operation of the circuit unit A is simulated again using the selected MOS model to determine whether or not a desired circuit operation is performed.

  Until the circuit unit A performs a desired circuit operation, correction and determination of the circuit configuration are repeated.

  If it is determined that the circuit unit A operates as a desired circuit, the circuit configuration at that time is determined as a finished circuit unit (step S17). That is, the dimensional deviation of the gate pattern of the circuit unit A from the mask pattern is within the allowable dimensional variation of the MOS model, that is, within ± 10%, which is the desired allowable dimensional variation. Thus, the correction process for the circuit unit A is completed.

  The same applies to the case where the pattern (gate electrode pattern) of the circuit unit B is corrected. Referring to FIG. 4, first, the circuit unit B is selected (step S21).

  Next, if the allowable dimensional variation required for the circuit unit B is ± 12%, a MOS model in which the allowable dimensional variation is set to ± 12% is selected from a plurality of MOS models prepared in advance. (Step S22).

  Correction conditions are defined for the circuit unit B (step S23). That is, the corner condition (limit condition) that determines the fastest operation / latest operation of the MOS model for the circuit unit B is determined. The corner condition is a condition determined in consideration of the gate dimension allowable variation amount, the device parameter allowable dimension variation amount, the process variation amount, and the like. Furthermore, the best / worst conditions for external factors such as external factor power supply fluctuation and temperature fluctuation are set.

  The circuit operation of the circuit unit B is simulated using the selected MOS model (step S24), and it is determined whether or not the circuit operation is desired from the viewpoint of circuit performance such as operation speed and timing margin (step S25). . That is, it is determined whether or not the dimensional deviation of the gate pattern of the circuit unit B from the mask pattern is within the allowable dimensional variation.

  As a result of this simulation, when it is determined that the circuit unit B does not perform a desired circuit operation, the circuit configuration of the circuit unit B is corrected (step S26). That is, correction for the circuit unit B is applied.

  After the circuit configuration of the circuit unit B is corrected, the circuit operation of the circuit unit B is simulated again using the selected MOS model to determine whether or not a desired circuit operation is performed.

  As a result of this simulation, when it is determined that the circuit unit B still does not perform a desired circuit operation, the circuit configuration of the circuit unit B is further corrected. That is, further correction of the circuit unit B is applied.

  After the circuit configuration of the circuit unit B is corrected, the circuit operation of the circuit unit B is simulated again using the selected MOS model to determine whether or not a desired circuit operation is performed.

  Until the circuit unit B performs a desired circuit operation, correction and determination of the circuit configuration are repeated.

  If it is determined that the circuit unit B operates as a desired circuit, the circuit configuration at that time is determined as a finished circuit unit (step S27). That is, the dimensional deviation of the gate pattern of the circuit unit B from the mask pattern is within the allowable dimensional variation of the MOS model, that is, within ± 12%, which is the desired allowable dimensional variation. Thus, the correction process for the circuit unit B is completed.

  In the above description, the case where the pattern of the circuit unit A is corrected and the case where the pattern of the circuit unit B is corrected are individually described.

  Actually, a plurality of circuit units are corrected in a flow consisting of a series of steps. Such a case will be described below with reference to FIG.

  Prior to the start of the correction flow, a plurality of circuit models having different allowable dimension fluctuation amounts are prepared for circuit patterns (for example, gate patterns).

  First, it is determined whether or not circuit configurations have been determined for all circuit units (step S31).

  If it is determined that there is an undetermined circuit unit, one circuit unit is selected (step S32).

  From among a plurality of MOS models (circuit models), a MOS model in which an allowable dimension variation corresponding to the allowable dimension variation defined in the selected circuit unit is defined is selected (step S33).

  Correction conditions are defined for the selected circuit unit (step S34). That is, the corner condition (limit condition) for determining the fastest operation / latest operation of the MOS model is determined for the selected circuit unit. The corner condition is a condition determined in consideration of the gate dimension allowable variation amount, the device parameter allowable dimension variation amount, the process variation amount, and the like. Furthermore, the best / worst conditions for external factors such as external factor power supply fluctuation and temperature fluctuation are set.

  The circuit operation of the selected circuit unit is simulated using the selected MOS model (step S35), and it is determined whether or not the circuit operation is desired from the viewpoint of circuit performance such as operation speed and timing margin ( Step S36). That is, it is determined whether or not the dimensional deviation of the gate pattern of the selected circuit unit from the mask pattern is within the allowable dimensional variation.

  As a result of the simulation, when it is determined that the selected circuit unit does not perform a desired circuit operation, the circuit configuration of the selected circuit unit is corrected (step S37). In other words, correction is performed for the selected circuit unit.

  After correcting the circuit configuration of the selected circuit unit, the circuit operation of the selected circuit unit is simulated again using the selected MOS model to determine whether or not the desired circuit operation is performed.

  As a result of the simulation, when it is determined that the selected circuit unit does not yet perform a desired circuit operation, the circuit configuration of the selected circuit unit is further modified. In other words, further correction is applied to the selected circuit unit.

  After correcting the circuit configuration of the selected circuit unit, the circuit operation of the selected circuit unit is simulated again using the selected MOS model to determine whether or not the desired circuit operation is performed.

  The correction and determination of the circuit configuration are repeated until the selected circuit unit performs a desired circuit operation.

  If it is determined that the selected circuit unit operates as a desired circuit, the circuit configuration at that time is determined as a finished circuit unit (step S38). That is, assuming that the selected circuit unit is the selected circuit unit A and the allowable dimensional variation of the MOS model is ± 10%, the dimensional deviation of the gate pattern of the circuit unit A from the mask pattern. Is within the allowable dimensional variation of the MOS model, that is, within a desired allowable dimensional variation of ± 10%.

  Thus, the correction process for the selected circuit unit is completed.

  Again, it is determined whether circuit configurations have been determined for all circuit units.

  If it is determined that there is an undetermined circuit unit, a new circuit unit is selected. Thereafter, in the same manner as described above, until the selected circuit unit is determined to perform a desired circuit operation, circuit correction, that is, correction correction and operation confirmation by simulation are repeated. When it is determined that the selected circuit unit operates as a desired circuit, the circuit configuration at that time is determined as a finished circuit unit. That is, assuming that the selected circuit unit is the circuit unit B and the allowable dimensional variation of the MOS model is ± 12%, the dimensional deviation of the gate pattern of the circuit unit B from the mask pattern is that of the MOS model. This is within the allowable dimensional variation, that is, within a desired allowable dimensional variation of ± 12%.

  Thus, the correction process for the selected circuit unit is completed.

  Again, it is determined whether circuit configurations have been determined for all circuit units.

  If it is determined that there is an undetermined circuit unit, a new circuit unit is further selected and the same process is performed. On the other hand, if there is no undetermined circuit unit as a result of the determination, the correction operation ends.

  According to the above correction method, pattern correction is performed for each individual circuit unit based on a desired allowable dimension variation, so that it is possible to minimize the amount of correction required for each individual circuit unit, and correction processing is performed. The speed can be improved and the correction processing time can be shortened.

  In the correction of the conventional method, the allowable dimensional variation amount of each pattern of the pattern layout (for example, the diffusion layer pattern, the gate pattern, the wiring pattern, and the contact hole pattern) is determined as a uniform allowable dimensional variation amount for all of these patterns. Therefore, the correction is repeated until all patterns fall within the uniform allowable dimension variation amount regardless of the shape of each pattern, the arrangement environment of each pattern, and the like. Conventionally, since a uniform allowable dimension variation amount is determined for all of the patterns in this way, even for a pattern in which the allowable dimension variation amount is not so large, that is, a pattern for which a high correction accuracy is not required, Correction correction is performed in the same manner as correction correction for a pattern with a small fluctuation amount, that is, a pattern for which high correction accuracy is required, and the correction processing efficiency decreases.

  In this embodiment, an allowable dimension variation is set for each pattern according to the shape of each pattern, the layout environment of each pattern, and the correction parameter is set accordingly. As described above, the allowable dimension variation amount is set for each pattern according to the shape of each pattern, the arrangement environment of the individual patterns, etc., and the allowable amount of variation is small by setting the amount of pattern correction to be driven. For patterns that require high correction accuracy, increase the number of corrections, that is, increase the amount of corrections to improve correction accuracy. On the other hand, patterns that do not have a large allowable dimension variation, that is, high correction accuracy. For a pattern that cannot be corrected, the number of corrections can be suppressed to the minimum necessary number, that is, the correction can be slowed down. That is, the extent of correction correction can be determined according to the allowable dimension fluctuation amount of each pattern, and the correction processing efficiency is improved.

  The pattern data correction condition is a correction convergence condition for determining whether or not to end correction due to a dimensional deviation between a finished pattern and a desired pattern on the wafer calculated from the corrected design pattern data, and correction of the design pattern It includes at least one of the minimum unit area of the region, the maximum amount of movement allowed for the design pattern, the minimum width of the design pattern, and the minimum space width adjacent to the design pattern as a conditional element. Here, the correction convergence condition means that correction is performed, and whether or not the dimension formed on the wafer as a result of the correction is within the allowable dimension is evaluated. Repeat the process of evaluating whether it is within the dimensions. The correction is completed when the allowable dimension is entered, and the correction convergence condition means the allowable dimension amount on the wafer of the pattern.

  FIG. 6 is a diagram showing a pattern layout of one circuit unit of a semiconductor circuit. This pattern layout includes a diffusion layer pattern 1, a gate pattern 2, a wiring pattern 3, and a contact hole pattern 4 that selectively connects them. Contains a pattern.

  As shown in FIG. 6, the pattern layout of the circuit unit includes a portion where patterns are densely arranged or a portion where the patterns are isolated, a portion where a pattern with a wide pattern width is arranged, or a pattern width. A portion where a wide pattern is arranged is mixed. In accordance with these layout features, an allowable dimension variation is defined for each part. As a result, the amount of pattern correction to be driven can be set for each portion, and the correction processing efficiency is improved. In other words, for patterns that strictly pursue correction, the number of correction calculations is increased to improve correction accuracy. On the other hand, for patterns that may require less correction, the number of repeated calculations is suppressed. can do. In the following, how to set the degree of correction, that is, the degree of correction correction, according to features such as the pattern width, pattern density, and a specific part of the pattern will be described.

  In FIG. 6, a region 11 is a region in which the end in the width direction of the gate layer 2 extends outward from the end of the impurity diffusion layer 1 within a process margin. Even if the amount of extension becomes large, there is no problem, but conversely, it becomes a problem when the width ends are terminated inside the diffusion layer 1. If the direction from the end of the diffusion layer 1 toward the outside is defined as a + (plus) direction, and the direction from the end of the diffusion layer 1 toward the inward is defined as a − (minus) direction, + Since the allowable dimensional variation on the side can be set large, the correction may be set loosely, but since the allowable dimensional variation on the-(minus) side cannot be set large, the correction accuracy must be set strictly. . In other words, when the end of the gate layer 2 in the width direction extends outward from the end of the impurity diffusion layer 1, the pattern correction of the gate layer 2 may be slowed down, whereas the gate layer 2 When the end in the width direction terminates inside the diffusion layer 1, it is necessary to tighten the pattern correction of the gate layer 2. In addition, for example, a well-known correction pattern is arranged at the corner so as to emphasize the pattern. Each of the above regions is surrounded by a broken line in FIG.

  The region 12 is a region where the gate layer 2 is disposed on the diffusion layer 2. The allowable variation of the gate dimension is generally a part that is required to be small, and is a part that requires strict correction as compared with other patterns. Therefore, an allowable variation amount with respect to the gate dimension is calculated, and pattern correction corresponding to the allowable variation amount is performed. Since the allowable fluctuation amount of the gate dimension is generally small, the pattern correction amount is strictly controlled.

  The region 13 is a region where the narrow wiring layers 3 are densely packed. It is important that the dense wiring layers 3 are resolved as adjacent patterns within an appropriate process margin. Therefore, the correction amount of the pattern in such a dense region needs to be set strictly for both the + side and the − side when the direction in which the width of the wiring layer increases is +.

  The region 14 is a region where the narrow wiring layer 3 is disposed in isolation. In this case, the width of the wiring layer 3 may be ensured within an appropriate process margin. That is, the pattern correction amount can be set to be moderate in the correction on the + side where the width of the wiring layer increases.

  The region 15 is a region in which the wide wiring layer 3 ′ is arranged in isolation and the contact layer 4 ′ is connected. In this case, similar to the region 14, the pattern correction amount can be set loosely on the + side where the width of the wiring layer increases. However, in the region 15, the contact layer 4 'is connected to the wiring layer 3'. For the wiring layer portion in the vicinity of the connection portion, it is necessary to set the correction driving on the minus side, where the width of the wiring layer is narrowed, and to correct with high accuracy. This is because if the minus side correction accuracy is low, good connection between the wiring layer 3 ′ and the contact hole layer 4 ′ cannot be established, resulting in poor connection.

  Next, the region 16 is a region in which the narrow wiring layer 3 is isolated and the contact layer 4 is connected. In this case, like the region 15, the pattern correction amount can be set loosely on the + side where the width of the wiring layer increases. However, in the region 16, the contact layer 4 is connected to the wiring layer 3. As for the wiring layer portion in the vicinity of the connection portion, like the region 15, it is necessary to set the correction driving on the minus side where the width of the wiring layer 3 is narrowed and to perform the correction with high accuracy. This is because if the minus side correction accuracy is low, the wiring layer 3 and the contact hole layer 4 cannot be connected well, resulting in poor connection.

  The region 17 is a region where the contact hole layer 4 is formed at the tip of the narrow wiring layer 3. In this case, similarly to the regions 15 and 16, the pattern correction amount can be set loosely on the + side where the width of the wiring layer increases. However, on the other hand, in the region 17, the contact layer 4 is connected to the wiring layer 3. For the wiring layer portion in the vicinity of the connecting portion, the correction driving amount on the minus side where the width of the wiring layer is narrowed is set strictly, and it is necessary to correct with high accuracy as in the regions 15 and 16. This is because if the minus side correction accuracy is low, the wiring layer 3 and the contact hole layer 4 cannot be connected well, resulting in poor connection.

  The region 18 is a region at the tip of the narrow wiring layer 3, but unlike the region 17, the contact hole layer 4 is not formed. In this case, even if the correction accuracy of the region 18 is deteriorated, there is almost no effect. Therefore, there is no problem in setting the correction amount regardless of the increase / decrease in the width of the wiring layer 3.

  Next, the region 19 is a region where the wide wiring layers 3 are densely packed. In this case, it is important that the gap between the wiring layers is resolved within an appropriate process margin range. Accordingly, it is sufficient to set the pattern correction amount on the + side where the width of the wiring layer increases strictly, and to set the pattern correction amount on the − side where the width decreases to be loose.

  By the way, it is necessary to correct the design pattern based on the deviation amount between the finished pattern on the wafer calculated from the corrected design pattern and the desired pattern, and clarify the correction convergence condition defined by this deviation amount. Done. Also, the minimum movement amount allowed for the minimum area (grid) to be corrected and the design pattern after correction is specified, or the minimum line width and the minimum space width in the design pattern after correction are secured. Need to be done.

  As a design method, for example, patterns having different allowable dimension fluctuation amounts are defined as patterns of different layers or patterns that can be converted into different layers, and only patterns having the same allowable dimension fluctuation amount are included in the same layer. The conventional correction method of simulating using a circuit model having a uniform allowable dimension variation for each layer can be used.

  The correction for each pattern described above can be applied to all the design patterns to be corrected according to a known OPC or PPC correction procedure, and finally a corrected mask pattern is created. In other words, the correction amount can be set appropriately depending on the combination of the pattern shape including the presence or absence of corners, the width of the pattern, the spacing between adjacent spaces, the positional relationship with other layer patterns including the presence or absence of contact holes, It becomes possible. Thereby, since it is not necessary to perform excessive pattern correction, the time required for pattern correction can be greatly reduced. Further, the design patterns described above can be easily classified by using the current design, rules, and checker (DRC). That is, the processing time required for pattern correction can be greatly improved.

  Next explained is a pattern verification method according to the second embodiment of the invention.

  A case will be described in which it is verified whether or not the deviation of the gate pattern of the circuit unit A corrected through the steps shown in FIG. 3 is within the desired allowable dimension variation.

  First, a verification condition is defined based on an allowable dimension variation when the circuit configuration of the circuit unit A is determined by the correction process. In other words, this verification condition is taken in as an evaluation factor of the correction amount when the circuit configuration of the circuit unit A is determined, and is determined in conjunction with this correction amount. It is verified whether or not the deviation of the corrected circuit unit A gate pattern is within the desired allowable dimension fluctuation amount by simulation using the determined verification condition. As a result of verification, when the deviation of the corrected circuit unit A gate pattern is not within the desired allowable dimension variation, the circuit configuration is corrected, and the circuit configuration is corrected until it is within the desired allowable dimension variation. Repeat the correction.

  All circuit units are verified in the same manner, and for circuit units that do not fall within the desired allowable dimension fluctuation amount, the circuit configuration is corrected, and the circuit configuration is corrected until it falls within the desired allowable dimension fluctuation amount. repeat.

  The simulation for verification can be executed by using a verification tool capable of performing simulation at a full chip level for verifying correction by OPC. When this verification tool is used, a location where there is a deviation between the finished pattern size and the desired pattern size on the wafer obtained from the simulation is displayed, and whether or not the process margin is sufficiently secured at that location is displayed. Indicated. In this case, since the amount of correction for correction is set for each individual circuit unit in the correction in the previous embodiment, if no measures are taken, a sufficient process margin is ensured in the above-described places. It may be determined that it is not. However, as described above, in the verification method of this embodiment, the correction amount when the circuit configuration of the circuit unit A is determined is taken as an evaluation element in the verification condition, that is, such an erroneous determination. Does not occur. Since the verification condition is defined based on the allowable dimensional variation when the circuit configuration of the circuit unit A is determined, the number of verifications is reduced and the verification time is shortened.

  Note that the process margin refers to variations in the amount of exposure irradiated from the exposure apparatus, variations in focus position, illuminance unevenness and shape error of the exposure apparatus illumination, aberrations included in the lens of the exposure apparatus, light transmittance of the lens, manufacturing It is a margin for a process parameter such as a dimensional variation of a mask to be processed or a process parameter such as a dimensional variation amount generated in an etching process or other processing processes.

  As a third embodiment of the present invention, the design pattern data corrected by the pattern correction method or the design pattern data verified by the pattern verification method is used, and the design pattern data corrected by a known method is supported. A photomask having a mask pattern to be manufactured is manufactured. A semiconductor device having a desired pattern on the semiconductor wafer is manufactured using this photomask. Since this photomask has a mask pattern corresponding to the corrected design pattern data, the film pattern formed on the semiconductor wafer has a desired pattern.

  Next, a semiconductor device manufacturing method according to the fourth embodiment of the present invention will be described with reference to FIGS.

  Here, a method for manufacturing a semiconductor device using a defect-inspected mask according to the defect inspection method of the above-described embodiment will be described using a MOS transistor as an example.

  As shown in FIG. 7, a gate insulating film 42 is formed on a silicon semiconductor substrate 41 by a thermal oxidation method, and a polysilicon layer 43 is formed on the gate insulating film by a CVD method. Next, the gate insulating film and the polysilicon layer are patterned to form a gate structure including the polysilicon gate electrode 43 and the gate insulating film 42. In order to form the gate structure, first, a photoresist layer 44 is formed on the polysilicon layer, and then the photoresist layer is patterned to form a photoresist pattern. In this photoresist layer patterning, the mask corrected by the pattern correction method of the above embodiment or the mask 45 verified by the pattern verification method is used. That is, in order to form a gate structure, the mask 45 is disposed on a silicon semiconductor, and a desired pattern is transferred to the photoresist layer by exposing the silicon semiconductor from a light source through the mask 45.

  Subsequently, by patterning the photoresist layer by photolithography, a photoresist layer (photoresist pattern) 44 having a pattern corresponding to the pattern of the mask is formed as shown in FIG.

  Next, using this photoresist pattern as an etching mask, the gate insulating film and the polysilicon layer are patterned to form a gate structure including the polysilicon gate electrode 43 and the gate insulating film 42 as shown in FIG. . Then, using this photoresist pattern, polysilicon layer (polysilicon gate electrode) and gate insulating film as a mask, impurities are implanted into the semiconductor substrate to form source / drain regions 46.

Thereafter, after the photoresist pattern 44 is removed, an interlayer insulating film 47 is formed on the entire surface of the semiconductor substrate by CVD as shown in FIG. Next, openings for contact with the gate electrode and the source / drain regions are formed in the interlayer insulating film. In order to form the opening, first, a photoresist layer 48 is formed on the polysilicon layer, and then the photoresist layer is patterned to form a photoresist pattern. In this photoresist layer patterning, the mask corrected by the pattern correction method of the above embodiment or the mask 49 verified by the pattern verification method is used. That is, in order to form an opening, the above-described mask is arranged on a silicon semiconductor, and a desired pattern is transferred to the photoresist layer by exposing the silicon semiconductor.

Next, by patterning the photoresist layer by photolithography, a photoresist layer (photoresist pattern) 48 having a pattern corresponding to the pattern of the mask is formed as shown in FIG.

Next, using this photoresist pattern as an etching mask, the interlayer insulating film is etched to form openings for contact with the gate electrode and the source / drain regions, as shown in FIG.

Next, after removing the photoresist pattern by a known method, a contact metal 50 is formed in the opening for contact with the gate electrode and the source / drain region and interlayer insulation as shown in FIG. 13 by a known method. A wiring 51 connected to the contact metal is formed on the film. In this semiconductor device manufacturing method, since the mask subjected to the defect inspection by the defect inspection method of the above embodiment is used in each patterning step, the transferred mask pattern is also highly consistent with the reference data. A highly accurate semiconductor device is provided.

  Furthermore, patterns with severe intersections are used as dimension management in factories and as dimension management locations in mask houses. Since these areas require strict tolerances on the wafer, it is necessary to strictly manage the mask dimensions that determine the dimensions on the wafer, and this pattern is also routinely used in factory wafer dimension management. Managed. In addition, a severely intersecting pattern is also used as an experimental pattern for determining the OPC condition. Since the dimensional variation allowed by OPC is small, the experimental results (dimensions obtained from the experiment on the wafer) and the optical calculation results used in OPC must match in this part. Without this match, it is difficult to perform OPC with high accuracy. This is also used for the same reason as an experimental pattern for determining OPC verification conditions.

  Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

The figure which shows the pattern layout of the circuit unit A containing the gate pattern (circuit pattern) of a MOS transistor, The figure which shows the pattern layout of the circuit unit B containing the gate pattern (circuit pattern) of a MOS transistor, FIG. 3 is a flowchart illustrating a correction method according to the first embodiment of the present invention. FIG. 3 is a flowchart illustrating a correction method according to the first embodiment of the present invention. FIG. 3 is a flowchart illustrating a correction method according to the first embodiment of the present invention. FIG. 6 is a diagram showing a pattern layout of a semiconductor device. Sectional drawing of the apparatus structure in one process in the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention. Sectional drawing of the apparatus structure in the process following the process of FIG. 7 in the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention. Sectional drawing of the apparatus structure in the process following the process of FIG. 8 in the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention. Sectional drawing of the apparatus structure in the process following the process of FIG. 9 in the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention. Sectional drawing of the apparatus structure in the process following the process of FIG. 10 in the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention. Sectional drawing of the apparatus structure in the process following the process of FIG. 11 in the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention. Sectional drawing of the apparatus structure in the process following the process of FIG. 12 in the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Diffusion layer, 2 ... Gate layer, 3, 3 '... Wiring layer, 4, 4' ... Contact hole layer, 11, 12, 13, 14, 15, 16, 17, 18, 19 ... Area | region, 41 ... Silicon Semiconductor substrate 42... Gate insulating film 42 43. Polysilicon gate electrode 44. Photoresist layer 45. Mask 46. Source / drain region 47. Interlayer insulating film 48. Photoresist layer 49. 50 ... Contact metal, 51 ... Wiring

Claims (14)

In a pattern correction method for correcting a design pattern so that a desired pattern is formed on a wafer,
A process for defining an allowable dimensional variation for each design pattern;
Defining a pattern correction condition for each of the design patterns based on the allowable dimension variation amount defined for each of the design patterns;
Correcting each design pattern based on the pattern correction conditions respectively defined for each design pattern;
A pattern correction method comprising:   The pattern correction method according to claim 1, wherein each of the design patterns is a gate pattern or a wiring pattern.   The allowable dimension variation amount is based on at least one of a width of each design pattern, a width of a space adjacent to each design pattern, and a length of an extended portion from an element region of each design pattern. The pattern correction method according to claim 1, wherein the pattern correction method is defined.   The pattern correction method according to claim 1, wherein the allowable dimension variation amount is different between a corner portion of each design pattern and a portion other than the corner portion.   The correcting step performs a simulation of a circuit operation of a circuit including each of the design patterns using a circuit model prepared based on the allowable dimension variation amount defined for each of the design patterns. 2. The pattern correction method according to claim 1, wherein the pattern correction method is a step of determining whether or not a predetermined circuit margin is satisfied and repeating the correction until it is determined that the predetermined circuit margin is satisfied.   In the correcting step, based on the pattern correction condition defined for each design pattern, a dimensional deviation between each design pattern and a desired pattern formed on the wafer causes each allowable dimension variation. The pattern correction method according to claim 1, wherein the pattern correction method is a step of correcting each of the design patterns so as to be within an amount.   A photomask manufacturing method for manufacturing a photomask using pattern data of a design pattern corrected by the pattern correction method according to claim 1.   A semiconductor device manufacturing method for manufacturing a semiconductor device using the photomask manufactured by the photomask manufacturing method according to claim 7. A pattern verification method for verifying a design pattern corrected by the pattern correction method according to claim 1,
A step of defining a pattern verification condition for each of the corrected design patterns based on the allowable dimension variation amount specified for each of the corrected design patterns.
Verifying each of the design patterns based on the pattern verification conditions respectively defined for the respective corrected design patterns;
A pattern verification method comprising:   In the verification step, based on the pattern correction conditions respectively defined for each design pattern, a dimensional deviation between each design pattern and a desired pattern formed on the wafer causes each allowable dimension variation. The pattern verification method according to claim 9, wherein the pattern verification method is a step of verifying whether or not the amount is within the quantity.   A photomask manufacturing method for manufacturing a photomask using pattern data of a design pattern verified by the pattern verification method according to claim 9.   The semiconductor device manufacturing method which manufactures a semiconductor device using the photomask manufactured by the photomask manufacturing method of Claim 11.   2. The pattern correction method according to claim 1, wherein each of the design patterns in which the allowable dimension variation amount is defined is a design pattern of a pattern formed in a different layer on the wafer.   The pattern data correction condition is a correction convergence condition for determining whether or not to end correction due to a dimensional deviation between a finished pattern and a desired pattern on the wafer calculated from the corrected design pattern data, and correction of the design pattern It includes at least one of a minimum unit area of a region, a maximum amount of movement allowed for the design pattern, a minimum width of the design pattern, and a minimum space width adjacent to the design pattern as a condition element The pattern correction method according to claim 1.

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