JP2005141104A - Photomask - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a photomask in which changes in device dimensions due to an optical proximity effect in a photolithographic process is prevented when patterns are spaced at a constant distance and the layout area of an integrated circuit is decreased. <P>SOLUTION: Device patterns corrected by minute dimensions from each other are formed on a photomask and transferred onto a substrate to obtain optical proximity characteristic curves 404, 405 and 406 of the pattern dimensions. From the pattern spaces a to e as the intersections of the above curves and an aimed design finish dimension 402, a space which minimizes the layout area of an integrated circuit is selected and adopted to form an integrated circuit pattern on a photomask. Thus, changes in a pattern due to an optical proximity effect can be eliminated even when gate electrodes or the like are closely arranged, and circuit layout can be made in a small area. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a photomask that corrects the optical proximity effect of semiconductor integrated circuit element pattern dimensions, and achieves both improvement in dimensional accuracy and reduction in circuit area.

  2. Description of the Related Art Conventionally, in a semiconductor integrated circuit device, a dimensional variation of a semiconductor element pattern formed by photolithography, in particular, a gate size of a MOS transistor has a great influence on its characteristics when the size of the transistor itself is fine. Since the size of such a gate electrode depends on the interval at which the gates are arranged by the optical proximity effect, in order to reduce the variation in the width of the gate electrode, a single gate pattern space (interval) value is used. A method of creating a gate pattern on a photomask has been used (see, for example, Patent Documents 1 and 2).

Hereinafter, a conventional photomask will be described with reference to the drawings.
FIG. 1A is a layout diagram showing an example in which the transistor gate pattern 102 is arranged with the contact hole pattern 103 interposed therebetween.

  In this figure, the transistor gate pattern 102 and the contact hole pattern 103 are arranged in a defined minimum space, and the target finished dimension of the inter-transistor gate space is defined by the inter-gate space 101.

  On the other hand, FIG. 1B shows a gate electrode having a finished dimension of the transistor gate pattern 102 after a resist pattern is formed by exposure from a gate pattern having a fixed dimension on the mask and a gate electrode is formed by dry etching. This shows the inter-pattern space dependency. As shown in FIG. 1B, when the space between the transistor gates is transferred to the semiconductor substrate, when the design dimension or the target dimension is determined as the inter-gate space 101, the width of the actual transistor gate pattern 102 The finished dimension does not necessarily become the target design dimension 104 due to the optical proximity effect that varies depending on the size of the inter-pattern space dimension and the pattern conversion difference in dry etching. Therefore, the optical proximity effect correction is usually performed mainly on the gate pattern on the photomask.

Next, optical proximity effect correction will be described with reference to FIG. FIG. 2 is a diagram for explaining the optical proximity correction method.
In the figure, the vertical axis represents the finished dimensions of the gate electrode film formed on the semiconductor substrate and dry-etched using the resist pattern as a mask, and the horizontal axis represents the space between the gate patterns. In the figure, a curve 105 shows the inter-pattern space dependence of the gate finish dimension when a gate pattern having a fixed width on a photomask is transferred and formed on a semiconductor substrate. When this photomask is used, if the inter-gate space 101 is set, the gate is formed with a width narrower than the finished target dimension 104 mainly due to the optical proximity effect.

Therefore, in order to perform the optical proximity correction, the mask size is changed by + δ with respect to the pattern size on the mask. Using this optical proximity effect correction, the pattern size on the mask is set so as to be the target design dimension 104 which is the finished dimension of the gate pattern 102 in FIG. A curve 106 shows the dependence of the finished dimension on the semiconductor substrate on the pattern interval (on the substrate) when the photomask after optical proximity correction is used. Then, all of the transistor gate patterns constituting the semiconductor integrated circuit device are created in the inter-gate space 101 to reduce the dimensional variation of the gate electrode.
Japanese Patent Laid-Open No. 10-200109 Japanese Patent Laid-Open No. 10-27796

However, when a gate electrode of a semiconductor integrated circuit device is formed using a single space as in the prior art, there is a problem that the circuit area increases.
For example, as shown in FIG. 3A, which shows a transistor layout pattern formed in a specific region of an integrated circuit, a MOS transistor gate pattern 102 and a contact hole pattern 103 are formed on an active region 301 of a semiconductor substrate. It is assumed that a gate wiring pattern 303 is formed on the isolation region 302 and the isolation region 302 that surround it.

  In such a case, assuming that the correct gate pattern width without the optical proximity effect can be formed when the inter-gate space is 101 in FIG. 1, the inter-gate pattern space 304 is the arrangement rule in the layout of FIG. Since it is larger than the inter-transistor gate space 101 in FIG. 1, when an element in the circuit is configured using only the space 101, the dummy gate pattern 306 is gated as shown in FIG. It must be arranged adjacent to the gate electrode 102 with a space 101 between them. The dummy pattern 306 and the gate wiring pattern 303 must be arranged at least with a minimum interval 307 that does not short-circuit each other. As a result, the size variation due to the optical proximity effect of the transistor gate pattern 102 is eliminated, but the inter-gate pattern space 304 is larger than that in FIG. 3A, and the element area is increased.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a photomask having a pattern subjected to optical proximity effect correction capable of reducing the element area and solving the disadvantages associated with the conventional optical proximity effect correction.

  In order to achieve the above object, a photomask according to claim 1 of the present invention is a photomask used when manufacturing a semiconductor circuit by photolithography, and is used for forming an element component having a predetermined width. A first element pattern having a first pattern dimension, and one or more second element patterns each having a pattern dimension different from the first pattern dimension used to form the element component. And an interval between one or more element components that can form an element component having the predetermined width using the first element pattern, and the predetermined element using the second element pattern. A mask pattern is selected by selecting an interval between arbitrary element components from among one or two or more element component intervals that can form an element component having a width. Characterized by using as down.

According to a second aspect of the present invention, in the photomask according to the first aspect, an interval between the arbitrary element constituent elements is selected so that the area of the semiconductor circuit is minimized.
The photomask according to claim 3 is the photomask according to claim 1 or 2, wherein a pattern dimension of the second element pattern is obtained by adding an arbitrary length to the first pattern dimension. And a pattern dimension obtained by subtracting an arbitrary length from the first pattern dimension.
A photomask according to a fourth aspect is the photomask according to the first aspect, the second aspect, or the third aspect, wherein the element component is a gate electrode.

  As described above, it is possible to provide a photomask having a pattern subjected to optical proximity effect correction that can reduce the element area.

  As described above, an optimal gate for forming a gate electrode pattern in a circuit from a plurality of gate-to-gate spaces prepared in advance so that a desired gate electrode pattern can be formed without being affected by the optical proximity effect. Provided a photomask having a pattern with optical proximity correction that can reduce the element area because a semiconductor integrated circuit device can be laid out using a plurality of optimal inter-gate spaces by selecting the inter-space. can do.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 4 is a diagram for explaining a method for correcting the optical proximity effect of the gate electrode pattern dimension on the photomask according to the embodiment of the present invention.

  For example, when a gate electrode pattern of a transistor is formed on an integrated circuit, a resist pattern is transferred to a semiconductor substrate using a photomask having a specific dimension, and the gate electrode is formed by dry etching. It is assumed that the pattern interval dependency of the pattern finished dimension including the proximity effect and the pattern conversion difference due to dry etching becomes a curve 404.

  When a pattern having this size is used, it is understood that the gate finish size is a design target when the gate interval on the semiconductor substrate is b and e. When a gate electrode pattern having a dimension corrected by ± δ is formed on the mask with reference to the width of the gate electrode pattern on the photomask, a curve indicating the interval dependency of each gate electrode pattern dimension is 405 and 406. In these curves, the distances that become the target design dimension 402 are a, c, and d, and this gate distance can be newly used for the pattern layout of the integrated circuit in addition to b and e. As described above, in the example of FIG. 4, five types of gate pattern intervals a to e can be used by properly using three types of masks having gate electrode dimensions having a predetermined value. Since a gate electrode pattern having an appropriate gate pattern arrangement interval can be selected and applied, the layout area of the integrated circuit can be prevented from increasing even when the optical proximity effect correction is performed.

  That is, a photomask having a proximity effect corrected pattern according to the present invention has a pattern having a specific dimension formed at or near a design target dimension when formed on a semiconductor substrate, and ± δ from the pattern dimension. In addition, these patterns have patterns that are arranged at intervals so as to be formed to one dimension that is a design target when formed on a semiconductor substrate. .

FIG. 5 is a diagram showing a pattern layout example of a semiconductor integrated circuit device manufactured using a photomask having a gate pattern with proximity effect correction as described above.
In FIG. 5A, a small-scale unit circuit is configured on the semiconductor integrated circuit chip 508, and two specific ones are indicated by 501 and 502. As shown in FIG. 5B, the unit circuit 501 has a gate electrode 505 formed on the active region 507 of the semiconductor substrate sandwiched between source / drain contacts, and a gate wiring 506 formed adjacent thereto. Yes. Further, in the unit circuit 502, as shown in FIG. 5C, two gate electrodes 505 are formed on the active region 507 of the semiconductor substrate with a contact interposed therebetween.

  The gate electrode 505 is a pattern that requires a dimensional system having a high gate width. Among the gate pattern intervals a to e, the gate electrode 505 has a design target dimension 402 in FIG. In each of the unit circuits 501 and 502, inter-gate spaces 503 and 504 are selected and formed so that the layout area is not increased and two gate patterns can be separated and resolved by a photolithography process.

  In this way, the optimal gate electrode pattern for forming the gate electrode pattern in the circuit from the plurality of inter-gate spaces prepared in advance so that the desired gate electrode pattern can be formed without being affected by the optical proximity effect. By selecting the space, it is possible to increase the selectivity of the circuit layout design and reduce the space between the gates compared to the case where only a single space, which has been a problem in the past, is used for the element pattern in the circuit. The circuit area in the circuit device can be reduced. In the present embodiment, three types of gate electrode patterns are formed on the basis of a specific gate pattern dimension and corrected by ± δ, and each pattern is formed on the substrate under the influence of the optical proximity effect. Although it has been shown that an optimum one of a plurality of pattern intervals having a design dimension is applied, any number may be used as long as it is a plurality of types, and other methods are possible.

  For example, in FIG. 4, when the target design interval b is first determined, and then a mask having a gate electrode having a certain width is created and a gate electrode pattern is formed on the substrate, the dependency of the pattern width on the interval is If it is the curve 402, a pattern according to the target design can be formed by correcting the pattern width in the direction to increase the pattern and following the curve 404.

  The photomask of the present invention can suppress the element area and is useful for a photomask that corrects the optical proximity effect of the semiconductor integrated circuit element pattern dimensions.

Diagram explaining the optical proximity effect The figure explaining the optical proximity effect correction method The figure which shows the transistor layout method which applied the conventional optical proximity effect correction The figure explaining the optical proximity effect correction method of the gate electrode pattern dimension on the photomask by embodiment of this invention The figure which illustrates the layout of the circuit created using the photomask of this invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Space between gates 102 Gate pattern 103 Contact hole pattern 104 Target design size 105 Curve 106 Curve 301 Active region 302 Separation region 303 Gate wiring pattern 304 Gate space 306 Dummy gate pattern 307 Minimum interval 402 Target design size 404 Curve 405 Curve 406 Curve 501 unit circuit 502 unit circuit 503 space between gates 504 space between gates 505 gate electrode 506 gate wiring 507 active region 508 semiconductor integrated circuit chip

Claims (4)

A photomask used when manufacturing a semiconductor circuit by photolithography,
A first element pattern having a first pattern dimension used to form an element component having a predetermined width;
One or two or more second element patterns each having a pattern dimension different from the first pattern dimension used for forming the element component, and using the first element pattern, the predetermined element An element component having the predetermined width can be formed by using an interval between one or more element components that can form an element component having a width and the second element pattern 1 or A photomask characterized in that an arbitrary element component interval is selected from two or more element component intervals and used as a mask pattern.   2. The photomask according to claim 1, wherein an interval between the arbitrary element constituent elements is selected so that an area of the semiconductor circuit is minimized.   The pattern dimensions of the second element pattern are a pattern dimension obtained by adding an arbitrary length to the first pattern dimension, and a pattern dimension obtained by subtracting an arbitrary length from the first pattern dimension. The photomask according to claim 1 or 2.   The photomask according to claim 1, wherein the element component is a gate electrode.

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