JP2017021263A - Reticle and manufacturing method for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device reducing the number of dummy chips formed with alignment marks and being capable of increasing the number of effective semiconductor chips when performing exposure a plurality of times while relatively moving a semiconductor wafer with respect to a reticle while improving accuracy of superposition inspection of patterns formed by using the reticle.SOLUTION: A reticle comprises: a rectangular transfer pattern arrangement region where a plurality of rectangular semiconductor chip pattern portions are disposed side-by-side in a short axial direction of the plurality of semiconductor chip pattern portions; a first alignment mark pattern and a second alignment mark pattern being adjacent to a first side of a transfer pattern arrangement region in a long axial direction of the semiconductor chip pattern portions and positioned inside the transfer pattern arrangement region; and a third alignment mark pattern and a fourth alignment mark pattern being adjacent to a second side facing the first side of the transfer pattern arrangement region and positioned outside the transfer pattern arrangement region.SELECTED DRAWING: Figure 1

Description

The present invention relates to a reticle (photomask) used for transferring a pattern to a transfer target by photolithography technology. Furthermore, the present invention relates to a method for manufacturing a semiconductor device.

In the manufacturing process of a semiconductor device, a well and an impurity region are formed in a semiconductor wafer, and an oxide insulating film, a polysilicon film, an interlayer insulating film, a metal film, and the like are sequentially formed on the semiconductor wafer. For example, in the case of forming a gate electrode by patterning a polysilicon film, a photoresist is applied on the polysilicon film, and a photolithography technique is used.
A pattern formed on a reticle is transferred to a photoresist.

When transferring the same pattern side by side on the area of one semiconductor wafer, multiple exposures are performed while moving the semiconductor wafer in the vertical and horizontal directions relative to the reticle. Further, the polysilicon film is etched using the photoresist to which the pattern is transferred as a mask, thereby forming a gate electrode having a desired pattern.

An alignment mark pattern is provided on the reticle in order to align the reticle used for patterning each film. The alignment mark pattern is transferred to the photoresist, and an alignment mark is formed on the cured photoresist. The alignment mark formed on the photoresist is used for performing an overlay inspection of each film pattern on the semiconductor wafer.

Conventionally, an alignment mark is formed together with a wafer inspection element called a TEG (test elementary group) in a scribe region which becomes a cutting allowance when a semiconductor wafer on which circuit elements are formed is separated into a plurality of semiconductor chips. It was. On the other hand, in recent years,
In order to increase the number of semiconductor chips that can be manufactured from one semiconductor wafer, the width of the scribe region is reduced and the alignment marks and TEG are formed in the dummy chip. In the present application, the dummy chip refers to a semiconductor chip that cannot be finally used as a product.

As a related technique, Patent Document 1 discloses a photomask capable of reducing the chip size. This photomask has a chip pattern arrangement area in which one or more semiconductor chip pattern portions for transferring a semiconductor chip pattern are arranged on a wafer, and the chip pattern arrangement area is for transferring marks on the wafer. The mark pattern portion including the mark pattern is adjacent to the semiconductor chip pattern portion and separately from the semiconductor chip pattern portion.

For example, since some alignment marks have a size of 100 μm square or more, when this alignment mark is provided in the semiconductor chip pattern portion, the chip size is considerably increased. On the other hand, according to Patent Document 1, since marks such as alignment marks are formed outside the semiconductor chip (dummy chip), an increase in chip size can be avoided.

By the way, in order to improve the accuracy of overlay inspection of a pattern formed using a reticle, it is desirable to arrange a plurality of alignment mark patterns on the reticle at different positions. For example, in paragraphs 0054-0055 and FIG. 3 of Patent Document 1, mark pattern portions 3A, 3B, 3C, and 3D are arranged at the four corners of the chip pattern arrangement region 2, and the mark pattern portion 3E is arranged at the center of the chip pattern arrangement region 2. To improve the manageability of the manufacturing process. However, in that case, five dummy chips are generated in the region of the semiconductor wafer to which the chip pattern arrangement region is transferred in one exposure.

JP 2007-310048 A (paragraphs 0014-0017)

Some aspects of the present invention improve the accuracy of overlay inspection of a pattern formed using a reticle, and perform multiple exposures while moving the semiconductor wafer relative to the reticle. This is related to providing a reticle capable of reducing the number of semiconductor chips (dummy chips) on which alignment marks are formed and increasing the number of effective semiconductor chips.
In addition, some aspects of the present invention relate to providing a semiconductor device manufacturing method and the like that can reduce the number of dummy chips on which alignment marks are formed and increase the number of effective semiconductor chips. ing.

The reticle according to the first aspect of the present invention includes a rectangular transfer pattern arrangement region in which a plurality of rectangular semiconductor chip pattern portions are arranged in the short axis direction of the semiconductor chip pattern portion, and the length of the semiconductor chip pattern portion. A first alignment mark pattern and a second alignment mark pattern located in the transfer pattern arrangement area adjacent to the first side of the transfer pattern arrangement area in the axial direction, and opposed to the first side of the transfer pattern arrangement area A third alignment mark pattern and a fourth alignment mark pattern that are adjacent to the second side and positioned outside the transfer pattern arrangement region.

According to the first aspect of the present invention, the reticle is formed using the reticle by disposing the first and second alignment mark patterns and the third and fourth alignment mark patterns at positions apart from each other. The accuracy of pattern overlay inspection can be improved. A dummy chip on which an alignment mark is formed by forming the first to fourth alignment marks on the same semiconductor chip when performing multiple exposures while moving the semiconductor wafer relative to the reticle. Thus, the number of effective semiconductor chips can be increased. In particular, the reticle according to the first aspect of the present invention is suitable for manufacturing an elongated semiconductor chip.

Here, it is desirable that no alignment mark pattern is provided outside the transfer pattern arrangement region in the major axis direction of the semiconductor chip pattern portion. In that case, the area of the semiconductor wafer can be effectively utilized as compared with the case where the alignment mark pattern is provided outside the transfer pattern arrangement region in the major axis direction of the semiconductor chip pattern portion.

In the above, the coordinates of the first alignment mark pattern in the major axis direction of the semiconductor chip pattern portion are different from the coordinates of the third alignment mark pattern in the direction,
You may make it the coordinate of the 2nd alignment mark pattern in the major axis direction of a semiconductor chip pattern part differ from the coordinate of the 4th alignment mark pattern in this direction.
In that case, the first to fourth alignment marks can be arranged in the major axis direction of the semiconductor chip having a short short side. Therefore, the number of dummy chips on which alignment marks are formed can be reduced and the number of effective semiconductor chips can be increased.

Alternatively, the distance from the first side of the transfer pattern arrangement region to the first and second alignment mark patterns is different from the distance from the second side of the transfer pattern arrangement region to the third and fourth alignment mark patterns. You may do it. In that case, a plurality of alignment marks can be arranged in the minor axis direction of the semiconductor chip to further improve the accuracy of overlay inspection of patterns formed in a plurality of layers.

The method of manufacturing a semiconductor device according to the second aspect of the present invention includes a step (a) of forming a photoresist on a substrate or a film formed on the substrate, and a step of exposing a first region of the photoresist ( b) and a step (c) of exposing the second region of the photoresist, wherein the first region and the second region are adjacent to each other in the minor axis direction of the semiconductor chip pattern and partially overlap with each other, A first alignment mark and a second alignment mark formed by exposure of the first region and a third region formed by exposure of the second region in a region where the first region and the second region overlap. The alignment mark and the fourth alignment mark are located.

According to the second aspect of the present invention, the first alignment mark and the second alignment mark formed by the exposure of the first region in the region where the first region and the second region overlap,
Since the third alignment mark and the fourth alignment mark formed by exposure of the second region are positioned, the number of dummy chips on which the alignment mark is formed is reduced and the number of effective semiconductor chips is increased. be able to.

The top view which shows the structural example of the reticle which concerns on one Embodiment of this invention. The figure which shows the example of a shot image when the several area | region of to-be-transferred object is exposed. The figure which shows the example of the alignment mark used in an overlay inspection. The figure which shows the specific example of an alignment mark. The top view which expands and shows the periphery of an alignment mark. The top view which expands and shows the periphery of an alignment mark. The top view which expands and shows the periphery of an alignment mark. The top view which expands and shows the periphery of an alignment mark.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same referential mark is attached | subjected to the same component and the overlapping description is abbreviate | omitted.
<Reticle composition>
A reticle is a transparent plate formed on glass or quartz or the like, which is a pattern original plate used in the manufacturing process of an electronic component. When transferring a circuit pattern of an electronic component to an object to be transferred by a transfer technique called photolithography. It will be the original edition. In the following, a reticle used for manufacturing a semiconductor device will be described.

FIG. 1 is a plan view showing a configuration example of a reticle according to an embodiment of the present invention. As shown in FIG. 1, the reticle 1 includes a rectangular transfer pattern arrangement area 10 and a transfer pattern arrangement area 10.
The first to fifth alignment mark patterns 21 to 25 located inside and outside the light shielding band 30 and the light shielding band 30 are included. In the transfer pattern arrangement region 10, a plurality of rectangular semiconductor chip pattern portions 11 to 13 surrounded by a line representing a scribe region are arranged in the short axis direction (Y-axis direction in the drawing) of the semiconductor chip pattern portion. Has been placed.

The first and second alignment mark patterns 21 and 22 are adjacent to the first side 10a of the transfer pattern arrangement area 10 in the major axis direction (X-axis direction in the drawing) of the semiconductor chip pattern portion, and are transferred pattern arrangement areas. 10 is located. For example, the first and second alignment mark patterns 21 and 22 are located in the lowermost semiconductor chip pattern portion 11 in FIG.

The third and fourth alignment mark patterns 23 and 24 correspond to the transfer pattern arrangement region 1.
It is adjacent to the second side 10b opposite to the zero first side 10a and is located outside the transfer pattern arrangement region 10. For example, the third and fourth alignment mark patterns 23 and 24 are
In FIG. 1, the semiconductor chip pattern portion 12 is located in a region adjacent to the upper side of the uppermost semiconductor chip pattern portion 12 (region having the same size and shape as the semiconductor chip pattern portion).

The fifth alignment mark pattern 25 is located in the semiconductor chip pattern portion 13 at the approximate center of the transfer pattern arrangement region 10. In order to reduce the number of dummy chips,
The fifth alignment mark pattern 25 may be omitted. In that case, a normal semiconductor chip pattern portion 12 is arranged instead of the semiconductor chip pattern portion 13.

The semiconductor chip pattern portion 12 is a semiconductor chip pattern for patterning an impurity region formed in a semiconductor wafer, an oxide insulating film, a polysilicon film, an interlayer insulating film, or a metal film formed on the semiconductor wafer. Is included. Therefore, the size and shape of the semiconductor chip pattern portion 12 are determined corresponding to the size and shape of the semiconductor chip to be manufactured.

The size and shape of the semiconductor chip pattern portions 11 and 13 may be the same as the size and shape of the semiconductor chip pattern portion 12. The semiconductor chip pattern portions 11 and 13 include an alignment mark pattern, and may further include a pattern for transferring a TEG or a chip identification mark or the like to a transfer target.

The light shielding band 30 blocks light transmission in regions other than the transfer pattern arrangement region 10 and the third and fourth alignment mark patterns 23 and 24 in the reticle 1 so that only a predetermined region of the photoresist is exposed. It is a member to make.

As shown in FIG. 1, the major axis direction of the semiconductor chip pattern portions 11 to 13 (X-axis direction in the drawing)
No alignment mark pattern is provided outside the transfer pattern arrangement region 10 in FIG. Therefore, the area of the semiconductor wafer can be effectively utilized as compared with the case where the alignment mark pattern is provided outside the transfer pattern arrangement region 10 in the X-axis direction. An alignment mark pattern may be provided outside the transfer pattern arrangement region 10 in the major axis direction (X-axis direction in the drawing) of the semiconductor chip pattern portions 11 to 13.

Impurity regions are formed in the semiconductor wafer by implanting impurity ions into the semiconductor wafer using the photoresist to which the pattern of the reticle 1 is transferred as a mask. Also, by etching the film using the photoresist with the transferred pattern as a mask,
A film or opening having a desired pattern is formed.

<Shot image>
FIG. 2 is a view showing an example of a shot image when a plurality of regions to be transferred are exposed using the reticle shown in FIG. In FIG. 2, nine areas A (1
1) to A (3, 3) are shown. In each of the areas A (1, 1) to A (3, 3), mark pattern areas 41 and 43 to which the semiconductor chip pattern portions 11 and 13 of the reticle 1 shown in FIG. 1 are transferred, and the reticle shown in FIG. There is a semiconductor chip pattern region 42 to which one semiconductor chip pattern portion 12 is transferred.

The exposure of the photoresist applied on the semiconductor wafer or the film formed on the semiconductor wafer is performed by moving the semiconductor wafer relative to the reticle shown in FIG. 1 in the vertical direction (Y-axis direction in the figure) and in the horizontal direction ( This is performed a plurality of times while moving in the X-axis direction in the figure.

For example, when the semiconductor chip pattern is transferred to the semiconductor chip pattern region 42 in the region A (2, 1) shown in FIG. 2, the first and second marks are transferred to the mark pattern region 41 in the region A (2, 1). Alignment mark patterns 21 and 22 are transferred. Thereby, the region A (2,
In 1), first and second alignment marks 51 and 52 are formed in the photoresist.

Next, when the semiconductor chip pattern is transferred to the semiconductor chip pattern region 42 in the region A (2, 2), the first and second alignment mark patterns are transferred to the mark pattern region 41 in the region A (2, 2). 21 and 22 are transferred, and the fifth alignment mark pattern 25 is transferred to the mark pattern region 43 in the region A (2, 2). At that time, the region A (2, 1
) In the mark pattern region 41 in the third and fourth alignment mark patterns 23 and 2.
4 is transferred. Thereby, in the region A (2, 2), the first and second photoresists are applied to the photoresist.
, Fifth alignment marks 51, 52, 55 are formed, and in region A (2, 1),
Third and fourth alignment marks 53 and 54 are formed in the photoresist.

Next, when the semiconductor chip pattern is transferred to the semiconductor chip pattern region 42 in the region A (2, 3), the third and fourth alignment mark patterns are transferred to the mark pattern region 41 in the region A (2, 2). 23 and 24 are transferred. Thereby, the third and fourth alignment marks 53 and 54 are formed in the photoresist in the region A (2, 2).

As shown in FIG. 2, in the region A (2, 2), the position of the third alignment mark 53 is adjacent to the position of the first alignment mark 51, but they do not overlap.
Further, the position of the fourth alignment mark 54 is adjacent to the position of the second alignment mark 52, but they do not overlap. As a result, in the region A (2, 2), the number of semiconductor chips (dummy chips) on which alignment marks are formed is “2”. Further, when the fifth alignment mark 55 is omitted, The number of dummy chips to be formed is “1”.

FIG. 3 is a diagram illustrating an example of alignment marks used in overlay inspection.
For example, in overlay inspection of a reference mark formed in a semiconductor wafer and an alignment mark made of a photoresist pattern formed on a semiconductor wafer via a polysilicon film, a first made of a photoresist pattern is used. To fifth alignment marks 51a to 55a are used.

As described above, according to the present embodiment, the first to fourth alignment mark patterns 21 to 24 are arranged at positions apart from each other in the reticle 1 shown in FIG. The accuracy of overlay inspection can be improved. In addition, when the exposure is performed a plurality of times while moving the semiconductor wafer relative to the reticle 1,
By forming the fourth alignment marks 51 to 54 (FIG. 2) on the same semiconductor chip, it is possible to reduce the number of dummy chips on which the alignment marks are formed and increase the number of effective semiconductor chips. In particular, the reticle 1 according to the present embodiment is suitable for manufacturing an elongated semiconductor chip in which the length of the long side of the semiconductor chip is 10 times or more the length of the short side of the semiconductor chip.

<Specific examples of alignment marks>
FIG. 4 is a diagram illustrating a specific example of the alignment mark. FIG. 4A is a plan view showing an alignment mark made of a photoresist, and FIG. 4B is a cross-sectional view showing a state in which a polysilicon film and a photoresist are formed on a semiconductor wafer. .

As shown in FIG. 4B, in the semiconductor wafer 61, LOCOS (local oxidation)
of silicon) or STI (shallow trench isolation) method, etc.
Is formed. A polysilicon film 62 is formed on the semiconductor wafer 61, a liquid photoresist is further applied, and a cured photoresist 63 is formed by exposure using a reticle.

In this example, as shown in FIG. 4A, the reference mark 61a has a square shape with a side length of 15 μm in plan view. On the other hand, the cured photoresist 63 has a shape having a square opening with a side length of 15 μm in a square with a side length of 25 μm in plan view, and serves as an alignment mark. An overlay inspection is performed using an alignment mark composed of the reference mark 61a and the cured photoresist 63.

5 to 8 are enlarged plan views showing the periphery of the alignment mark. 5 and 6
FIG. 7 and FIG. 8 show examples of arrangement of alignment marks when one layer is formed.
Shows an arrangement example of alignment marks when three layers are formed.

<Alignment mark alignment example 1>
FIG. 5 is a plan view showing a first arrangement example of alignment marks. When the short side of the semiconductor chip is short, for example, when the short side is about 50 μm or less, the first and third alignment marks 51 and 53 are placed in the mark pattern region 41 as shown in FIG. It is desirable to arrange in the major axis direction. The second and fourth alignment marks 52 and 54 are also preferably arranged in the major axis direction of the semiconductor chip (see FIG. 2).

In that case, in the reticle 1 shown in FIG. 1, the coordinate (X coordinate) of the first alignment mark pattern 21 in the major axis direction of the semiconductor chip pattern portion is the same as the X coordinate of the third alignment mark pattern 23. Only the value is different. Further, the X coordinate of the second alignment mark pattern 22 is different from the X coordinate of the fourth alignment mark pattern 24 by a predetermined value. Here, the predetermined value is desirably larger than the length of each alignment mark pattern in the X-axis direction.

Thereby, the first to fourth alignment marks 5 are arranged in the major axis direction of the semiconductor chip having a short short side.
1-54 (FIG. 2) can be arranged. The first side 10 of the transfer pattern arrangement region
The distance from a to the first and second alignment mark patterns 21 and 22 is preferably equal to the distance from the second side 10b of the transfer pattern arrangement region to the third and fourth alignment mark patterns 23 and 24. .

<Alignment mark alignment example 2>
FIG. 6 is a plan view showing a second arrangement example of the alignment marks. When the short side of the semiconductor chip is long, for example, when the short side is about 100 μm or more, the first and third alignment marks 51 and 53 are placed in the mark pattern region 41 as shown in FIG. It is desirable to arrange in the minor axis direction. Although not shown in FIG. 6, it is desirable that the second and fourth alignment marks are also arranged in the minor axis direction of the semiconductor chip.

In that case, in the reticle 1 shown in FIG. 1, the first side 10 of the transfer pattern arrangement region.
The distance from a to the first and second alignment mark patterns 21 and 22 is only a predetermined value from the distance from the second side 10b of the transfer pattern arrangement region to the third and fourth alignment mark patterns 23 and 24. To be different. Here, the predetermined value is desirably larger than the length of each alignment mark pattern in the Y-axis direction.

Thereby, a plurality of alignment marks can be arranged in the minor axis direction of the semiconductor chip to further improve the accuracy of overlay inspection of patterns formed in a plurality of layers (see FIG. 8). The X coordinate of the first and second alignment mark patterns 21 and 22 is the third coordinate.
It is desirable that the X coordinate of each of the fourth alignment mark patterns 23 and 24 is equal.

<Alignment mark arrangement example 3>
FIG. 7 is a plan view showing a third arrangement example of alignment marks. For example, alignment marks 51a to 55a are formed when a polysilicon film provided on a semiconductor wafer is patterned using a first reticle. In addition, when the contact hole of the interlayer insulating film provided thereon is patterned using the second reticle, alignment marks 51b to 55b are formed. Further, when the metal film provided thereon is patterned using the third reticle, alignment marks 51c to 55c are formed.

When the short side of the semiconductor chip is short, for example, when the short side is about 50 μm or less, as shown in FIG. 7, in the mark pattern region 41, for example, an alignment mark formed when patterning a polysilicon film 51a and 53a, alignment marks 51b and 53b formed when patterning the contact holes, and alignment marks 51c and 53c formed when patterning the metal film are arranged in the major axis direction of the semiconductor chip. Is desirable. Although not shown in FIG. 7, alignment marks 52a and 54a formed when patterning the polysilicon film, alignment marks 52b and 54b formed when patterning the contact holes, and a metal film are formed. It is desirable to align alignment marks 52c and 54c formed at the time of patterning in the major axis direction of the semiconductor chip.

In that case, the X coordinates of the first to fourth alignment mark patterns 21 to 24 shown in FIG. 1 are different from each other in each reticle, and further different from each other in the first to third reticles. Thus, three layers of alignment marks can be arranged in the major axis direction of the semiconductor chip having a short short side. Note that the distance from the first side 10a of the transfer pattern arrangement region to the first and second alignment mark patterns 21 and 22, and the second side 10b of the transfer pattern arrangement region to the third and fourth alignment marks. Patterns 23 and 24
Are preferably equal to each other in the first to third reticles.

<Alignment mark alignment example 4>
FIG. 8 is a plan view showing a fourth arrangement example of alignment marks. When the short side of the semiconductor chip is long, for example, when the short side is about 100 μm or more, as shown in FIG. 8, the short side of the semiconductor chip is formed when patterning the polysilicon film in the mark pattern region 41. Alignment marks 51a and 53a arranged in the axial direction, alignment marks 51b and 53b formed when patterning the contact holes and arranged in the short axis direction of the semiconductor chip, and formed when patterning the metal film. It is desirable that the alignment marks 51c and 53c arranged in the minor axis direction of the semiconductor chip are arranged side by side in the major axis direction of the semiconductor chip. Although not shown in FIG. 8, the alignment mark 5 formed when patterning the polysilicon film and arranged in the minor axis direction of the semiconductor chip.
2a and 54a, alignment marks 52b and 54b formed when patterning the contact holes and arranged in the minor axis direction of the semiconductor chip, and formed in patterning the metal film and arranged in the minor axis direction of the semiconductor chip Alignment marks 52c and 5
4c are preferably arranged side by side in the major axis direction of the semiconductor chip.

In this case, the distance from the first side 10a of the transfer pattern arrangement region shown in FIG. 1 to the first and second alignment mark patterns 21 and 22 is the third side from the second side 10b of the transfer pattern arrangement region. The distance to the fourth alignment mark patterns 23 and 24 is different. The first and third alignment mark patterns 21 and 2 shown in FIG.
3 are different from each other in the first to third reticles, and the X coordinates of the second and fourth alignment mark patterns 22 and 24 are different from each other in the first to third reticles. Thereby, a plurality of alignment marks can be arranged in the short axis direction and the long axis direction of the semiconductor chip, and the accuracy of overlay inspection of patterns formed in a plurality of layers can be further improved. In each reticle, the X coordinates of the first and second alignment mark patterns 21 and 22 are preferably equal to the X coordinates of the third and fourth alignment mark patterns 23 and 24, respectively.

<Method for Manufacturing Semiconductor Device>
Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described. In the following, as an example, the case where the reticle shown in FIG. 1 is used will be described with reference to FIGS. However, the alignment mark 25 shown in FIG. 1 is omitted.

An N well and a P well are formed in a semiconductor wafer (in this embodiment, a P-type silicon substrate). As shown in FIG. 4, the LOC is formed in a part of the P-type silicon substrate.
The reference mark 61a is formed by OS (local oxidation of silicon) or STI (shallow trench isolation). A polysilicon film 62 is formed on the substrate. The semiconductor device manufacturing method according to the present embodiment can be applied to patterning of the polysilicon film 62, for example.

In step (a), a photoresist is formed on the substrate. In step (b), the first region of the photoresist is exposed. In step (c), the second region of the photoresist is exposed. Here, the first region and the second region are adjacent to each other in the minor axis direction of the semiconductor chip pattern, and part of them overlaps. In the region where the first region and the second region overlap, the first alignment mark and the second formed by exposure of the first region
The third alignment mark and the fourth alignment mark formed by exposure of the second region are positioned.

For example, in FIG. 2, the mark pattern area 41 and the area A (2, 2) in the area A (2, 1).
The whole of 2) corresponds to the first region. The mark pattern area 41 in the area A (2, 2) and the entire area A (2, 3) correspond to the second area. Therefore, the region A (2, 2,
The mark pattern region 41 in () corresponds to a region where the first region and the second region overlap.

By exposing the first area in the step (b), the third and fourth alignment mark patterns 23 and 24 (FIG. 1) are transferred to the mark pattern area 41 in the area A (2, 1). Further, the semiconductor chip pattern is transferred to the semiconductor chip pattern region 42 in the region A (2, 2), and the first and second alignment mark patterns 21 and 22 are transferred to the mark pattern region 41 in the region A (2, 2). (FIG. 1) is transferred.

Next, in the step (c), the second region is exposed to expose the third and fourth alignment mark patterns 23 and 24 (FIG. 1) in the mark pattern region 41 in the region A (2, 2).
) Is transcribed. Further, the semiconductor chip pattern is transferred to the semiconductor chip pattern area 42 in the area A (2, 3), and the first pattern pattern 41 in the area A (2, 3) is not shown in FIG. The second alignment mark patterns 21 and 22 (FIG. 1) are transferred.

Therefore, by removing the uncured photoresist, the semiconductor chip pattern is formed in the semiconductor chip pattern region 42 in the region A (2, 2), and the first and second in the mark pattern region 41. Alignment marks 51 and 52, and third and fourth
Alignment marks 53 and 54 are formed.

As a result, the mark pattern area 41 in the area A (2, 2) includes first and second alignment marks 51 and 52 formed by exposure of the first area in the step (b),
The third and fourth alignment marks 53 and 54 formed by the exposure of the second region in the step (c) are positioned.

Next, the polysilicon film 62 shown in FIG. 4 is etched to form a gate electrode. For example, by diffusing P-type impurities in N wells on both sides of the first gate electrode, P-type impurity regions to be the source / drain of the P-channel MOS transistor are formed. Further, by diffusing N-type impurities in the P-wells on both sides of the second gate electrode, N-type impurity regions to be the source / drain of the N-channel MOS transistor are formed. The semiconductor device manufacturing method according to the present embodiment can also be applied to the formation of impurity regions.

In addition, a BPSG (Boron Phosphorus Silicon) is formed on a substrate on which a transistor or the like is formed.
An interlayer insulating film such as glass) is formed, and the interlayer insulating film is patterned to form a contact hole. The semiconductor device manufacturing method according to the present embodiment can also be applied to patterning of an interlayer insulating film.

Further, a metal film such as aluminum is formed on the substrate on which the interlayer insulating film or the like is formed, and the metal film is patterned to form a wiring. The method for manufacturing a semiconductor device according to this embodiment can also be applied to patterning of a metal film. The wiring layer may have a multilayer structure as necessary.

According to the method for manufacturing a semiconductor device according to the present embodiment, the first alignment mark and the second alignment mark formed by exposure of the first region in the region where the first region and the second region overlap. Since the third alignment mark and the fourth alignment mark formed by the exposure of the second region are positioned, the number of effective semiconductor chips can be reduced by reducing the number of dummy chips on which the alignment marks are formed. Can be increased.

In the above embodiment, a box-shaped mark (BOX mark) is used as the alignment mark.
However, the present invention is not limited to the embodiment described above, and it is also possible to use a cross-shaped mark or the like as an alignment mark in plan view. Thus, many modifications are possible within the technical idea of the present invention by those who have ordinary knowledge in the technical field.

DESCRIPTION OF SYMBOLS 1 ... Reticle, 10 ... Transfer pattern arrangement area, 10a, 10b ... Side of transfer pattern arrangement area, 11-13 ... Semiconductor chip pattern part, 21-25 ... Alignment mark pattern, 30 ... Shading band, 41, 43 ... Mark pattern Region, 42... Semiconductor chip pattern region,
51-55 ... Alignment mark, 61 ... Semiconductor wafer, 61a ... Reference mark, 62 ...
Polysilicon film, 63 ... photoresist

Claims (5)

A rectangular transfer pattern arrangement region in which a plurality of rectangular semiconductor chip pattern portions are arranged side by side in the minor axis direction of the semiconductor chip pattern portion;
A first alignment mark pattern and a second alignment mark pattern located in the transfer pattern arrangement area adjacent to the first side of the transfer pattern arrangement area in the major axis direction of the semiconductor chip pattern portion;
A third alignment mark pattern and a fourth alignment mark pattern, which are located outside the transfer pattern arrangement region adjacent to the second side facing the first side of the transfer pattern arrangement region;
Reticle with The reticle according to claim 1, wherein an alignment mark pattern is not provided outside the transfer pattern arrangement region in the major axis direction of the semiconductor chip pattern portion. The coordinates of the first alignment mark pattern in the major axis direction of the semiconductor chip pattern portion are different from the coordinates of the third alignment mark pattern in the direction, and the second alignment mark in the major axis direction of the semiconductor chip pattern portion The reticle according to claim 1 or 2, wherein coordinates of the alignment mark pattern are different from coordinates of the fourth alignment mark pattern in the direction. The distance from the first side of the transfer pattern arrangement region to the first and second alignment mark patterns is the distance from the second side of the transfer pattern arrangement region to the third and fourth alignment mark patterns. The reticle according to claim 1 or 2, which is different from the above. Forming a photoresist on a substrate or a film formed on the substrate (a);
Exposing a first region of the photoresist (b);
Exposing a second region of the photoresist (c);
The first region and the second region are adjacent to each other in the minor axis direction of the semiconductor chip pattern and partly overlap, and the first region and the second region overlap, The first
A semiconductor device in which a first alignment mark and a second alignment mark formed by exposure of the second region, and a third alignment mark and a fourth alignment mark formed by exposure of the second region are located Manufacturing method.

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