JP2009194323A - Semiconductor wafer and its identification method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor wafer and its identification method which can identify wafer information while using an existing process without forming wafer information by marking and without adding a new process. <P>SOLUTION: A semiconductor wafer 10 has a silicon (semiconductor) substrate 11 and a chip effective region 12 which is defined in the silicon substrate 11 and includes a plurality of chip regions 15. The chip effective region 12 is rotated at a rotation angle in accordance with wafer information from an in-plane prescribed direction L of the silicon substrate 11. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor wafer and a method for identifying the same.

  In a manufacturing process of a semiconductor device such as an LSI, various processes such as film formation and etching are performed on a semiconductor wafer. Before and after these steps, a process called numbering is performed on the semiconductor wafer, and wafer information such as a lot number and a wafer number is imprinted in a dot pattern by a laser on the periphery of the semiconductor wafer. The numbering process may be performed in a mass production factory for semiconductor devices, or may be performed in advance by a semiconductor wafer manufacturer before delivery.

  In a mass production factory for semiconductor devices, an operator visually recognizes such wafer information to recognize the lot number and wafer number of the semiconductor wafer.

  However, the wafer information engraved by numbering has a drawback that it becomes difficult to read due to interference fringes or the like of each film while a plurality of films are laminated thereon.

  When the wafer information is engraved in a dot pattern with a laser, the semiconductor substrate slightly rises around the dots, and a step is formed on the semiconductor substrate. The step becomes a source of particles, and the yield of the semiconductor device may be reduced by the particles.

  Therefore, a technique for identifying a semiconductor wafer without using laser marking is desired. Such a technique is disclosed in Patent Documents 1 and 2, for example.

  In these patent documents, a plurality of notches are formed at the periphery of the semiconductor wafer, and the semiconductor wafer is identified from the positional relationship between the notches.

  However, if a plurality of notches are formed in this way, the risk of the semiconductor wafer breaking from the notches is increased, and a process for forming the notches needs to be newly added, so that labor and cost are required.

The following patent documents 3 to 5 also disclose techniques related to the present invention.
Japanese Patent Laid-Open No. 11-233389 JP 2002-367871 A JP 2001-230165 A JP 2003-347200 A JP-A-4-043358

  An object of the present invention is to provide a semiconductor wafer that can identify wafer information while making use of existing processes without forming wafer information by engraving and without adding new processes, and a method for identifying the same.

  According to an aspect of the present invention, a semiconductor substrate and a chip effective region defined in the semiconductor substrate and including a plurality of chip regions are provided, and the chip effective region is defined in a predetermined direction within the semiconductor substrate surface. A semiconductor wafer characterized by being rotated at a rotation angle corresponding to wafer information is provided.

  According to another aspect of the present invention, a semiconductor substrate, a device pattern above or on the semiconductor substrate, and a position corresponding to wafer information in the same layer as the device pattern are formed. There is provided a semiconductor wafer having an identification mark formed thereon.

  According to still another aspect of the present invention, a chip effective area including a plurality of chip areas is rotated from a predetermined direction within a semiconductor substrate surface by a rotation angle corresponding to wafer information and determined on the semiconductor substrate. A method of identifying a semiconductor wafer is provided, wherein the wafer information is identified based on the rotation angle.

  Further, according to another aspect of the present invention, an identification mark is provided at a position corresponding to wafer information above the semiconductor substrate or in the same layer as the device pattern formed on the semiconductor substrate. According to the present invention, there is provided a semiconductor wafer identification method for identifying the wafer information.

  According to the present invention, the chip effective area is rotated from a predetermined direction at a rotation angle corresponding to the wafer information, and the wafer information is identified from the rotation angle. Therefore, it is not necessary to stamp the wafer information on the semiconductor substrate. Particles can be suppressed and a reduction in the yield of the semiconductor device can be prevented. Furthermore, a new process for writing wafer information is not necessary, and an increase in the number of processes and costs can be suppressed.

  Further, an identification mark may be provided at a position corresponding to the wafer information above the semiconductor substrate or in the same layer as the device pattern formed on the semiconductor substrate, and the wafer information may be identified from the position of the identification mark. In this case, since the identification mark can be formed at the same time as the device pattern in the same layer as the device pattern, a new process is unnecessary. Furthermore, in this case as well, it is not necessary to imprint wafer information on the semiconductor substrate, so that particles caused by the imprinting can be suppressed.

(1) Description of Survey Results Prior to the embodiment of the present invention, a survey conducted by the present inventor will be described.

  FIG. 1 is a plan view of a semiconductor substrate 1 on which wafer information 2 is engraved by a laser.

  The wafer information 2 is for identifying the lot number and wafer number of the semiconductor substrate 1 and is composed of character strings such as numerals and alphabets.

  FIG. 2 is a microscopic image of characters constituting the wafer information 2. As shown in the figure, each character constituting the wafer information 2 is composed of a set of dots D.

  However, since the laser marking is used, the semiconductor substrate 1 rises around one dot D to form a step, and particles P as shown in the figure may be generated from the step. The particles P may cause scratches called scratches on device patterns such as wiring.

  FIG. 3 is a diagram drawn based on a microscopic image of the wiring 3 on which the scratch S is formed in this way. The scratch S causes a defect of the semiconductor chip and reduces the number of good chips cut out from the semiconductor substrate 1.

  On the other hand, FIG. 4 is a microscopic image of the wafer information 2 after a plurality of insulating films are formed on the semiconductor substrate 1. It is understood that the formation of a plurality of insulating films causes interference fringes and makes it difficult to read the wafer information 2.

  The inventor of the present application has come up with an embodiment of the present invention as described below based on the results of such investigation.

(2) First Embodiment FIG. 5 is a schematic diagram for explaining a semiconductor wafer and its identification method according to the present embodiment.

  The semiconductor wafer 10 according to the present embodiment includes a silicon (semiconductor) substrate 11 and a chip effective region 12 defined by the silicon substrate 11 and including a plurality of chip regions 15.

  Among these, the chip effective area 12 is an area where a part of the semiconductor chip does not overlap the outer periphery of the semiconductor wafer 10 and a rectangular semiconductor chip can be cut out in a complete shape.

  A notch 13 indicating the crystal orientation of silicon is provided on the outer periphery of the silicon substrate 10. The semiconductor wafer 10 provided with the notches 13 is called a notch type. Instead of the notch type, an orientation flat type semiconductor wafer 10 in which a linear portion called orientation flat is formed on the outer periphery may be used.

  In this embodiment, the wafer number in one lot is used as wafer information. Then, the chip effective area 12 is rotated from a predetermined direction L in the plane of the semiconductor substrate 11 at a rotation angle corresponding to the wafer number.

  The predetermined direction L is, for example, a direction from the center 14 of the silicon substrate 11 toward the notch 13, and the rotation angle is set to 0 ° with respect to the semiconductor wafer 10 with wafer number 1. When the orientation flat type silicon substrate 11 is used, the direction from the center 14 toward the orientation flat is the predetermined direction L.

  For the semiconductor wafer 10 with wafer number 2, the rotation angle is θ, and for wafer number 3, the rotation angle is 2θ. When the number of wafers constituting one lot is 25, n is a natural number of 25 or less, and the rotation angle of the wafer number n with respect to the semiconductor wafer 10 is (n−1) θ.

  In this way, it is possible to recognize the wafer number within one lot of the semiconductor wafer 10 from the above rotation angle without marking the wafer information on the silicon substrate 11 with a laser.

  FIG. 6 is a perspective view of the cassette 16 containing one lot of semiconductor wafers 10.

  In this example, when the semiconductor wafer 10 is accommodated in the cassette 16, the rotation angle is given to each of the semiconductor wafers 10 in advance, and the direction of the notch 13 is different for each semiconductor wafer 10. In this way, the semiconductor wafer 10 is mounted on the stage of the exposure apparatus in a state where a rotation angle is given in advance by simply taking out the semiconductor wafer 10 from the cassette 16 and transferring it to the exposure apparatus by a transfer robot (not shown). Can be placed.

  FIG. 7 is a perspective view of a cassette 16 according to another example in which one lot of semiconductor wafers 10 is accommodated.

  In this example, the rotation angle is not given to each semiconductor wafer 10 at the time of being accommodated in the cassette 16, and the direction of the notch 13 is the same for all the semiconductor wafers 10. In this case, for example, the wafer number and the slot number of the cassette 16 are made the same, and when the semiconductor wafer 10 of a certain slot number is transferred to the exposure apparatus, the stage of the exposure apparatus is rotated based on the slot number. Thus, the rotation angle as described above can be given.

  According to the present embodiment described above, since laser marking for writing wafer information is not performed on the silicon substrate 11, the generation of particles as described with reference to FIGS. The yield can be improved.

  Furthermore, the wafer information such as the wafer number only needs to correspond to the rotation angle of the chip effective area 12, and since a new process for writing the wafer information is not required, it is possible to suppress an increase in the number of processes and costs.

(3) Second Embodiment In this embodiment, an identification mark is provided at a position corresponding to wafer information in the same layer as a device pattern such as an interlayer insulating film and a gate electrode formed above a silicon substrate.

  The formation part of the identification mark will be described in the following first to third examples.

First Example FIG. 8 is a schematic diagram for explaining a semiconductor wafer and its identification method according to this example. In FIG. 8, the same elements as those described in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and description thereof is omitted below.

  In this example, an identification mark M is provided in the peripheral region 18 of the silicon substrate 11. Then, an angle between a predetermined direction L in the surface of the silicon substrate 11 and a direction N from the center 14 of the silicon substrate 11 toward the identification mark M is made to correspond to the wafer information.

  For example, if the wafer information is a wafer number within one lot, the angle is set to ω for the semiconductor wafer 10 with the wafer number 1.

  For the semiconductor wafer 10 with the wafer number 2, the above angle is 2ω, and for the wafer number 3, the angle is 3ω. When the number of wafers constituting one lot is 25, n is a natural number of 25 or less, and the above-mentioned angle in the semiconductor wafer 10 with wafer number n is nω.

  Such an identification mark M can be formed as follows using peripheral exposure on the semiconductor wafer 10.

  9 to 11 are cross-sectional views showing a method for forming the identification mark M according to this example. In these sectional views, the section in the chip region 15 and the section in the peripheral region 18 of the silicon substrate 11 on which the identification mark M is formed are shown.

  First, steps required until a sectional structure shown in FIG.

  First, an element isolation trench 11a is formed in a p-type silicon substrate 11, and an element isolation insulating film 21 such as a silicon oxide film is formed therein. Such an element isolation structure is called STI (Shallow Trench Isolation).

  Then, a p-type impurity is ion-implanted into the active region defined by the element isolation insulating film 21 to form a p-well 29, and then a MOS transistor TR is formed thereon. The MOS transistor TR includes a gate insulating film 22 made of a thermal oxide film, a gate electrode 23 made of polysilicon, an n-type source / drain region 26, a refractory metal layer 25 made of cobalt silicide and the like.

  Further, a silicon nitride film 27 and a silicon oxide film 28 are formed in this order on the entire upper surface of the silicon substrate 11 by the CVD method, and these films serve as an interlayer insulating film 30. Thereafter, the upper surface of the interlayer insulating film 30 is flattened by the CMP method.

  Next, as shown in FIG. 9B, a positive photoresist 31 is applied on the interlayer insulating film 30.

  Next, as shown in FIG. 9C, the photoresist 31 in each chip region 15 is exposed using an exposure device such as a stepper to form a hole-shaped latent image 31 a in the photoresist 31.

  The photoresist 31 is developed later to form a resist pattern. However, if the resist pattern remains in the peripheral region 18, the interlayer insulating film 30 remains without being etched using the resist pattern as a mask.

  However, in the peripheral region 18, the chip region is missing and a device pattern such as a contact hole becomes incomplete, and the device pattern is peeled off and particles are easily generated.

  Therefore, usually, the photoresist 31 in the peripheral region 18 is exposed and exposed using a peripheral exposure apparatus, and the photoresist 31 in the peripheral region 18 is removed in a later development process.

  However, if all of the photoresist 31 in the peripheral region 18 is removed in this example, the identification mark M made of the interlayer insulating film 30 cannot be formed in the peripheral region 18.

  Therefore, in this example, as shown in FIG. 10A, a part of the exposure light EL emitted from the peripheral exposure apparatus is blocked by a mask or the like (not shown) to form the identification mark M. The photoresist 31 in other parts of the peripheral region 18 is exposed while preventing the photoresist 31 from being exposed.

  Thereby, an unexposed portion 31 b corresponding to the identification mark M is formed in the photoresist 31 in the peripheral region 18.

  Subsequently, as shown in FIG. 10B, the photoresist 31 is developed to form a resist pattern 32.

  FIG. 12 is an enlarged plan view of the resist pattern 32 in the peripheral region 18. The cross-sectional view of the peripheral region 18 in FIG. 10B corresponds to the cross-sectional view along the line AA in FIG.

  As shown in FIG. 12, the resist pattern 32 remains in the portion where the identification mark M is formed later, but the resist pattern 32 is removed by peripheral exposure in the peripheral region 18 in the other portion.

  Then, as shown in FIG. 10C, the interlayer insulating film 30 is etched using the resist pattern 32 as a mask. As a result, when the contact hole 30a having a depth reaching the refractory metal layer 25 is formed in the interlayer insulating film 30 in the chip region 15, the interlayer insulating film 30 is patterned in an island shape in the peripheral region 18.

  Thereafter, the resist pattern 32 is removed as shown in FIG.

  As described above, the identification mark M made of the interlayer insulating film 30 left in an island shape in the same layer as the contact hole 30a which is the device pattern is formed in the peripheral region 18.

  According to the above-described method for forming the identification mark M, it is only necessary to block the exposure light in the portion corresponding to the identification mark M in the peripheral exposure step (FIG. 10A). A new process is not required, and the number of processes and cost increase are not caused.

  Further, such an identification mark M is made of the interlayer insulating film 30, and a color difference is generated between the identification mark M and the periphery where the interlayer insulating film 30 is removed.

  The color originates from the interference fringes generated in the interlayer insulating film 30. For example, the interference fringes X as shown in FIG.

  The identification mark M can be easily distinguished from the surroundings based on such a color difference, and the visibility of the identification mark M can be ensured.

  In the above description, the identification mark M is composed of the interlayer insulating film 30, but this example is not limited to this. The identification mark M can be made of the same material as the device pattern in the same layer as the device pattern of the chip region 15.

  For example, as shown in FIG. 14, the identification mark M may be formed of a conductive film such as polysilicon that forms the gate electrode (conductive pattern) 23.

  Alternatively, as shown in FIG. 15, the identification mark M may be constituted by the element isolation groove 1a.

Second Example FIG. 16 is a schematic diagram for explaining a semiconductor wafer and its identification method according to this example. In FIG. 16, the same elements as those described in the first embodiment and the first example are denoted by the same reference numerals, and description thereof is omitted below.

  In this example, among the plurality of chip areas 15 in the chip effective area 12, the identification mark M is provided in all areas in the chip area 15 located at a position corresponding to the wafer information.

  For example, when the wafer information is a wafer number within one lot, the identification mark M is provided in the entire area of the chip area 15 at the upper left of the figure in the semiconductor wafer 10 having the wafer number 1.

  An identification mark M is provided in the entire area of the right chip area 15 for the semiconductor wafer 10 of wafer number 2, and an identification mark M is further provided in the right chip area 15 of the semiconductor wafer 10 of wafer number 3. To be provided. In this way, by shifting the chip regions 15 one by one, the identification mark M is provided on all of the semiconductor wafers 10 constituting one lot (for example, 25 wafers).

  Thus, by associating the position of the identification mark M with the wafer number, the wafer number can be specified from the position of the identification mark M.

  Various configuration examples of the identification mark M will be described below.

  FIGS. 17 and 18 are examples of cross-sectional views of the semiconductor wafer 10.

  The left side of these figures shows a chip region 15 in which an element such as a MOS transistor TR is provided without an identification mark M. The right side shows the chip region 15 provided with the identification mark M.

  In the example of FIG. 17, the identification mark M is configured by an interlayer insulating film 30 left in an island shape on the entire surface of the corresponding chip region 15.

  On the other hand, in the example of FIG. 18, an opening 30c is formed in the interlayer insulating film 30 in the chip region 15, and the identification mark M is configured by the opening 30c.

  In both cases of FIGS. 17 and 18, the identification mark M causes a difference in color from the surroundings depending on the presence or absence of the interlayer insulating film 30 in the chip region 15, so that the visibility can be ensured.

  Such an identification mark M leaves a resist pattern on the entire surface of the corresponding chip region 15 (FIG. 16) or forms a window when a resist pattern for forming the contact hole 30a is formed on the interlayer insulating film 30. (FIG. 17), the interlayer insulating film 30 may be etched by using the resist pattern as a mask. Such exposure that exposes all the photoresist in one chip region 15 or makes it unexposed is also called a dropout shot.

  According to this, the identification mark M is simultaneously formed in the same layer as the device pattern such as the contact hole 30a, and a new process is not required.

  Further, since it is not necessary to imprint wafer information on the semiconductor substrate 11 with a laser, generation of particles due to a portion imprinted in a dot shape can be suppressed.

  Although the identification mark M is provided in the interlayer insulating film 30 in this example, the identification mark M may be provided in the same layer as the gate electrode 23 or the element isolation trench 11a using the above-described drop shot.

Third Example FIG. 19 is a schematic diagram for explaining a semiconductor wafer and its identification method according to this example. In FIG. 19, the same elements as those described in the second example are denoted by the same reference numerals as those in the second example, and description thereof is omitted below.

  As shown in FIG. 19, the silicon substrate 11 outside the chip effective area 12 has a plurality of invalid chip areas 17 in which the chip shape overlaps the periphery of the substrate and becomes incomplete.

  In this example, the position of the invalid chip area 17 and the wafer information are made to correspond to each other, and the identification mark M is provided in all areas in the invalid chip area 17 at the position corresponding to the wafer information.

  For example, when the wafer information is the wafer number in one lot, the identification mark M is provided in the entire area of the invalid chip area 17 in the upper left of the figure in the semiconductor wafer 10 having the wafer number 1.

  An identification mark M is provided in the entire area of the right invalid chip area 17 for the semiconductor wafer 10 with the wafer number 2, and further identified with the invalid chip area 17 on the right in the semiconductor wafer 10 with the wafer number 3. Mark M is provided. In this way, by shifting the invalid chip area 17 one by one, the identification mark M is provided on all the semiconductor wafers 10 constituting one lot (for example, 25 wafers).

  As in the second example, the identification mark M is simultaneously formed in the same layer as the device pattern using a dropout shot, so that a new process for forming the identification mark M is unnecessary.

  As the device pattern, there is an interlayer insulating film 30 as shown in FIGS. In that case, the identification mark M is configured by an interlayer insulating film 30 (FIG. 17) that remains in an island shape without being etched, and an opening (FIG. 18) formed in the interlayer insulating film 30.

  In addition, the identification mark M may be formed of polysilicon which is a material of the gate electrode 23 in the same layer as the gate electrode 23. Further, the identification mark M may be constituted by the element isolation groove 11a.

  According to this example, the identification mark M is not provided in the chip effective area 12 as in the second example, but the identification mark M is provided in the invalid chip area 17 outside the chip effective area 12. In addition to not sacrificing the number of product chips cut out from the chip, it is possible to effectively use the invalid chip region 17.

  Further, as in the first and second examples, since it is not necessary to laser-engrave the silicon substrate 11, generation of particles due to the laser engraving can be suppressed, and the yield of chips can be prevented from being reduced by the particles. it can.

  The features of the present invention will be described below.

(Appendix 1) a semiconductor substrate;
A chip effective area defined in the semiconductor substrate and including a plurality of chip areas;
A semiconductor wafer, wherein the chip effective area is rotated at a rotation angle corresponding to wafer information from a predetermined direction in the surface of the semiconductor substrate.

(Appendix 2) The wafer information is a wafer number in one lot.
2. The semiconductor wafer according to appendix 1, wherein the rotation angle corresponds to the wafer number.

  (Additional remark 3) The said predetermined direction is a direction which goes to the notch or orientation flat of this semiconductor substrate from the center of the said semiconductor substrate, The semiconductor wafer of Additional remark 1 or Additional remark 2 characterized by the above-mentioned.

(Appendix 4) a semiconductor substrate;
A device pattern formed above or on the semiconductor substrate;
In the same layer as the device pattern, an identification mark formed at a position corresponding to wafer information,
A semiconductor wafer comprising:

(Additional remark 5) The said identification mark is provided in the periphery of the said semiconductor substrate,
The semiconductor wafer according to appendix 4, wherein an angle between a predetermined direction in the surface of the semiconductor substrate and a direction from the center of the semiconductor substrate toward the identification mark corresponds to the wafer information.

(Appendix 6) A chip effective area including a plurality of chip areas is defined in the semiconductor substrate,
The semiconductor wafer according to appendix 4, wherein the identification mark is provided in all areas within one chip area at a position corresponding to the wafer information.

(Appendix 7) A plurality of ineffective chip regions in which the chip shape is incomplete are defined in the semiconductor substrate,
The semiconductor wafer according to appendix 4, wherein the identification mark is provided in all areas in one invalid chip area at a position corresponding to the wafer information.

  (Supplementary Note 8) The semiconductor wafer according to any one of Supplementary Notes 4 to 7, wherein the wafer information is a wafer number in one lot.

(Appendix 9) The device pattern is a hole provided in an insulating film formed above the semiconductor substrate,
The semiconductor wafer according to any one of appendices 4 to 8, wherein the identification mark is an opening formed in the insulating film or the insulating film patterned in an island shape.

(Appendix 10) The device pattern is a conductive pattern formed above the semiconductor substrate,
The semiconductor wafer according to any one of appendices 4 to 8, wherein the identification mark is made of the same material as the conductive pattern.

(Appendix 11) The device pattern is an element isolation groove formed in the semiconductor substrate,
9. The semiconductor wafer according to any one of appendices 4 to 8, wherein the identification mark is a groove formed in the semiconductor substrate.

(Supplementary Note 12) A chip effective region including a plurality of chip regions is rotated at a rotation angle corresponding to wafer information from a predetermined direction in a semiconductor substrate surface, and determined on the semiconductor substrate,
A method for identifying a semiconductor wafer, wherein the wafer information is identified based on the rotation angle.

(Supplementary Note 13) An identification mark is provided at a position corresponding to wafer information above the semiconductor substrate or in the same layer as the device pattern formed on the semiconductor substrate.
A method for identifying a semiconductor wafer, wherein the wafer information is identified based on a position of the identification mark.

(Additional remark 14) The said identification mark is provided in the periphery of the said semiconductor substrate,
14. The semiconductor wafer identification according to appendix 13, wherein an angle between a predetermined direction in the semiconductor substrate surface and a direction from the center of the semiconductor substrate toward the identification mark is associated with the wafer information. Method.

(Supplementary Note 15) A chip effective area including a plurality of chip areas is defined in the semiconductor substrate,
14. The method for identifying a semiconductor wafer according to appendix 13, wherein the identification mark is provided in an entire area within one chip area at a position corresponding to the wafer information.

(Supplementary Note 16) A plurality of invalid chip regions in which the chip shape is incomplete are defined in the semiconductor substrate,
14. The method for identifying a semiconductor wafer according to appendix 13, wherein the identification mark is provided in an entire area within one invalid chip area at a position corresponding to the wafer information.

FIG. 1 is a plan view of a semiconductor substrate on which wafer information is engraved by a laser. FIG. 2 is a microscopic image of characters constituting the wafer information. FIG. 3 is a diagram drawn based on a microscopic image of the wiring in which the scratch is formed. FIG. 4 is a microscopic image of wafer information after forming a plurality of insulating films on a semiconductor substrate. FIG. 5 is a schematic diagram for explaining the semiconductor wafer and its identification method according to the first embodiment of the present invention. FIG. 6 is a perspective view (No. 1) of a cassette containing one lot of semiconductor wafers. FIG. 7 is a perspective view (No. 2) of a cassette containing one lot of semiconductor wafers. FIG. 8 is a schematic diagram for explaining the semiconductor wafer and the identification method thereof according to the first example of the second embodiment of the present invention. FIGS. 9A to 9C are cross-sectional views (part 1) showing a method of forming the identification mark M included in the semiconductor wafer according to the first example of the second embodiment of the present invention. FIGS. 10A to 10C are sectional views (No. 2) showing a method for forming the identification mark M provided in the semiconductor wafer according to the first example of the second embodiment of the present invention. FIG. 11 is a cross-sectional view (No. 3) illustrating the method for forming the identification mark M included in the semiconductor wafer according to the first example of the second embodiment of the present invention. FIG. 12 is an enlarged plan view of the resist pattern in the peripheral region in the semiconductor wafer according to the first example of the second embodiment of the present invention. FIG. 13 is a diagram showing an example of interference fringes seen with the identification mark M of the first example of the second embodiment of the present invention. FIG. 14 is a cross-sectional view of the first example of the second embodiment of the present invention in the case where the identification mark M is made of polysilicon of the gate electrode. FIG. 15 is a cross-sectional view of the first example of the second embodiment of the present invention in which the identification mark M is configured by the element isolation groove. FIG. 16 is a schematic diagram for explaining a semiconductor wafer and its identification method according to a second example of the second embodiment of the present invention. FIG. 17 is a cross-sectional view of the semiconductor wafer according to the second example of the second embodiment of the present invention when the identification mark M is formed of an island-shaped interlayer insulating film. FIG. 18 is a cross-sectional view of the semiconductor wafer according to the second example of the second embodiment of the present invention when the identification mark M is formed from the opening of the interlayer insulating film. FIG. 19 is a schematic diagram for explaining a semiconductor wafer and its identification method according to the third example of the second embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Wafer information, 3 ... Wiring, 10 ... Semiconductor wafer, 11 ... Silicon substrate, 12 ... Chip effective area, 13 ... Notch, 14 ... Center, 15 ... Chip area, 16 ... Cassette, 17 ... Invalid Chip region, 18 ... peripheral region, 11a ... element isolation trench, 21 ... element isolation insulating film, 22 ... gate insulating film, 23 ... gate electrode, 25 ... refractory metal layer, 26 ... n-type source / drain region, 27 ... Silicon nitride film, 28 ... silicon oxide film, 29 ... p well, 30 ... interlayer insulating film, 30a ... contact hole, 31 ... photoresist, 31a ... latent image, 31b ... unexposed portion, 32 ... resist pattern, L ... predetermined Direction, M ... identification mark, N ... direction from the center to the identification mark, TR ... MOS transistor.

Claims (5)

A semiconductor substrate;
A chip effective area defined in the semiconductor substrate and including a plurality of chip areas;
A semiconductor wafer, wherein the chip effective area is rotated at a rotation angle corresponding to wafer information from a predetermined direction in the surface of the semiconductor substrate. A semiconductor substrate;
A device pattern formed above or on the semiconductor substrate;
In the same layer as the device pattern, an identification mark formed at a position corresponding to wafer information,
A semiconductor wafer comprising: Providing the identification mark on the periphery of the semiconductor substrate;
3. The semiconductor wafer according to claim 2, wherein an angle between a predetermined direction in the surface of the semiconductor substrate and a direction from the center of the semiconductor substrate toward the identification mark corresponds to the wafer information. A chip effective area including a plurality of chip areas is determined on the semiconductor substrate by rotating at a rotation angle according to wafer information from a predetermined direction in the semiconductor substrate surface,
A method for identifying a semiconductor wafer, wherein the wafer information is identified based on the rotation angle. In the same layer as the device pattern formed on or above the semiconductor substrate, an identification mark is provided at a position corresponding to the wafer information,
A method for identifying a semiconductor wafer, wherein the wafer information is identified based on a position of the identification mark.

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