JP2009267199A - Semiconductor device and production method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of utilizing a wafer ID with high visiblity also in a post-process, and to provied its production method. <P>SOLUTION: The production method of a semiconductor device includes a step of printing a first wafer ID 20, with a laser marker on a silicon substrate 11; a step of forming first to third interlayer insulating films 12-14 on the silicon substrate; a step of forming a passivation film 15 on the first to third interlayer insulating films; and a step of printing with a laser marker a second wafer ID 2 on the passivation film and superimposed on the first wafer ID 20. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device and a manufacturing method thereof that can use a wafer ID having high visibility even in a later process.

  3A and 3B and FIGS. 4A and 4B are cross-sectional views for explaining a conventional method of manufacturing a semiconductor device. 3A and 4A are cross-sectional views showing a part of the product chip region of the silicon wafer, and FIG. 3B and FIG. 4B are respectively shown in FIG. It is sectional drawing which shows a part of printing exclusive area | region located in the notch vicinity of the silicon wafer shown.

  First, as shown in FIG. 3B, a wafer ID is printed by a laser marker on a print-dedicated area 1a located near the notch of the silicon wafer (silicon substrate) 11. As a result, a plurality of recesses 20 are formed in the silicon substrate 11 (only one recess is shown in FIG. 3B), and the wafer ID is printed by these recesses 20. At this time, an element or the like is not yet formed in the product chip region shown in FIG. The wafer ID is used for process management and quality control in the pre-process and post-process (see, for example, Patent Document 1).

  Thereafter, as shown in FIGS. 4A and 4B, a LOCOS oxide film 3 is formed on the silicon substrate 11 by the LOCOS method. Next, a gate oxide film 4 is formed on the silicon substrate 11 located inside the LOCOS oxide film 3 by a thermal oxidation method. Since the thickness of the gate oxide film must be changed depending on the type of transistor, it is necessary to form a plurality of types of gate oxide films having different thicknesses on the same silicon substrate 11. Specifically, a thermal oxidation (gate oxidation) process and an oxide film removal process are repeated on the silicon substrate 11.

  Next, a gate electrode 5 made of a polysilicon film is formed on the gate oxide film 4, and impurities are ion-implanted using the gate electrode 5 as a mask, whereby an LDD region 7 is formed in the silicon substrate 11. Next, sidewalls 6 are formed on the side walls of the gate electrode 5, and impurities are ion-implanted using the sidewalls 6 and the gate electrode as a mask, whereby source / drain regions are formed in the silicon substrate 11.

  Thereafter, a first interlayer insulating film 12 made of a silicon oxide film is formed on the entire surface including the gate electrode 5, and contacts located on the gate electrode 6 and the source / drain regions respectively are formed on the first interlayer insulating film 12. Hole 12a is formed. Next, the first W plug 9 is embedded in the contact hole 12 a, and the first Al alloy wiring 10 is formed on the first W plug 9 and the first interlayer insulating film 12.

  Next, a second interlayer insulating film 13 made of a silicon oxide film is formed on the first Al alloy wiring 10 and the first interlayer insulating film 12, and the first Al alloy is formed on the second interlayer insulating film 13. A first via hole 13a located on the wiring 10 is formed. Next, a second W plug 16 is embedded in the first via hole 13 a, and a second Al alloy wiring 17 is formed on the second W plug 16 and the second interlayer insulating film 13.

  Thereafter, a third interlayer insulating film 14 made of a silicon oxide film is formed on the second Al alloy wiring 17 and the second interlayer insulating film 13, and the second Al alloy is formed on the third interlayer insulating film 14. A second via hole 14 a located on the wiring 17 is formed. Next, a third W plug 18 is embedded in the second via hole 14 a, and an Al pad 19 is formed on the third W plug 18 and the third interlayer insulating film 14. Next, a passivation film 15 made of a silicon nitride film is formed on the Al pad 19 and the third interlayer insulating film 14, and a pad opening 15 a for exposing the Al pad 19 is formed in the passivation film 15.

JP 2005-166885 A (paragraph 0011)

  By the way, after the wafer ID 20 is printed by the laser marker at the start of the previous process, the semiconductor manufacturing process is performed on the silicon substrate 11 as described above. That is, the semiconductor manufacturing process is also performed in the print-only area 1a on which the wafer ID 20 is printed. For this reason, in the wafer ID 20 that has good visibility immediately after printing, the level difference of the depression 20 in the printing portion decreases with each passing through the process. As a result, the visibility of the wafer ID 20 becomes worse, and the previous process is performed. At the stage of completion, the visibility may be so poor that it cannot be confirmed with the naked eye.

The reason why the level difference of the depression 20 in the printing portion is reduced is as follows. When a plurality of types of gate oxide films having different thicknesses are formed on the same silicon substrate 11, the thermal oxidation (gate oxidation) process and the oxide film removal process are repeated on the silicon substrate 11, so that the thermal oxidation process is also performed in the print-only area 1a. The oxide film removing process is repeated, and as a result, the level difference of the depression 20 in the printing portion is reduced.
Further, since the wafer ID 20 formed on the silicon substrate 11 is visually recognized through the first to third interlayer insulating films 12 to 14 and the passivation film 15 at the stage where the pre-process is completed, the visibility is so large that it cannot be confirmed with the naked eye. May be worse. In particular, in a multilayer metal process for forming a multilayer wiring, a plurality of interlayer insulating films are stacked. Therefore, the thicker the total laminated film thickness of the interlayer insulating films, the larger the number of interlayer insulating films. , Visibility becomes worse.

  For the above reasons, at the stage where the pre-process is completed, the visibility may deteriorate so that it cannot be confirmed with the naked eye. As a result, the post-process (the process after the process shown in FIG. Etc.), the wafer ID may not be automatically recognized in each manufacturing apparatus or may be erroneously recognized. As a result, the load of the operator's wafer ID confirmation work increases.

  On the other hand, it is conceivable that the depth of the depression 20 in the printing portion is increased in advance in anticipation of a decrease in the level difference of the depression 20 in the printing portion. However, when the depth is increased, there is a concern that the amount of particles generated after laser irradiation with the laser marker increases.

  The present invention has been made in consideration of the above-described circumstances, and an object of the present invention is to provide a semiconductor device that can use a highly visible wafer ID even in a later process and a method for manufacturing the same.

In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention includes a step of printing a first wafer ID on a semiconductor substrate with a laser marker,
Forming an interlayer insulating film on the semiconductor substrate;
Forming a passivation film on the interlayer insulating film;
Printing the second wafer ID on the passivation film with the laser marker over the first wafer ID;
It is characterized by comprising.

  According to the semiconductor device manufacturing method, since the second wafer ID is printed on the passivation film so as to overlap the first wafer ID, the wafer ID having high visibility can be used even in a subsequent process.

A method of manufacturing a semiconductor device according to the present invention includes a step of printing a first wafer ID on a semiconductor substrate with a laser marker;
Forming an interlayer insulating film on the semiconductor substrate;
Printing the second wafer ID with the laser marker on the interlayer insulating film, overlaid on the first wafer ID;
Forming a passivation film on the interlayer insulating film;
It is characterized by comprising.

In the method for manufacturing a semiconductor device according to the present invention, it is preferable that the character of the second wafer ID is exactly the same as the character of the first wafer ID.
In the method of manufacturing a semiconductor device according to the present invention, the laser marker used in the step of printing the second wafer ID is the same type device as the laser marker used in the step of printing the first wafer ID. It is preferable that

A semiconductor device according to the present invention includes a first wafer ID printed on a semiconductor substrate,
An interlayer insulating film formed on the semiconductor substrate;
A passivation film formed on the interlayer insulating film;
A second wafer ID printed on the passivation film overlying the first wafer ID;
It is characterized by comprising.

A semiconductor device according to the present invention includes a first wafer ID printed on a semiconductor substrate,
An interlayer insulating film formed on the semiconductor substrate;
A second wafer ID printed on the interlayer insulating film so as to overlap the first wafer ID;
A passivation film formed on the interlayer insulating film;
It is characterized by comprising.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
1A and 1B are cross-sectional views for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 1A shows a part of a product chip region of a silicon wafer. FIG. 1B is a cross-sectional view showing a part of the print-only area located in the vicinity of the notch of the silicon wafer shown in FIG. 2A is a plan view showing the entire print-only area shown in FIG. 1B, and FIG. 2B is an enlarged plan view of the printed wafer ID shown in FIG. 2A. It is.

  First, as shown in FIGS. 1B and 2A, a wafer ID is printed with a laser marker in a print-only area 1a located in the vicinity of the notch 1b of the silicon wafer (silicon substrate) 11. As a result, a plurality of recesses 20 are formed in the silicon substrate 11 (only one recess is shown in FIG. 1B), and the wafer ID is printed by these recesses 20. This wafer ID is used for process control and quality control in the pre-process and post-process.

  Thereafter, as shown in FIGS. 1A and 1B, a LOCOS oxide film 3 is formed on the silicon substrate 11 by the LOCOS method. Next, a gate oxide film 4 is formed on the silicon substrate 11 located inside the LOCOS oxide film 3 by a thermal oxidation method. In order to form a plurality of types of transistors on the silicon substrate 11, the gate oxide film having a different thickness is formed by changing the thickness of the gate oxide film according to each type. Specifically, a thermal oxidation (gate oxidation) process and an oxide film removal process are repeated on the silicon substrate 11. As a result, the thermal oxidation process and the oxide film removal process are repeated in the print-only area 1a, and as a result, the level difference of the depression 20 in the print portion is reduced.

  Next, a polysilicon film is deposited on the entire surface including the gate oxide film 4 by a CVD (chemical vapor deposition) method, and this polysilicon film is patterned to form a polysilicon film on the gate oxide film 4. A gate electrode 5 is formed. Next, LDD regions 7 are formed in the silicon substrate 11 by ion-implanting impurities using the gate electrode 5 and the LOCOS oxide film 3 as a mask.

  Next, a silicon oxide film or a silicon nitride film is deposited on the entire surface including the gate electrode 5 by a CVD method, and the silicon oxide film or the silicon nitride film is etched back, so that a sidewall 6 is formed on the side wall of the gate electrode 5. It is formed. At this time, the silicon substrate 11 in the print-only area 1a shown in FIG. 1B is in a state where a LOCOS oxide film, a gate oxide film, a silicon oxide film for forming a sidewall, and the like are not formed. Next, impurities are ion-implanted using the sidewalls 6 and the gate electrode 5 as a mask, whereby source / drain regions are formed in the silicon substrate 11.

  Thereafter, a first interlayer insulating film 12 made of a silicon oxide film is formed on the entire surface including the gate electrode 5 by a CVD method, and a resist pattern (not shown) is formed on the first interlayer insulating film 12. Next, by etching the first interlayer insulating film 12 using this resist pattern as a mask, contact holes 12 a located on the gate electrode 6 and the source / drain regions are formed in the first interlayer insulating film 12. . At this time, a first interlayer insulating film 12 is formed on the silicon substrate 11 in the print-only area 1a shown in FIG.

  Next, a W film is deposited in the contact hole 12a and on the first interlayer insulating film 12 by a sputtering method. Next, the W film existing on the first interlayer insulating film 12 is removed by CMP (Chemical Mechanical Polishing) or etch back, whereby the first W plug 9 is embedded in the contact hole 12. Next, an Al alloy film is deposited on the first W plug 9 and the first interlayer insulating film 12 by a sputtering method, and this Al alloy film is patterned to thereby form the first W plug 9 and the first interlayer film. A first Al alloy wiring 10 is formed on the insulating film 12. At this time, the W film and the Al alloy film are not formed on the first interlayer insulating film 12 in the print-only area 1a shown in FIG.

  Next, a second interlayer insulating film 13 made of a silicon oxide film is formed on the first Al alloy wiring 10 and the first interlayer insulating film 12 by a CVD method, and a resist is formed on the second interlayer insulating film 13. A pattern (not shown) is formed. Next, by etching the second interlayer insulating film 13 using this resist pattern as a mask, a first via hole 13 a located on the first Al alloy wiring 10 is formed in the second interlayer insulating film 13. . At this time, a second interlayer insulating film 13 is formed on the first interlayer insulating film 12 in the print-only area 1a shown in FIG.

  Next, a W film is deposited by sputtering in the first via hole 13a and on the second interlayer insulating film 13. Next, the second W plug 16 is embedded in the first via hole 13a by removing the W film existing on the second interlayer insulating film 13 by CMP or etch back. Next, an Al alloy film is deposited on the second W plug 16 and the second interlayer insulating film 13 by a sputtering method, and this Al alloy film is patterned, whereby the second W plug 16 and the second interlayer film are patterned. A second Al alloy wiring 17 is formed on the insulating film 13. At this time, the W film and the Al alloy film are not formed on the second interlayer insulating film 13 in the print-dedicated region 1a shown in FIG.

  Thereafter, a third interlayer insulating film 14 made of a silicon oxide film is formed on the second Al alloy wiring 17 and the second interlayer insulating film 13 by the CVD method, and a resist is formed on the third interlayer insulating film 14. A pattern (not shown) is formed. Next, by etching the third interlayer insulating film 14 using this resist pattern as a mask, a second via hole 14 a located on the second Al alloy wiring 17 is formed in the third interlayer insulating film 14. . At this time, a third interlayer insulating film 14 is formed on the second interlayer insulating film 13 in the print-only area 1a shown in FIG.

  Next, a W film is deposited by sputtering in the second via hole 14 a and on the third interlayer insulating film 14. Next, the third W plug 18 is embedded in the second via hole 14a by removing the W film existing on the third interlayer insulating film 14 by CMP or etch back. Next, an Al alloy film is deposited on the third W plug 18 and the third interlayer insulating film 14 by a sputtering method, and this Al alloy film is patterned to thereby form the third W plug 18 and the third interlayer film. An Al pad 19 is formed on the insulating film 14. At this time, the W film and the Al alloy film are not formed on the third interlayer insulating film 14 in the print-only area 1a shown in FIG.

  Next, a passivation film 15 made of a silicon nitride film is formed on the Al pad 19 and the third interlayer insulating film 14 by a CVD method, and a resist pattern (not shown) is formed on the passivation film 15. Next, by etching the passivation film 15 using this resist pattern as a mask, a pad opening 15 a that exposes the Al pad 19 is formed in the passivation film 15. At this time, a passivation film 15 is formed on the third interlayer insulating film 14 in the print-only area 1a shown in FIG. In this embodiment, the passivation film 15 made of a silicon nitride film is formed. However, a passivation film having a laminated structure of a silicon oxide film and a silicon nitride film may be formed, or a passivation film made of a silicon oxide film may be formed. A film may be formed.

  Thereafter, the wafer ID is printed with a laser marker on the passivation film 15 in the print-only area 1a shown in FIG. As a result, a plurality of recesses 2 are formed in succession on the passivation film 15 (only one recess is shown in FIG. 1B), and the wafer ID 2 as shown in FIG. Printed in the area 1a. The laser marker printing conditions at this time are as follows.

(1) The wafer ID character to be printed is exactly the same as the character printed at the start of the previous process.
(2) The character type, size, and pitch of the recesses 2 are the same.
(3) Use the same type of laser marker.
(4) Overprint at the same position.

  In FIG. 1B, the bottom of the depression 2 reaches the third interlayer insulating film 14, but the bottom of the depression 2 depends on conditions such as the thickness of the passivation film 15 and the irradiation intensity of the laser. May be located on the second interlayer insulating film 13 or the first interlayer insulating film 12, or may be located on the silicon substrate 11.

  According to the above embodiment, the wafer ID 20 is printed in the print-only area 1a at the start of the previous process, and the wafer ID 2 is again printed in the same area under the same conditions at the end of the previous process. For this reason, even if the visibility deteriorates at the end of the pre-process, the wafer ID 2 printed again at the end of the pre-process ensures good automatic recognition of the wafer ID in each manufacturing apparatus in the post-process (for example, bump process, inspection process, etc.) Can be implemented. Thereby, it is possible to suppress an increase in the load of the operator's wafer ID confirmation work, and it is possible to satisfactorily use the wafer ID for process management and quality management in the subsequent process. Therefore, both the pre-process and the post-process can be managed using a wafer ID having excellent visibility.

  In this embodiment, since the same character is again printed at the same position at the end of the previous process, the dead space on the wafer (printing shown in FIG. 2A) is performed as compared with the case of printing at another position. The dedicated area 1a) can be minimized.

  Further, in the present embodiment, when the previous process is completed, the same character as the character printed at the start of the previous process is printed again, so that there is an advantage that both the previous process and the subsequent process can be managed with the same wafer ID.

  In the present embodiment, the laser marker used when printing again at the end of the previous process is printed at the same conditions using the same type of device as the laser marker used at the start of the previous process. The positional deviation between the wafer ID and the wafer ID printed at the end of the previous process can be suppressed. Therefore, it is possible to suppress the occurrence of a failure when the wafer ID is automatically recognized in the subsequent process.

  Moreover, in this embodiment, since the laser marker conventionally used for printing at the start of the previous process can be used as a laser marker used for printing at the end of the previous process, there is no need to purchase a new laser marker. In addition, it is not necessary to purchase a new reading device that automatically recognizes the wafer ID in a later process. Therefore, it can be realized without increasing the cost.

  In this embodiment, the printing at the end of the previous process is performed after the passivation film 15 is formed. However, the printing at the end of the previous process is performed before the formation of the passivation film and before the first to third. It is also possible to carry out after forming any of the interlayer insulating films. Even in this case, the effects described above can be expected.

  The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

9A and 9B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment. FIG. 3A is a plan view showing the entire print-only area shown in FIG. 1B, and FIG. 2B is an enlarged plan view of the printed wafer ID shown in FIG. (A), (B) is sectional drawing for demonstrating the manufacturing method of the conventional semiconductor device. (A), (B) Sectional drawing for demonstrating the manufacturing method of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon wafer, 1a ... Print-only area | region, 1b ... Notch, 2 ... Depression (wafer ID), 3 ... LOCOS oxide film, 4 ... Gate oxide film, 5 ... Gate electrode, 6 ... Side wall, 7 ... LDD area | region, DESCRIPTION OF SYMBOLS 8 ... Source / drain region, 9 ... 1st W plug, 10 ... 1st Al alloy wiring, 11 ... Silicon substrate, 12 ... 1st interlayer insulation film, 12a ... Contact hole, 13 ... 2nd interlayer insulation Film 13a ... first via hole, 14 ... third interlayer insulating film, 14a ... second via hole, 15 ... passivation film, 15a ... pad opening, 16 ... second W plug, 17 ... second Al Alloy wiring, 18 ... third W plug, 19 ... Al pad, 20 ... depression (wafer ID)

Claims (6)

Printing a first wafer ID on a semiconductor substrate with a laser marker;
Forming an interlayer insulating film on the semiconductor substrate;
Forming a passivation film on the interlayer insulating film;
Printing the second wafer ID on the passivation film with the laser marker over the first wafer ID;
A method for manufacturing a semiconductor device, comprising: Printing a first wafer ID on a semiconductor substrate with a laser marker;
Forming an interlayer insulating film on the semiconductor substrate;
Printing the second wafer ID with the laser marker on the interlayer insulating film, overlaid on the first wafer ID;
Forming a passivation film on the interlayer insulating film;
A method for manufacturing a semiconductor device, comprising:   3. The method of manufacturing a semiconductor device according to claim 1, wherein the character of the second wafer ID is exactly the same as the character of the first wafer ID.   4. The laser marker used in the step of printing the second wafer ID according to claim 1, wherein the laser marker used in the step of printing the first wafer ID is the same type device as the laser marker used in the step of printing the first wafer ID. A method for manufacturing a semiconductor device, comprising: A first wafer ID printed on a semiconductor substrate;
An interlayer insulating film formed on the semiconductor substrate;
A passivation film formed on the interlayer insulating film;
A second wafer ID printed on the passivation film overlying the first wafer ID;
A semiconductor device comprising: A first wafer ID printed on a semiconductor substrate;
An interlayer insulating film formed on the semiconductor substrate;
A second wafer ID printed on the interlayer insulating film so as to overlap the first wafer ID;
A passivation film formed on the interlayer insulating film;
A semiconductor device comprising:

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