JP5105824B2 - Method for forming mask structure and method for forming fine pattern using the same - Google Patents

Method for forming mask structure and method for forming fine pattern using the same Download PDF

Info

Publication number
JP5105824B2
JP5105824B2 JP2006289669A JP2006289669A JP5105824B2 JP 5105824 B2 JP5105824 B2 JP 5105824B2 JP 2006289669 A JP2006289669 A JP 2006289669A JP 2006289669 A JP2006289669 A JP 2006289669A JP 5105824 B2 JP5105824 B2 JP 5105824B2
Authority
JP
Japan
Prior art keywords
mask
film
forming
method
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2006289669A
Other languages
Japanese (ja)
Other versions
JP2008060517A (en
Inventor
斗烈 李
漢九 趙
昔柱 李
起成 呂
次元 高
成坤 丁
Original Assignee
三星電子株式会社Samsung Electronics Co.,Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to KR10-2006-0082119 priority Critical
Priority to KR1020060082119A priority patent/KR100763538B1/en
Application filed by 三星電子株式会社Samsung Electronics Co.,Ltd. filed Critical 三星電子株式会社Samsung Electronics Co.,Ltd.
Publication of JP2008060517A publication Critical patent/JP2008060517A/en
Application granted granted Critical
Publication of JP5105824B2 publication Critical patent/JP5105824B2/en
Application status is Active legal-status Critical
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

Description

  The present invention relates to a method for forming a mask structure and a method for forming a fine pattern using the same in the manufacture of a semiconductor device, and more particularly, the present invention relates to a method for forming a mask structure and a mask structure used as an etching mask. The present invention relates to a method for forming a fine pattern using an object.

  Recently, semiconductor devices are manufactured with high integration. As a result, in the manufacture of semiconductor devices, formation of a fine pattern is required. Accordingly, in the manufacture of semiconductor devices, a SADP (Self Alignment Double Patterning) process or the like has been developed in order to form a finer pattern.

  In the SADP process, after a first mask pattern is formed on the semiconductor substrate, a sacrificial film is continuously formed on the surface of the first mask pattern. Thereafter, a hard mask film is formed on the sacrificial film, and the hard mask film is partially removed. Then, the sacrificial film is removed, and a hard mask film remaining on the semiconductor substrate is formed in the second mask pattern. Then, a mask pattern including the first mask pattern and the second mask pattern is formed on the semiconductor substrate.

  As described above, the single mask pattern is not formed in the SADP process, but a double mask pattern of the first mask pattern and the second mask pattern is formed. Therefore, when the SADP process is applied to the manufacture of a semiconductor device, a double mask pattern of the first mask pattern and the second mask pattern is used, so that a fine pattern for the semiconductor device can be obtained.

  However, in the SADP process for forming the first mask pattern and the second mask pattern, when the second mask pattern is formed, the hard mask film is not sufficiently removed and is often generated as a residue. Occurs. In particular, the residue occurs more frequently in the portion where the pattern having the corner structure is located in the first mask pattern. The reason for this is that when the hard mask film is removed for forming the second mask pattern, the removal amount (etching amount) of the hard mask film at the inner portion of the pattern having the corner structure and the inner portion of the pattern having the corner structure This is because the removal amount (etching amount) of the hard mask film is different from the other portions except for.

  As described above, conventionally, when a fine pattern is formed by applying the SADP process, there is a problem that a desired fine pattern cannot be easily formed because a frequent occurrence occurs.

A first object of the present invention is to provide a mask pattern forming method which can be applied when a fine pattern is formed.
A second object of the present invention is to provide a method for forming a fine pattern using the mask pattern described above.

In order to achieve the first object, a method for forming a mask structure according to the present invention includes a first mask pattern having a plurality of mask pattern portions having openings at the top of a substrate and a corner portion having curved inner walls. A first mask including two mask patterns is formed. Then, after a sacrificial film is continuously formed on the first mask, a hard mask film is formed on the sacrificial film. Thereafter, the hard mask film is partially removed until the entire side wall of the sacrificial film adjacent to the corner portion is exposed so that the side wall of the sacrificial film adjacent to the opening is not at least partially exposed . Then, the sacrificial film is removed. Then, a second mask is formed from the hard mask film pattern remaining in the opening.
Accordingly, a mask structure including the first mask and the second mask is formed on the semiconductor substrate. That is, a double mask pattern suitable for forming a fine pattern is formed.

According to another aspect of the present invention, there is provided a fine pattern forming method comprising: forming a first mask pattern having a plurality of mask pattern portions having openings on an interlayer insulating film after forming an interlayer insulating film on the substrate; A first mask including a second mask pattern having a corner portion having a curved inner wall is formed. Then, after a sacrificial film is continuously formed on the first mask, a hard mask film is formed on the sacrificial film. Thereafter, the hard mask film is partially removed until the entire surface of the sacrificial film adjacent to the corner is exposed so that the side wall of the sacrificial film adjacent to the opening is not at least partially exposed . Then, the sacrificial film is removed. Then, a second mask is formed from the hard mask film pattern remaining in the opening. That is, a mask structure including a first mask and a second mask is formed on the semiconductor substrate. Then, an etching process using the first mask and the second mask as an etching mask is performed. Thereby, the interlayer insulating film is formed in an interlayer insulating film pattern.
In particular, in the present invention, since the interlayer insulating film pattern is formed using the mask structure including the first mask and the second mask, that is, the double mask pattern, the interlayer insulating film pattern having a finer structure can be formed. It is.

As described above, according to the present invention, the second mask pattern including the corner portion having the curved inner wall is formed on the first mask. Thereby, the thickness of the hard mask film can be reduced adjacent to the corner portion. Therefore, etching can be performed until the surface of the sacrificial film adjacent to the corner portion is exposed. As a result, the residue hardly occurs in the removal of the hard mask film for forming the second mask. Further, since the removal amount of the hard mask film at the portion adjacent to the corner portion and the portion other than the corner portion, that is, the etching amount is almost similar, no problem due to over-etching occurs.
Therefore, when the method of the present invention is applied to the manufacture of a semiconductor device, a finer pattern can be easily obtained.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein, and may be embodied in other forms. The embodiments presented herein are provided so that the disclosed content will be thorough and complete, and will fully convey the spirit of the invention to those skilled in the art. In the drawings, the thickness and size of thin films and regions are exaggerated for clarity. Also, when a thin film is referred to as being on another thin film or substrate, it can be formed directly on the other thin film or substrate, or a third thin film can be interposed between them. it can.

(Method for forming mask structure)
1 to 5 are cross-sectional views illustrating a method of forming a mask structure according to an embodiment of the present invention, FIG. 6 is a plan view illustrating a first mask illustrated in FIG. 1, and FIG. It is a perspective view which shows the state when removing a hard mask film | membrane in FIG.
As shown in FIG. 1, a first mask 120 is formed on the substrate 100.
Here, examples of the substrate 100 to be applied include semiconductor substrates such as a silicon substrate, a silicon on insulator (SOI) substrate, a germanium substrate, a germanium on insulator (GOI) substrate, a silicon germanium substrate, and the like. In this embodiment, a silicon substrate is mainly used as the substrate 100. Examples of a material that can be used as the first mask 120 include polysilicon. This is because the first mask 120 must have an etching selectivity different from that of a sacrificial film, which will be described later. The first mask 120 is formed by performing a photolithography process or the like.

  The first mask 120 is formed on the substrate 100 so as to have a first mask pattern 121 and a second mask pattern 123. The first mask pattern 121 includes a plurality of mask pattern portions. The plurality of mask pattern portions are formed so as to be spaced apart from each other and have an opening 130 therebetween. The second mask pattern 123 is formed to include a corner portion 125 having a curved inner wall. At this time, the curvature of the corner portion 125 is preferably formed from about 30 ° to 70 °, and more preferably about 45 °.

The corner portion 125 having a curved inner wall can reduce the occurrence of residue in the corner portion 125 of the second mask pattern portion 123 in a subsequent process for removing the hard mask film.
The second mask pattern 123 is formed by a photolithography process. Therefore, by adjusting the layout of the first mask 120, the second pattern 123 can be easily formed to include the corner portion 125 having the curved inner wall.

  As shown in FIG. 2, after the first mask 120 including the first mask pattern 121 and the second mask pattern 123 is formed, a sacrificial layer 140 is formed on the resultant structure on which the first mask 120 is formed.

  Here, the sacrificial layer 140 must be continuously formed on the surface of the first mask 120. That is, the sacrificial layer 140 is formed on the upper surface and sidewalls of the first mask 120 and the exposed surface of the substrate 100, respectively. The sacrificial film 140 is formed to have a substantially uniform thickness.

  The sacrificial film 140 is formed by performing a chemical vapor deposition process or an atomic layer deposition process. When the sacrificial film 140 is formed by the atomic layer stacking process, the sacrificial film is formed with a constant thickness. When the sacrificial film 140 is formed by an atomic layer stacking process, the atomic layer stacking process can provide good step coverage by adjusting the thickness of the sacrificial film 140.

The sacrificial layer 140 must have a different etching selectivity than the first mask 120. Accordingly, examples of a material that can be used as the sacrificial film 140 include metal oxides such as tungsten oxide, tantalum oxide, and titanium oxide.
In one embodiment of the present invention, the sacrificial film 140 may be a metal oxide film obtained by performing an atomic layer stacking process.

As shown in FIG. 3, after a sacrificial film 140 is formed on the resultant structure including the first mask 120, a hard mask film 160 is formed on the sacrificial film 140.
Here, the hard mask layer 160 must have the same etching selectivity as the first mask 120. This is because the second mask pattern formed by patterning the hard mask film 160 is used as an etching mask in the same process as the first mask 120. Accordingly, the hard mask film 160 includes the same material as the first mask 120. Accordingly, when the first mask 120 is formed of polysilicon, examples of a material that can be used as the hard mask film 160 include polysilicon.

The hard mask film 160 and the first mask 120 for obtaining the second mask pattern have the same etching selectivity. However, the sacrificial layer 140 has an etching selectivity different from that of the first mask 120. Therefore, the sacrificial film 140 has an etching selectivity different from that of the hard mask film 160. Accordingly, the first mask 120 and the hard mask film 160 include the same material such as polysilicon, and the sacrificial film 140 includes a metal oxide or the like.
In the above description, the materials constituting the first mask 120, the hard mask film 160, and the sacrificial film 140 are specifically limited. However, when the etching selectivity mentioned above is satisfied, other materials may be applied. Also good.

  As shown in FIG. 4, after the hard mask film 160 is formed on the first mask 120, the hard mask film 160 is partially removed, and a hard mask pattern 180 is formed in the opening 130. That is, the etching process is performed on the hard mask film 160. At this time, the removal of the hard mask film 160 is mainly performed by whole surface etching (etch back), specifically, isotropic etching. In particular, the isotropic etching is performed in the removal of the hard mask film 160 in order to alleviate the formation of the side well on the side wall of the portion where the first mask 120 is located. That is, when the hard mask film 160 is removed by performing anisotropic etching, there is a problem that a side well is likely to be generated on a side wall or the like of a portion where the first mask 120 is located.

  When the hard mask film 160 is removed, the hard mask film 160 is removed until the side wall of the sacrificial film 140 adjacent to the corner portion 125 (see FIG. 6) having a curved inner wall is partially exposed. Set the condition. That is, the hard mask film 160 is removed under a process condition in which the time when the sacrificial film 140 adjacent to the corner portion 125 of the second mask pattern 123 of the first mask 120 is exposed is an etching end point.

The removal amount (etching amount) of the hard mask film 160 adjacent to the corner portion 125 of the second mask pattern 123 and the etching amount of the hard mask film 160 formed on the second mask pattern 123 are substantially matched. Can do. That is, as shown in FIG. 7, the hard mask film 160 is formed to have a first portion adjacent to the corner portion 125 and a second portion separated from the corner portion 125. The first etching thickness D1 of the first part is substantially the same as the second etching thickness D2 of the second part. Therefore, when the hard mask film 160 is removed until the side wall of the sacrificial film 140 adjacent to the corner portion 125 (see FIG. 6) of the second mask pattern 123 is exposed, almost no residue is generated, and only the hard mask is formed in the opening 130. A film 18a is selectively formed.
Thus, in one embodiment of the present invention, when the second mask pattern 123 includes a curved corner portion, when the hard mask film 160 for obtaining a second mask pattern to be described later is removed, the residue is reduced to the corner portion. Almost no residue in the neighborhood of 125.

  As shown in FIG. 5, after partially removing the hard mask film 160 from the substrate 100, the sacrificial film 140 is removed from the substrate 100. That is, a part of the exposed sacrificial film 140 is removed by removing a part of the hard mask film 160.

  Thus, by removing the sacrificial film 140, the hard mask film pattern 180 remaining in the opening 130 is formed as the second mask 185. As a result, a mask structure including the first mask 120 and the second mask 185 is formed on the substrate 100.

  In particular, in the present embodiment, the second mask pattern 123 is formed so as to include a curved corner portion 125 having a predetermined curvature, and the corner portion 125 is appropriately used as described above so that the corner portion 125 is formed. The second mask 185 can be obtained in a state where there is almost no adjacent residue.

  Therefore, when the method for forming a mask structure in this embodiment is applied to the manufacture of a semiconductor device, there is almost no defect due to residue or the like when forming a fine pattern. Therefore, the mask structure forming method of this embodiment can be positively applied to the recent manufacture of semiconductor devices that require fine patterns.

(Fine pattern formation method)
8 to 10 are cross-sectional views illustrating a fine pattern forming method according to an embodiment of the present invention. The process of forming the mask structure in FIGS. 8 to 10 is substantially the same as the process described in FIGS. Therefore, the same reference numerals as those in FIGS. 1 to 5 are used as the reference numerals in FIGS.

  As shown in FIG. 8, an interlayer insulating film 110 is formed on the substrate 100. Here, the interlayer insulating film 110 must have an etching selectivity different from that of the first mask 120, the second mask 185, and the sacrificial film 140 described above. The reason is that the first mask 120 and the second mask 185 are used as an etching mask when the interlayer insulating film 110 is formed as an interlayer insulating film pattern to be described later, and when the sacrificial film 140 is removed, the interlayer insulating film is used. This is because 110 is exposed. In particular, the interlayer insulating film 110 must have a function of an etching stopper film when the sacrificial film 140 is removed.

Therefore, as described above, when the first mask 120 and the second mask 185 include polysilicon and the sacrificial film 140 includes a metal oxide such as tungsten oxide or titanium oxide, the interlayer insulating film 110 is formed of silicon oxide. It is preferable that a thing is included.
Therefore, in this embodiment, the interlayer insulating film 110 is formed by performing a thermal oxidation process, a radical oxidation process, or a chemical vapor deposition process on silicon oxide. For example, the interlayer insulating film is formed by a chemical vapor deposition process.

  As illustrated in FIG. 9, the first mask 120 and the second mask 185 are formed on the interlayer insulating film 110 by performing the steps described with reference to FIGS. 1 to 5. That is, a mask structure including the first mask 120 and the second mask 185 is formed on the interlayer insulating film 110. The mask structure is referred to as a double mask pattern.

In particular, in this embodiment, the first mask 120 and the second mask 185 are formed by performing the steps described with reference to FIGS. Therefore, when the first mask 120 and the second mask 185 are formed, almost no residue is generated.
As shown in FIG. 10, an etching process is performed using a double mask pattern including a first mask 120 and a second mask 185 as an etching mask. Thereby, an interlayer insulating film pattern 112 is formed on the semiconductor substrate 100.

As mentioned above, according to the present embodiment, since the interlayer insulating film pattern 112 is formed using the double mask pattern including the first mask 120 and the second mask 185 in which almost no residue is generated, in an environment in which defects hardly occur. A pattern having a fine structure can be easily formed.
Although not shown, after the interlayer insulating film pattern 42 is formed, a process of forming a fine pattern using the interlayer insulating film pattern 42 as a mold film can be additionally performed.
(Industrial applicability)

As described above, in the present invention, the first mask and the second mask structure in which almost no residue is generated can be easily formed. Further, by applying the mask structure that hardly generates the mentioned residue to the manufacture of a semiconductor device, a pattern with a finer structure can be easily formed.
Therefore, the present invention can be positively applied to the manufacture of recent semiconductor devices that require a fine structure, and as a result, improvement in reliability due to the manufacture of semiconductor devices can be expected.

  As described above, the embodiments of the present invention have been described in detail. However, the present invention is not limited to the embodiments, and as long as it has ordinary knowledge in the technical field to which the present invention belongs, without departing from the spirit and spirit of the present invention, The present invention can be modified or changed.

It is sectional drawing which shows the formation method of the mask structure by one Example of this invention. It is sectional drawing which shows the formation method of the mask structure by one Example of this invention. It is sectional drawing which shows the formation method of the mask structure by one Example of this invention. It is sectional drawing which shows the formation method of the mask structure by one Example of this invention. It is sectional drawing which shows the formation method of the mask structure by one Example of this invention. It is a top view which shows the 1st mask of FIG. FIG. 5 is a perspective view showing a state when the hard mask film is removed in FIG. 4. It is sectional drawing which shows the formation method of the fine pattern by one Example of this invention. It is sectional drawing which shows the formation method of the fine pattern by one Example of this invention. It is sectional drawing which shows the formation method of the fine pattern by one Example of this invention.

Explanation of symbols

  100: semiconductor substrate, 110: interlayer insulating film, 112: interlayer insulating film pattern, 120: first mask, 125: corner portion, 140: sacrificial film, 160: hard mask film, 185: second mask

Claims (12)

  1. Forming a first mask including a first mask pattern provided with a plurality of mask pattern portions having openings and a second mask pattern having curved corner portions on an upper portion of the substrate;
    Continuously forming a sacrificial layer on the first mask;
    Forming a hard mask film on the sacrificial film;
    Partially removing the hard mask film until the entire sidewall of the sacrificial film adjacent to the corner portion is exposed such that the sidewall of the sacrificial film adjacent to the opening is not at least partially exposed ;
    Removing the sacrificial film and forming a second mask from the hard mask film remaining in the opening;
    A method of forming a mask structure including:
  2.   The mask structure according to claim 1, wherein the first mask and the second mask have substantially the same etching selectivity, and the sacrificial film has an etching selectivity different from that of the first mask. Forming method.
  3.   The method of claim 1, wherein the first mask and the second mask are formed of the same material, and the sacrificial film is formed of a material different from the first mask pattern.
  4.   4. The method of forming a mask structure according to claim 3, wherein the first mask and the second mask are formed of polysilicon, and the sacrificial film is formed of a metal oxide.
  5.   2. The method of forming a mask structure according to claim 1, wherein an atomic layer stacking step is performed in the step of forming the sacrificial film.
  6.   2. The method of forming a mask structure according to claim 1, wherein isotropic etching is performed in the step of partially removing the hard mask film.
  7. Forming an interlayer insulating film on the substrate;
    Forming a first mask including a first mask provided with a plurality of mask pattern portions having openings and a second mask pattern provided with corner portions having curved inner walls on the interlayer insulating film; ,
    Continuously forming a sacrificial layer on the first mask;
    Forming a hard mask film on the sacrificial film;
    The method comprising the side wall of the sacrificial layer adjacent to said opening to remove the hard mask layer to expose the entire sidewall of the sacrificial film adjacent to the corner portion so as not to at least partially exposed partially,
    Removing the sacrificial film and forming a second mask from the hard mask film remaining in the opening;
    Partially etching the interlayer insulating film using the first mask and the second mask as an etching mask to form the interlayer insulating film in an interlayer insulating film pattern;
    A fine pattern forming method comprising:
  8.   8. The method of claim 7, wherein the first mask and the second mask have the same etching selectivity, and the interlayer insulating film and the sacrificial film both have an etching selectivity different from that of the first mask. Fine pattern forming method.
  9.   8. The method of forming a fine pattern according to claim 7, wherein the first mask and the second mask contain the same material, and the interlayer insulating film and the sacrificial film both contain a material different from the first mask.
  10.   The method of claim 9, wherein the first mask and the second mask include polysilicon, the interlayer insulating film includes silicon oxide, and the sacrificial film includes metal oxide.
  11.   8. The method for forming a fine pattern according to claim 7, wherein the sacrificial film is formed by atomic layer lamination.
  12.   8. The method for forming a fine pattern according to claim 7, wherein the hard mask film is removed by isotropic etching.
JP2006289669A 2006-08-29 2006-10-25 Method for forming mask structure and method for forming fine pattern using the same Active JP5105824B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR10-2006-0082119 2006-08-29
KR1020060082119A KR100763538B1 (en) 2006-08-29 2006-08-29 Method of forming mask pattern and method of forming fine pattern using the same in a semiconductor device fabricating

Publications (2)

Publication Number Publication Date
JP2008060517A JP2008060517A (en) 2008-03-13
JP5105824B2 true JP5105824B2 (en) 2012-12-26

Family

ID=39152165

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006289669A Active JP5105824B2 (en) 2006-08-29 2006-10-25 Method for forming mask structure and method for forming fine pattern using the same

Country Status (4)

Country Link
US (1) US7452825B2 (en)
JP (1) JP5105824B2 (en)
KR (1) KR100763538B1 (en)
CN (1) CN101135840B (en)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7611944B2 (en) 2005-03-28 2009-11-03 Micron Technology, Inc. Integrated circuit fabrication
KR100648859B1 (en) * 2005-06-07 2006-11-16 주식회사 하이닉스반도체 Method for manufacturing semiconductor device
US7572572B2 (en) 2005-09-01 2009-08-11 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US7393789B2 (en) 2005-09-01 2008-07-01 Micron Technology, Inc. Protective coating for planarization
US7488685B2 (en) 2006-04-25 2009-02-10 Micron Technology, Inc. Process for improving critical dimension uniformity of integrated circuit arrays
KR100735535B1 (en) * 2006-07-10 2007-06-28 삼성전자주식회사 Manufacturing method of mask
US7611980B2 (en) 2006-08-30 2009-11-03 Micron Technology, Inc. Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US8563229B2 (en) 2007-07-31 2013-10-22 Micron Technology, Inc. Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures
US7790531B2 (en) 2007-12-18 2010-09-07 Micron Technology, Inc. Methods for isolating portions of a loop of pitch-multiplied material and related structures
US8492282B2 (en) * 2008-11-24 2013-07-23 Micron Technology, Inc. Methods of forming a masking pattern for integrated circuits
US8133664B2 (en) * 2009-03-03 2012-03-13 Micron Technology, Inc. Methods of forming patterns
FR2954584B1 (en) * 2009-12-22 2013-07-19 Commissariat Energie Atomique Hybrid substrate with improved insulation and method for simplified realization of a hybrid substrate
CN101872119A (en) * 2010-06-08 2010-10-27 电子科技大学 Preparation method of sacrificial layer structure with gentle slope
CN102880291A (en) * 2012-09-06 2013-01-16 中国科学院计算技术研究所 Braille inputting device and method based on micro button switch
CN104425225A (en) * 2013-09-04 2015-03-18 中芯国际集成电路制造(上海)有限公司 Forming method for triple graphs
US9455178B2 (en) * 2014-03-14 2016-09-27 Taiwan Semiconductor Manufacturing Company, Ltd. Method of semiconductor integrated circuit fabrication
US9754910B2 (en) * 2014-06-05 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of packaging semiconductor devices and packaged semiconductor devices
KR20170051003A (en) 2015-11-02 2017-05-11 삼성전자주식회사 Semiconductor device and method of manufacturing the same
CN108666207A (en) 2017-03-29 2018-10-16 联华电子股份有限公司 The method for making semiconductor element
CN109216167A (en) 2017-07-04 2019-01-15 联华电子股份有限公司 patterning method

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0586659B2 (en) * 1982-10-27 1993-12-13 Nippon Telegraph & Telephone
WO1996002070A2 (en) * 1994-07-12 1996-01-25 National Semiconductor Corporation Integrated circuit comprising a trench isolation structure and an oxygen barrier layer and method for forming the integrated circuit
KR100248356B1 (en) 1997-06-30 2000-05-01 김영환 Method for semiconductor device
US5959325A (en) * 1997-08-21 1999-09-28 International Business Machines Corporation Method for forming cornered images on a substrate and photomask formed thereby
US5939335A (en) 1998-01-06 1999-08-17 International Business Machines Corporation Method for reducing stress in the metallization of an integrated circuit
TW442972B (en) * 1999-10-01 2001-06-23 Anpec Electronics Corp Fabricating method of trench-type gate power metal oxide semiconductor field effect transistor
JP2001135565A (en) * 1999-11-08 2001-05-18 Sony Corp Method of fabrication for semiconductor device
US6584609B1 (en) * 2000-02-28 2003-06-24 Numerical Technologies, Inc. Method and apparatus for mixed-mode optical proximity correction
US6667237B1 (en) * 2000-10-12 2003-12-23 Vram Technologies, Llc Method and apparatus for patterning fine dimensions
US6884733B1 (en) * 2002-08-08 2005-04-26 Advanced Micro Devices, Inc. Use of amorphous carbon hard mask for gate patterning to eliminate requirement of poly re-oxidation
JP2004093705A (en) 2002-08-29 2004-03-25 Fujitsu Ltd Method for correcting mask pattern
JP2004296930A (en) * 2003-03-27 2004-10-21 Nec Electronics Corp Pattern forming method
JP2004004904A (en) 2003-06-23 2004-01-08 Matsushita Electric Ind Co Ltd Correction method for figure pattern for semiconductor device, and manufacturing method for the semiconductor device
KR101072514B1 (en) 2004-04-09 2011-10-11 에이에스엠엘 마스크툴즈 비.브이. Optical proximity correction using chamfers and rounding at corners
KR100614651B1 (en) 2004-10-11 2006-08-22 삼성전자주식회사 Apparatus And Method For Pattern Exposure, Photomask Used Therefor, Design Method For The Photomask, Illuminating System Therefor and Implementing Method For The Illuminating System
KR100640640B1 (en) 2005-04-19 2006-10-31 삼성전자주식회사 Method of forming fine pattern of semiconductor device using fine pitch hardmask
US7230287B2 (en) * 2005-08-10 2007-06-12 International Business Machines Corporation Chevron CMOS trigate structure
KR100861212B1 (en) * 2006-02-24 2008-09-30 주식회사 하이닉스반도체 Method for forming fine patterns of semiconductor devices
JP4772618B2 (en) * 2006-07-31 2011-09-14 東京応化工業株式会社 Pattern forming method, metal oxide film forming material and method of using the same

Also Published As

Publication number Publication date
CN101135840A (en) 2008-03-05
US20080057610A1 (en) 2008-03-06
KR100763538B1 (en) 2007-10-05
CN101135840B (en) 2011-05-18
JP2008060517A (en) 2008-03-13
US7452825B2 (en) 2008-11-18

Similar Documents

Publication Publication Date Title
JP3406302B2 (en) Method of forming a fine pattern, a method of manufacturing a semiconductor device and a semiconductor device
KR20110055912A (en) Method for forming fine pattern in semiconductor device
JP5134760B2 (en) Manufacturing method of recess channel array transistor using mask layer having high etching selectivity with silicon substrate
JP2006303500A (en) Fine pattern formation method of semiconductor device using fine-pitch hard mask
JP4653735B2 (en) Process for forming a dual metal gate structure
JP4599578B2 (en) Method for suppressing pattern deformation and photomask contamination in semiconductor device manufacturing process
CN1292468C (en) Methods of simultaneously fabricating isolation structures having varying dimensions
US20020061616A1 (en) Method for fabricating semiconductor device
US8927353B2 (en) Fin field effect transistor and method of forming the same
TWI356446B (en) Methods to reduce the critical dimension of semico
JP2004080033A (en) Method of micropattern formation using silicon oxide film
US20070111467A1 (en) Method for forming trench using hard mask with high selectivity and isolation method for semiconductor device using the same
US5688704A (en) Integrated circuit fabrication
US7442607B2 (en) Method of manufacturing transistor having recessed channel
WO2008005612A1 (en) Method for forming a semiconductor device and structure thereof
JP4466668B2 (en) Manufacturing method of semiconductor device
JP4737953B2 (en) Manufacturing method of semiconductor device
EP1387395B1 (en) Method for manufacturing semiconductor integrated circuit structures
TWI335615B (en) Method for fabricating semiconductor device using arf photolithography capable of protecting tapered profile of hard mask
US7265013B2 (en) Sidewall image transfer (SIT) technologies
KR100574999B1 (en) Method of forming pattern of semiconductor device
KR100187678B1 (en) Method of forming an element isolation film in a semiconductor device
US20110159691A1 (en) Method for fabricating fine patterns of semiconductor device utilizing self-aligned double patterning
US8389400B2 (en) Method of manufacturing fine patterns of semiconductor device
US7803709B2 (en) Method of fabricating pattern in semiconductor device using spacer

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20091019

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20111031

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20111108

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120207

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120907

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20121002

R150 Certificate of patent or registration of utility model

Ref document number: 5105824

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20151012

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250