JPH0526326B2 - - Google Patents

Info

Publication number
JPH0526326B2
JPH0526326B2 JP59149819A JP14981984A JPH0526326B2 JP H0526326 B2 JPH0526326 B2 JP H0526326B2 JP 59149819 A JP59149819 A JP 59149819A JP 14981984 A JP14981984 A JP 14981984A JP H0526326 B2 JPH0526326 B2 JP H0526326B2
Authority
JP
Japan
Prior art keywords
torr
autodoping
area ratio
pressure
arsenic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59149819A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60101928A (ja
Inventor
Kumaaru Geindo Aran
Barukurishina Kurukaruni Subashu
Robaato Hohonyatsuku Maikeru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS60101928A publication Critical patent/JPS60101928A/ja
Publication of JPH0526326B2 publication Critical patent/JPH0526326B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/2205Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities from the substrate during epitaxy, e.g. autodoping; Preventing or using autodoping
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/914Doping
    • Y10S438/916Autodoping control or utilization

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Bipolar Transistors (AREA)
JP59149819A 1983-10-19 1984-07-20 エピタキシヤル層の形成方法 Granted JPS60101928A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/543,555 US4504330A (en) 1983-10-19 1983-10-19 Optimum reduced pressure epitaxial growth process to prevent autodoping
US543555 2006-10-05

Publications (2)

Publication Number Publication Date
JPS60101928A JPS60101928A (ja) 1985-06-06
JPH0526326B2 true JPH0526326B2 (OSRAM) 1993-04-15

Family

ID=24168529

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59149819A Granted JPS60101928A (ja) 1983-10-19 1984-07-20 エピタキシヤル層の形成方法

Country Status (4)

Country Link
US (1) US4504330A (OSRAM)
EP (1) EP0139990B1 (OSRAM)
JP (1) JPS60101928A (OSRAM)
DE (1) DE3476492D1 (OSRAM)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63185061A (ja) * 1987-01-28 1988-07-30 Toshiba Corp 半導体装置の製造方法
JPH01161826A (ja) * 1987-12-18 1989-06-26 Toshiba Corp 気相エピタキシャル成長法
FR2766845B1 (fr) * 1997-07-31 1999-10-15 Sgs Thomson Microelectronics Procede d'epitaxie sur un substrat de silicium comprenant des zones fortement dopees a l'arsenic
US6612240B1 (en) 2000-09-15 2003-09-02 Silverbrook Research Pty Ltd Drying of an image on print media in a modular commercial printer

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3669769A (en) * 1970-09-29 1972-06-13 Ibm Method for minimizing autodoping in epitaxial deposition
US3765960A (en) * 1970-11-02 1973-10-16 Ibm Method for minimizing autodoping in epitaxial deposition
US4153486A (en) * 1978-06-05 1979-05-08 International Business Machines Corporation Silicon tetrachloride epitaxial process for producing very sharp autodoping profiles and very low defect densities on substrates with high concentration buried impurity layers utilizing a preheating in hydrogen
US4263336A (en) * 1979-11-23 1981-04-21 Motorola, Inc. Reduced pressure induction heated reactor and method

Also Published As

Publication number Publication date
DE3476492D1 (en) 1989-03-02
JPS60101928A (ja) 1985-06-06
US4504330A (en) 1985-03-12
EP0139990A2 (en) 1985-05-08
EP0139990B1 (en) 1989-01-25
EP0139990A3 (en) 1985-08-28

Similar Documents

Publication Publication Date Title
US3966577A (en) Dielectrically isolated semiconductor devices
US4717681A (en) Method of making a heterojunction bipolar transistor with SIPOS
US3664896A (en) Deposited silicon diffusion sources
US3861968A (en) Method of fabricating integrated circuit device structure with complementary elements utilizing selective thermal oxidation and selective epitaxial deposition
JPH0697666B2 (ja) マルチレベル・エピタキシャル構造を用いた半導体デバイス構造体及びその製造方法
US3558375A (en) Variable capacity diode fabrication method with selective diffusion of junction region impurities
US3149395A (en) Method of making a varactor diode by epitaxial growth and diffusion
JPH04230037A (ja) インサイチュ・ドープされたn型シリコン層の付着方法およびNPNトランジスタ
JPS6063961A (ja) 半導体装置の製造方法
US3165811A (en) Process of epitaxial vapor deposition with subsequent diffusion into the epitaxial layer
US4338481A (en) Very thin silicon wafer base solar cell
US3753803A (en) Method of dividing semiconductor layer into a plurality of isolated regions
US4408386A (en) Method of manufacturing semiconductor integrated circuit devices
US4859626A (en) Method of forming thin epitaxial layers using multistep growth for autodoping control
JP3079575B2 (ja) 半導体装置の製造方法
JP2906260B2 (ja) Pn接合素子の製造方法
EP0051534B1 (en) A method of fabricating a self-aligned integrated circuit structure using differential oxide growth
US3345222A (en) Method of forming a semiconductor device by etching and epitaxial deposition
US3850707A (en) Semiconductors
JP2911694B2 (ja) 半導体基板及びその製造方法
US4404048A (en) Semiconductor device manufacture
US4164436A (en) Process for preparation of semiconductor devices utilizing a two-step polycrystalline deposition technique to form a diffusion source
JPH0526326B2 (OSRAM)
US4128440A (en) Liquid phase epitaxial method of covering buried regions for devices
US3986904A (en) Process for fabricating planar scr structure